Two Basic Components of a Computer

>Primary storage or Memory

>CPU (Central Processing Unit)
CPU
Start

Fetch
Instruction
Interpret
Instruction

Process Data

Write Data

End

Computer Architecture it refers to those attributes that is visible to the

programmer
-

Those attributes that have a direct impact on the logical

execution of program
Physical Attributes of a computer
It is an architectural design issue whether a computer will have
a multiply instruction

Architectural Attributes

Instruction Set
Number of bits used to represent various data
I/O mechanisms
Techniques for addressing memory

Computer Organization > it refers to the operational units and their

interconnections that realize the architectural specifications
Organizational Attributes > hardware details transparent to those programmer such
as:
Control signals
Interfaces between the computer and its peripherals
Memory technology used
Function
The operation of each individual component as part of the structure
The four basic function of a computer can perform:

Data Processing
Data Storage
Data Movement
Control

Functional View of a computer

Operating Environment Data Movement Apparatus

Control Mechanism

Data Storage Facility

Data Processing Facility

Structure
The way in hic the components are interrelated
The computer interacts in some fashion with its external environment
In general all of its linkages to the external environment can be classified
as peripheral devices or communication lines
Simple Description of a computer
Peripherals Computer storage, processing Communication lines

Top level structure of a Computer

Computer
I/O

Main Memory
System Interconnection
CPU

CPU
Registers

ALU

Internal Interconnection
Control Unit

Control Unit
Sequential Logic

Control Memory

Central Unit Registers and Decoders

CPU controls the operation of the computer & performs the data processing
function
Main Memory stores data
I/O Device moves data between the computer and its external environment
System Interconnection mechanisms that provides for communication among CPU,
main memory, I/O
Control Unit controls the operation of the CPU and hence the computer
ALU performs the computers data processing functions
Registers provides storage internal to the CPU
CPU Interconnection mechanism that provides for communication using the
control unit ALU and Register

SAP-1 (Simple as possible) all registers outputs to the W-bus are three state; this
allows orderly communication and data transfer. All register outputs not connected
to the W-bus are two states, these output continuously drive the boxes they are
connected to.
-

Is to show all the crucial ideas behind computer operation

without burying you in unnecessary detail

Program Counter (PC) counts from 0000 to 1111, equivalent to 0 through F. the pc
reset to 0 before each run
Memory Address Registers (MAR) receive binary address from the program
counter
Read Only Memory (ROM) you can store any 16 words of 8 bits of data or
instructions
Instruction Registers (IR) gets the data or information from the ROM and then
loaded into the IR

- Two components are MSB and LSB

MSB (Most Significant Bit) is a two state output that goes directly to the
control unit
LSB (Least Significant Bit) are a three state output that is read onto the Wbus

Control Unit (CON) an automatic data processing machine which instruct all of the
registers
Accumulator (A) it has two outputs, one directly goes to the ALU while the other
output goes to the W-bus
ALU (Arithmetic Logic Unit) it performs all of the operation such as addition and
subtraction
B-register (B) temporary storage when accumulator has a data/information. H is
also connected to the ALU
Output Registers (O) it gets the answer to the accumulator then shows it to the
binary display
Binary Display (D) shows the answer in binary form of LEDS

PC

8
A
8

MAR

4
8

4
RO
M

ALU
8

8
8

IR

O
8

CON

12

Instruction Set step by step instructions into the memory before the start of a
computer run
LDA means load the accumulator
Ex. LDA R8; R8=1111 0000
Then A=1111 0000
ADD means to add a specific content to the content of the accumulator
Ex. ADD R9; R9 = 0000 0011; A=0000 0010 then the content of R9 will go to the B
register; B=0000 0011 then ALU forms the sum of A and B: ALU=0000 0101 Lastly
ALU contents are loaded into the accumulator A=0000 0101
SUB means subtract a specific content to the content of the accumulator
Ex. SUB Rc; Rc=0000 0011; A=0000 0111 then the content of Rc will go to the B
register B=0000 0011 then ALU forms the subtraction of A and B ALU=0000 0100
lastly ALU contents are loaded into the Accumulator A=0000 0100
OUT tells the computer to transfer the accumulator contents to the output
registers
HLT stands for Halt
-

Tells the computer to stop processing data

Marks the end of a program

Mnemonics are the instruction set that are being abbreviated

Ex. LDA, OUT, ADD, SUB, HLT
Operation Code also called as OPCODE, go into the four msb positions
Opcode table
Mnemonics opcode
LDA

0000

ADD

0001

SUB

0010

OUT

1110

HLT

1111

Machine Cycle
*Cycle
takes place every time a program runs
- an instruction need 6 cycles to be completed
*Fetch Cycle
- is the first 3 cycle that takes place every time an instruction was executed
*Execution Cycle
- the last 3 cycles which takes place after the fetch cycle
Ring Counter
-

The ring counter which is part of SAP1s control unit has an output of
T=T6T5T4T3T2T1 at the beginning of the computer run, the ring word is
T=000001
T1: 000 001
T4: 001 000
T2: 000 010Fetch T5: 010 000 Execution
T3: 000 100Code T6: 100 000 Code
Then the ring resets to 000001 and the cycle repeats. Each ring word
represents one machine phase
Each instruction is fetched and executed during the 6 phases
Fetch Cycle

T1 State (Address State) the address in program counter (PC) us

transferred to the memory register (MAR) during this state, Ep and Lm are
active while other control bits are inactive
T2 State (Memory State) the addressed ROM instructions is
transferred from the memory to the Instruction Register (IR). During this state
Er and Lt are active while other control bits are inactive
T3 State (Increment State) the program counter is incremented so
that the next instruction was performed, only Cp is active during this phase
Note: The Fetch Cycle is the same for all instructions in SAP1 computers
Execution Cycle
>LDA Runtime (T4 State)
Instruction

address

Field

field

Assuming that the instruction register (IR) has been loaded with LDA R9
IR = 0000 1001
The instruction field goes to the control unit (CON) where it is decoded
The address field goes w/ MAR
Note: Ei and Lm are active > after this state the contents of the registers will
be:
CON : 0010 0100 0000 (Base 2)
CON : 240H
IR: 0000 1001
MAR: 1001
>LDA Runtime (T5)
> Er and La go low. This means the addressed data word in the ROM will be
loaded into the accumulator (A)
> after this state the contents of the register will be:
CON: 0001 0010 0000
CON 120H

A: 0000 1001

LDA Routine (T6)

> T6 is no operation (NOP) during this state all registers are inactive
Note: If the previous instruction has no operation the next instruction will only
be executed after 6T states was processed.

Add Runtime (T4)

Surface at the end of the fetch cycle the instruction register contains:
ADD Rb: IR = 0001 1011
The instruction field goes to the MAR
Er and La are active
After this state the contents of the registers will be:
CON: 0010 0100 0000
CON: 240H
B: 10H
Add Runtime (T5)
Er and La are active, this allows the address word to set up the B register:
After this state the contents of the register will be:
CON: 0001 0000 0010
CON: 102H
B: 0000 1011
Add Routine (T6)
Eu and La are active. The adder/subtracter of the Ax
The output will be stored in the Ax until the controller receives instructions
to place the output somewhere else, the output register for instance
After this state the contents of the register will be:
CON: 0000 0010 0100
CON: 024H
CON: (Content of Ax) + (Content of B)
Sub Routine
T4 and T5 is similar to Add Routine
T6 Su is high, means that the function of the Adder/Subtractor should be
subtraction
Out Routine (T4)
Suppose the IR contains the out instructions at the end of the fetch cycle:
IR=1110 XXXX
The instruction field goes to the control unit for decoding the COM, send
out the control word needed to load the Ax contents onto the output
registers(O)

 Ea and Lo are active

o The Ax contents will be loaded into the output during the T4 state
o T5 and T6 are no operations (NOP)
HLT Routine

Doesnt require a control routine because no register are involved in

execution of HLT instructions
If IR- 1111 XXXX, the instruction field signals the control unit to stop the
computer and turning off the clock
MAR
4
IR
Machine Cycle for SAP1
CON
4

Instruction Cycle
The # of T states needed to fetch and execute and instruction
WBU
S

ALU
D

>retrieves
B
the data from
8 the
registers
O
L=load
8

8
>opens the
registers to
receive data

*A computer must have instructions capable of performing these:

Four types of instructions

E= enable
8

12

ROM (3 fetch and 3 execution) these states are called

SAP1 has 6 states
machine cycle 8
It takes one machine cycle to fetch and execute each instructions
SAP1 clock has frequency of 1000Hz (1KHz)
T=n/f where t=time, n=# of instruction, f= frequency
It will take 6ms for a SAP1 computer to execute 1 instruction

Data transfer between the main memory and the CPU registers
Arithmetic and logic operations on data
Program sequencing and control
I/O transfers

*Fields the bits of binary instructions that are divided into groups
- common fields found in instruction format
> Operation Code Field that specifies the operation to be performed
> Address Field that designates either a memory address or a code for
choosing a processor registers
> The operation code field of an instruction is a group of bits that define
various processor operations
*Address Field operators specified by computer instructions are executed on some
data stored memory or in processor registers
- Operands rending in memory are specified by their addresses
- The number of address field in the instruction format of a computer depends on
the internal organization of its registers
Types of Organization
Single accumulator organization
Multiple accumulator organization
Stack organization
*Single Accumulator Organization > all operations are performed with the implied
accumulator registers
> The instruction format in the type of computer uses one memory address field
Ex. ADDX
*Multiple Accumulator Organization > a processor unit with multiple register usually
allows for greater programming flexibility
> The instruction format in the type of computer needs B register
*Stack Organization > computers with stack organization have instructions that
require one address field for transferring data to and from the stack
Ex. PUSH, POP
>Notations<

> Infix Notation A+B

>Prefix Notation +AB
>Postfix Notation AB+
*RPN (Reverse Polish Notation) > usually used for evaluating mathematical
operations for stack organizations`
4 Kinds of Instructions
3- Address Instructions
OPCODE
Instruction
Destination

OPER 1
Data Source 1

OPER 2
Data Source 2

OPER 3

*Advantage: Program Disability

*Disadvantage: Long Instruction Word
2- Address Instruction
OPCODE
Instruction

OPER 1
Data Source

OPER 2
Destination

*Advantage: smaller instruction word

*Disadvantage: needs a data transfer to the actual location
1- Address Instruction
OPCODE
Instruction

OPER 1
Data Source

*Advantage: smaller instruction word

*Disadvantage: needs a to be loaded into the accumulator first
0- Address Instruction
OPCODE
Instruction
*Advantage: smaller instruction word
*Disadvantage: data needs to be loaded into the stack first
*+/RD-JM-+ST*QR
RD/JM-+ST+QR*-*