ECE 385

Fall 2015
Experiment 1

Introductory TTL Experiment

Chris Chen
ABD/Tues. 8AM
TA: Bilal Gabula, Benjamin Delay
Introduction

The use of a simple TTL circuit served as an introduction to the equipment and lab process for
this course. It required us to design, build, and test two implementations of the same circuit, a
multiplexer, and explain the differences and issues, if any, for each.

Description of Circuit
The implementation of a 2-1 multiplexer appeared to be more of a review; the main focus of this
lab was rather to explain the existence and consequences of a static hazard. The 2-1 multiplexer
selects and outputs one of two signals based on an input signal. The truth table is shown below.

Figure 1: Truth table for 2-1 multiplexer

Boolean expressions can then be derived from this truth table using a Karnaugh Map. This is
where two implementations of this circuit must be derived, due to a glitch that results from gate
timings.

Figure 2: K-maps for glitched and non-glitched implementations

From these k-maps, we can derive the Boolean expressions Z = BC + BA for the glitched
implementation, and Z = BC + BA + AC.
Logic Diagrams

Figure 3: Basic implementation of a 2-1 multiplexer with NAND gates

Part A discusses the most basic implementation of a 2-1 multiplexer with only NAND gates.
However, this minimal implementation brings up an issue with gate timings the static-1 hazard.
This is due to the three level implementation of this circuit. Inverting the B signal for the BC
component adds an extra level of delay, when compared to the BA component. During this
momentary delay, the circuit produces an output opposite of the intended output when the logic
doesnt consider this delay. Theoretically the output should stay a constant logical 1 when
switching from 101 to 111, but during our testing, a short spike towards 0 was observed at every
falling edge, the aforementioned glitch.

Figure 4: NAND implementation without glitches

Adding this extra AC term reduces the error caused by this delay.

Results

Figure 5: Glitched output

Figure 6: Corrected output

The glitch in figure 5 is clearly evident, it is represented by the momentary spike towards logic 0
on the oscilloscope. Figure 6 is the result when implementing the glitch free multiplexer.
Post-lab Questions
1. Each box spans 20 nanoseconds. Glitches may appear between 0 and 60ns after the first clock
cycle.

2. During the actuation of a switch, quick and successive fluctuations between the pressed and
non-pressed state can be observed. If not dealt with, these fluctuations can have a major impact
on the behavior of the circuit. The debouncer circuit shown in GG.32 uses an SR latch to allow
the detection of the initial contact between the switch and the latch. When moved from A to B or
vice versa, the initial contact allows a value to be stored in the latch, and this value wont be
changed until the position is reverted. The circuit only requires an initial contact, and not a
continuous contact.

Conclusion
This experiment was a fairly simple one that visually demonstrated a simple concept. Despite the
simplicity, many struggles were encountered when using the equipment for the first time, it took
some time getting used to the switch and LED module, and wiring the ICs took some getting

used to. We also realized that the real world delay of the gate switching was minimal- we had to
add more delay by inverting the signal twice more in order to see the glitch. Overall, this
introductory lab gave a basic review of previously learned material in ECE 120, and provided an
overview and basis for the labs to come.