430 5

microcontroller basics
a description based on TIs MSP430
author and speaker
Prof. Dr. Matthias Sturm

based on TIs design seminar MSP430
Prof. Dr. Matthias Sturm HTWK Leipzig
topics
architectural overview
memory configuration
instruction set and addressing modes
software development
stack and subroutines
interrupt process
system clock generator
periphery
parallel ports
basic timer 1
LCD driver module
ADC
8-bit interval timer / counter
timer / port module
watchdog timer module
typically microcontroller applications for the MSP430 family

Handheld Measurement
Air Flow measurement
Alcohol meter
Barometer
Data loggers
Emission/Gas analyser
Temperature measurement
Weight scales
Medical Instruments
Blood pressure meter
Blood sugar meter
Breath measurement
EKG system
Utility Metering
Gas Meter
Water Meter
Heat Volume Counter
Heat Cost Allocation
Electricity Meter
Sports equipment
Bike computer
Diving watches
Home environment
Air conditioning
Control unit
Thermostat
Boiler control
Shutter control
White goods
(Washing machine,..)
Misc.
Smart card reader
Taxi meter
Smart Batteries
Security
Glass break sensors
Door control
Smoke/fire/gas detectors
architectural overview: configuration 320
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
CPU register
special register
universal register
R0 programm counter PC
R4 universal register
R1 stack pointer
SP
R2 statur register
SR
R3 const. generator CG2
16 bit
16 bit
CPU register
special register
universal register
R1 stack pointer
SP
R2 statur register
SR
R0 programm counter
16 bit
15

16 bit
CPU register
special register
universal register
R1 stack pointer
SP
R2 statur register
SR
R1 stack pointer
16 bit
15

16 bit
CPU register
special register
universal register
R1 stack pointer
SP
R2 statur register
SR
R2 status register

15
16 bit9 8
R8 universal
5
4 register
3 2
1 0
universal
register
V SCG1 SCG0 R9
OSC
off CPUoff GIE N Z C
16 bit
formats of numbers
unsigned
65535 FFFFh
0
0000h
0001h 1
C
49152 C000h
4000h 16384
8000h 7FFFh 32767

32768
formats of numbers
signed
-1 FFFFh
-16384 C000h
0
0000h
0001h 1
4000h 16384
V
8000h 7FFFh 32767
-32768
Flags
Flags are set or cleared in dependence of

logic or arithmetic instructions.
Flags are used to control the program flow.
Z-Flag (zero)
set, if the result of a logic or arithmetic instruction is zero,
otherwise cleared.
N-Flag (negative)
set, if the result of a logic or arithmetic instruction is negative,
otherwise cleared.
The N-Flag is a copy of the most significant bit (MSB)
Flags
C-Flag (carry)
set, if the result of a logic or arithmetic instruction
produced a carry, otherwise cleared.
V-Flag (overflow)
set, if the result of an arithmetic instruction overflows
the signed variable range, otherwise cleared.
positiv + positive
negativ + negative
positive - negative
negative - positive
= negative
= positive
= negative
= positive
memory configuration MSP430P325
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
memory model MSP430P325
Word access
FFFFh
FFE0h
FFDFh
Byte access
interrupt vectors
OTP EPROM
16 kB OTP
C000h
unused
03FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
512 Byte RAM

16 bit periphery
8 bit periphery
RAM
special function register
MSP430P325 starter kit
The board
pre-programmed in starter kit

FFFFh
FFE0h
FFDFh
EA00h
interrupt vectors
C000h
16 kB OTP
monitor
OTP EPROM
unused
03FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
512 Byte RAM

16 bit periphery
8 bit periphery
RAM
RAM-area in starter kit

3FEh
3E0h
3DFh
3DCh
interrupt vectors
identification bit pattern
stack used by
application
stack needed from
monitor, 50 Bytes
RAM
user address range

3DCh - 214h
214h
212h
200h
(do not set the stack pointer)
RAM-area for monitor

instruction set and addressing modes
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
instruction set
fifty-one instructions
twenty-seven basic instructions
twenty-four emulated instructions
RISC
CISC
byte and word processing

seven address modes for source
four address modes for destination
all instructions appropriate for all modules
instruction set - basic instructions
Format I
Format II
Format III
source,destination
source or destination
+/- 9bit offset ( Word )
ADD(.B)
ADDC(.B)
AND(.B)
BIC(.B)
BIS(.B)
BIT(.B)
CMP(.B)
DADD(.B)
MOV(.B)
SUB(.B)
SUBC(.B)
XOR(.B)
CALL
PUSH(.B)
RETI
RRA(.B)
RRC(.B)
SWPB
SXT
JMP
JC
JNC
JEQ
JNE
JGE
JL
JN
12 instructions
1 .. 6 cycles
1 .. 3 word
7 instructions
1 .. 5 cycles
1 .. 2 word
8 instructions
2 cycles
2 word
instruction set - emulated instructions
emulated instructions are:
basic instruction to the user

replaced with a basic instruction by the assembler
emulated instructions benefits:
increased processing speed

increased ROM code efficiency
supply users with familiar instructions
no additional effort in CPU:
RISC with CISC-like instruction set
Arithmetic
ADC(.B)
DADC(.B)
DEC(.B)
DECD(.B)
INC(.B)
INCD(.B)
SBC(.B)
7 instructions
Logical
INV(.B)
RLA(.B)
RLC(.B)
3 instructions
Data
CLR(.B)
CLRC
CLRN
CLRZ
POP(.B)
SETC
SETN
SETZ
TST(.B)
9 instructions
Program Flow
BR
DINT
EINT
NOP
RET
5 instructions
How to emulate instructions?

emulated instruction
basic instruction
INC.B dst
INCD.B dst
CLRN
EINT
INV
dst
ADD.B #1,dst
ADD.B #2,dst
BIC
#4,SR
BIS
#8,SR
XOR #0FFFFh,dst
increment destination
double-incr. destination
clear negative bit
enable interrupt
invert destination
The trick is to take constant numbers in basic instructions

by using special registers, the constant generators.
CPU register
special register
universal register
R1 stack pointer
SP
R2 statur register
SR
R3 constant register
16 bit
Under different addressing modes:
15
0
R11 universal
register

R14 universal
register
0
0
1
2
F
F 16 bit
F
CPU register
special register
universal register
R1 stack pointer
SP
R2 statur register
SR
R2 status register

15
9 8
R8 universal
5
4 register
3 2
1 0
universal
register
V SCG1 SCG0 R9
OSC
off CPUoff GIE N Z C
Under different addressing modes:


R14 universal
register
0
0
4
0
16 bit
8
instruction set
instruction table (example)
source form
ADD
:
:
MOV
operand
operation
status bits
src, dst
src+dst->dst
V N Z C
* * * *
:
:
src, dst
:
:
src -> dst
:
:
-
orthogonal instruction set

Address
Modes
Source
Orthogonality is, when

all instructions
with
all address modes
are valid for
all operands
Address
Modes
Destination
Instructions
Example: Non-Orthogonality for two operand instructions
Orthogonality in MSP430
Address
Modes
Source
all single operand instructions use

all seven address modes.
and
all double operand instructions use
all seven source address modes and
all four destination address modes
Address
Modes
Destination
Instructions
Example: Orthogonality for two operand instructions
address modes
seven address modes for source
four address modes for destination
mode
source
destination
register mode
indexed mode
symbolic mode
absolute mode
indirect mode
indirect autoincrement mode
immediate mode
address modes
register addressing mode

ADD
R7,R8
; ( R7 ) + ( R8 ) ( R8 )
MOV
R5,R6
; ( R5 ) ( R6 )
CLR
R5
XOR
#1,R9
; Toggle Bit 0 in R9
#0 ( R5 )
The operand is contained in one of the registers R0 to R15.

This is the fastest addressing mode and needs the least memory .
address modes
indexed addressing mode

MOV
2(SP),R7
; Move 2nd item of Stack to R7
MOV.B
R5,9(R10)
; LSByte (R5) ((R10)+9)
ADDC
-2(R5),4(R7)
; ((R5)-2)+((R7)+4)+C ((R7)+4)
The address of the operand is the sum of the index and the contents
of the register.
The indexed mode with index zero may used for indirect register
addressing of the destination operand.
BIS
#8,0(R4)
; Set Bit 3 at address (R4)
address modes
symbolic addressing mode (PC relative addressing)

ADD
EDE,TONI
; (EDE) + (TONI) (TONI)
MOV
TONI,EDE
; Move (TONI) to (EDE)
MOV
R5,TONI
; (R5) (TONI)
MOV
EDE,R8
; (EDE) (R8)
The content of the words EDE / TONI is used for the operation.
Any address in the 64k memory space is addressable both as a
source and as a destination.
address modes
absolute addressing mode

ADD
&CCR1,&CCR2
; (CCR1) + (CCR2) (CCR2)
MOV
&P1IN,&P2OUT
; Move (P1IN) to (P2OUT)
MOV
R5,&ACTL
; (R5) (ADC Control Register)
MOV
&TACTL,R8
; (TACTL) (R8)
The contents of the fixed addresses are used for the operation.
Used for hardware peripheral modules that are located at an
absolute address; used for Position Independent Code.
address modes
indirect register addressing mode

ADD
@R8,R9
; ((R8)) + (R9) (R9)
MOV
@R10,0(R12)
; ((R10)) ((R12)+0)
MOV
@R5,&ACTL
; ((R5)) (ADC Control Register)
MOV.B
@R4,R8
; Byte addressed by R4 (R8)
The registers are used as a pointer to the operand.

The registers are not modified.
Only for the source operand addressing.
address modes
indirect register addressing with autoincrement

ADD
@R8+,R9
; ((R8)) + (R9) (R9), (R8)+2 (R8)
MOV
@R10+,0(R12)
; ((R10)) ((R12)+0)
MOV
@R5+,&ACTL
; ((R5)) (ADC Register), (R5)+2 (R5)
MOV.B
@R4+,R8
; Byte ((R4)) (R8)
, (R10)+2 (R10)
, (R4)+1 (R4)
The registers are used as a pointer to the operand.

The registers are incremented accordingly afterwards.
Only for the source operand addressing.
address modes
immediate register addressing mode

BIT
#0100h,4(R9)
; Test Bit 8=1 ? in the 3rd word of a table

; starting at (R9)
MOV.B
#01Fh,0(R12)
; 01Fh ((R12)+0)
MOV
#0010,&ACTL
; 0Ah
ADD
#0A00h,R8
; 0A00h + (R8) (R8)
(ADC Control Register)
Any immediate 8 or 16 bit constant can be used with the instruction.
Only for the source operand.
steps of
start
editor
tools
for software development
editor
assembler
success?
no
assembler
yes
simulator
simulator
success?
debugger
no
yes
hardware
debugger
(monitor)
success?
no
yes
end
source code line
Label
instruction
operand(s)
; comment
start
mov
#0FC17h, R15
; load the
; value #0FC17h
; in register R15
assembler directives
.sect
.sect defines initialized named sction and associates subsequent
code or data with this section
example: .sect INIT,0214h
.set and .equ
.set and .equ directives set a constant value to symbol
example: LCDCTL .equ 030h
.byte and .word
.byte places one or more 8-bit values into consecutive bytes
of current section
.word places one or more 8-bit values into consecutive bytes
of current section
.end
.end teminates assembly, should be the last source statement
programming techniques - stack and subroutines
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
stack and subroutine
mainprogram
mainprogram
instruction A
instruction A
instruction B
CALL subroutine
instruction C
instruction D
instruction D
CALL subroutine
instruction B
instruction E
instruction C
CALL subroutine
instruction E
instruction F
instruction B
CALL subroutine
instruction C
instruction G
instruction F
subroutine
instruction B
instruction B
instruction C
instruction C
instruction G
RETURN
main process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
stack area
instruction A
instruction B
instruction C
instruction D
instruction B
instruction C
instruction E
instruction B
instruction C
instruction F
instruction B
instruction C
instruction G
mainprogram
No subroutine
JMP MP
high address
main process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
stack area
instruction A
instruction B
instruction C
instruction D
instruction B
instruction C
instruction E
instruction B
instruction C
instruction F
instruction B
instruction C
instruction G
mainprogram
No subroutine
JMP MP
high address
main process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
stack area
instruction A
instruction B
instruction C
instruction D
instruction B
instruction C
instruction E
instruction B
instruction C
instruction F
instruction B
instruction C
instruction G
mainprogram
No subroutine
JMP MP
high address
main process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
stack area
instruction A
instruction B
instruction C
instruction D
instruction B
instruction C
instruction E
instruction B
instruction C
instruction F
instruction B
instruction C
instruction G
mainprogram
No subroutine
JMP MP
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
address of instruction D
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
Address of instruction D
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
MP
SR
stack
stack
stack
stack
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
JMP MP
instruction B
instruction C
RET
low address
stack area
mainprogram
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
MP
SR
stack
stack
stack
stack
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
JMP MP
instruction B
instruction C
RET
low address
stack area
mainprogram
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
address of instruction E
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
subroutine process
register area
R2 flag register
R1 stack pointer
R0 program counter
memory
low address
stack
stack
stack
MP
SR
instruction A
CALL SR
instruction D
CALL SR
instruction E
CALL SR
instruction F
CALL SR
instruction G
instruction B
instruction C
RET
stack area
mainprogram
JMP MP
subroutine
high address
stack and data
Save data on the stack

before you save data on the stack you need to initiate the stack
by writing the stack address to the stack pointer (R1)
to push data on the stack use the PUSH instruction
to pop data from the stack use the POP instruction
function: last-in first-out
the stackpointer uses always two Bytes of stack space
remember:
be careful not to demage addresses on the stack
avoid underflow and overflow of the stack
Conclusion
before you call a subroutine you need to initiate the stack
by writing the stack address to the stack pointer (R1)
to call a subroutine use the CALL instruction
to return from subroutine use the RET instruction
before a subroutine call the microcontroller saves
the following instruction address on the stack
remember:
the stack location have to be RAM
the stack is growing to lower addresses
the stack pointer points to the latest used stack address
programming techniques - interrupts
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
interrupt
generally
An interrupt request (usually called an interrupt)
is generated by an interrupt source.
An interrupt need to be served by a special program,
the interrupt service routine (ISR).
An interrupt can take place every time
independent of program flow (in difference to subroutine calls).
Interrupts can be maskable or non-maskable.
Different interrupt sources have different priority.
To react on an interrupt the most microcontroller
containing a vector interrupt system.
interrupt
interrupt process
register area
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
int. source 1 / local enable
interrupt logic
global interrupt enableGIE
priority check
memory
stack
stack
stack
low address
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
interrupt vector ISR1
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
memory
stack
stack
stack
low address
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
memory
stack
stack
stack
low address
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
memory
stack
stack
stack
low address
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
memory
stack
stack
stack
low address
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
memory
low address
stack
stack
instruction D address
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
memory
low address
stack
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
flag register
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
memory
low address
stack
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
flag register
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
memory
low address
stack
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
flag register
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
memory
low address
stack
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
flag register
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
memory
low address
stack
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
flag register
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
memory
low address
stack
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
flag register
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
memory
low address
stack
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
flag register
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
memory
low address
stack
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
flag register
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
memory
low address
stack
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
flag register
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt process
register area
memory
low address
stack
R2 flag register
R1 stack pointer
R0 program counter
interrupt sources
interrupt logic
priority check
flag register
stack area
MP
instruction A
instruction B
instruction C
instruction D
instruction E
JMP MP
ISR1 instruction X
instruction Y
RETI
instruction Z
ISR2 instruction U
instruction V
RETI
instruction W
hard wired
mainprogram
interrupt
service routine 1
interrupt
service routine 2
interrupt
vector table
high address
interrupt
interrupt vector table

Int. Source
Int. Flag
system Int.
Word address
mirror address
RSTI
reset
0FFFEh
03FEh
nonmaskable
0FFFCh
03FCh
14
maskable
maskable
0FFFAh
0FFF8h
03FAh
03F8h
13
12
maskable
0FFF4h
03F4h
10
maskable
maskable
0FFEAh
0FFE8h
03EAh
03E8h
5
4
maskable
maskable
0FFE2h
0FFE0h
03E2h
03E0h
power-up
external reset
watchdog
NMI
Oscillator fault
dedicated I/O
dedicated I/O
WDI
NMIIFG
OFIFG
P0.0IFG
P0.1IFG
watchdog timer
WDTIFG
ADC
timer port
basic timer
I/O port 0
ADCIFG
flags located in
module register
BTIFG
P0.2..7IFG
priority
15, highest
1
0, lowest
interrupt
programming interrupts
program structure
initiate
main program
Interrupt service
routine 1
Interrupt service
routine 2
Interrupt service
routine 3
Priority falling
interrupt
program steps
Dont forget to
initiate the
interrupt
vector table !
initiate
stack and stack pointer
resources of the main program
resources of interrupt subroutines
local interrupt enable
global interrupt enable
main program
instructions of main program
loop inside the main program
interrupt subroutine 1
instructions of the interrupt subroutine
end ISR with RETI instruction
interrupt subroutine 2
instructions of the interrupt subroutine
end ISR with RETI instruction
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
features
One crystal - no external components
stable processor frequency - no accumulating error
fast start up
XIN
Low power Oscillator

for 32.768 kHz crystal
ACLK
Auxiliary Clock
XOUT
FLL
PUC
fMCLK = ( N + 1 ) * fACLK
MCLK
Main System Clock
(fSystem)
frequency locked loop

+
ACLK
:(N+1)
synchronizer
Reset
U/D
frequency integrator
10 bit
CLK
M 26 25 24 23 22 21 20
SCFQCTL
Enable
SCFI0
SCFI1
9
PUC
2 2 2 2 2 2 2 2
... 21 20
modulator
5
digitally controlled oscillator

(DCO)
DC Gen
MCLK
fSystem
OscOff,
SCG0, SCG1
Control of
operation mode
set interrupt flag

in SFRs
FN_4 FN_3 FN_2 ...

SCFI0
system clock frequency

MCLK = f(System) = ( N + 1 ) f(crystal)
N in the range of 3 .. 127

MCLKmax = f(System)max = 3.3 MHz
three register used for control

system clock frequency control register SCFQCTL
system clock frequency integrator 0 register SCFI0
system clock frequency integrator 1 register SCFI1
osc. fault interrupt flag OFIFG
IFG 1.1
osc. Fault interrupt enable OFIE
IE 1.1
0052h
0050h
0051h
0002h
0000h
use byte instructions

system clock operation modes

mode
crystal
osc.
DC
DCO
loop
generator
control
comments
typ. current
at Vcc=3V
fsys.=1MHz
active
on
on
on
on
conditions after PUC
LPM1
on
on
on
off
loop control off CPU off
LPM2
on
on
off
off
DCO and loop control off
6A
LPM3
on
off
off
off
only crystal osc. On
1.3A
LPM4
off
off
off
off
all functions disabled

fsystem=0Hz
0.1A
3000A
(400A/C325)
70A
R2 status register
15
9 8
1 0
V SCG1 SCG0 OSCoff CPUoff GIE N Z C

crystal buffer output

POR
CL
Q0
CBSEL1
CBSEL0
Q1
ACLK
XBUF
2
3
MCLK
CBE
CBCTL crystal buffer control register

7
CBSEL1 CBSEL0 CBE
program example
configures the system clock to 1.05MHz by crystal frequency of 32768Hz
START mov.b #1Fh,&SCFQCTL
; set multiplication
; factor of PLL to 32
periphery
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
periphery
periphery register
FFFFh
FFE0h
FFDFh
EA00h
interrupt vectors
C000h
16 kB OTP
monitor
OTP EPROM
unused
03FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
512 Byte RAM

16 bit periphery
8 bit periphery
RAM
periphery register / special function register

:
0007h
0006h
0005h
0004h
0003h
0002h
0001h
0000h
03FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
:
reserved
reserved
module enable 2
module enable 1
interrupt flag register 2
interrupt flag register 1
interrupt enable 2
interrupt enable 1
ME2.2
ME1.1
IFG2.x
IFG1.x
IE2.x
IE1.x
512 Byte RAM

16 bit periphery
8 bit periphery
RAM
periphery register / Byte modules

:
:
0080h - 008Fh
0070h - 007Fh
0060h - 006Fh
0050h - 005Fh
0040h - 004Fh
0030h - 003Fh
0020h - 002Fh
0010h - 001Fh
03FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
:
reserved
USART register
reserved
system clock generator register
basic timer, 8-Bit timer/counter, timer/port register
LCD register
digital I/O port P3 and P4 control register
digital I/O port P0, P1 and P2 control register
512 Byte RAM
16 bit periphery
8 bit periphery
RAM
periphery register / Word modules

:
:
0180h - 018Fh
0170h - 017Fh
0160h - 016Fh
0150h - 015Fh
0140h - 014Fh
0130h - 013Fh
0120h - 012Fh
0110h - 011Fh
0100h - 010Fh
03FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
:
reserverd
timer_A
timer_A
reserved
reserved
multiplier
watchdog timer
analog-to-digital converter
reserved
512 Byte RAM
16 bit periphery
8 bit periphery
RAM
general port P0 / parallel ports
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
general port P0
P0.0
P0BIT.0
P0DIR.0
features
P0.1
P0BIT.1
P0DIR.1
P0.2
P0DIR.2
8 Bit parallel port
P0.3
bit programmable
individual function select
interrupt source selection
(three interrupt vectors)
P0BIT.2
P0BIT.3
P0DIR.3
P0.4
P0BIT.4
P0DIR.4
P0.5
P0BIT.5
P0DIR.5
P0.6
P0BIT.6
P0DIR.6
P0.7
P0BIT.7
P0DIR.7
general port P0
six register used for control

input register
output register
direction register
interrupt flags
interrupt edge select
interrupt enable
P0IN
P0OUT
P0DIR
P0IFG
P0IES
P0IE
0010h
0011h
0012h
0013h
0014h
0015h
general port P0
P0DIR.x
P0.x
P0BIT.x
output buffer
input
Pad logic
interrupt
edge select
P0IES.x
P0OUT.x
P0IN.x
interrupt flag
P0IFG.x
P0IE.x
P0IRQ.x
schematic of bits P0.7 to P0.3

general port P0
program example
configures P0.3 and P0.4 as input and checks the pins
main
P04
next
bic.b
clr
bit.b
jnc
mov.b
bit.b
jnc
mov.b
nop
#018h,&P0DIR
R15
#008h,&P0IN
P04
#015h,R15
#010h,&P0IN
next
#016h,R15
;
;
;
;
;
;
;
;
set P0.3 and P0.4 to inputs

clear R15
check pin P0.3
if not pressed -> check pin P0.4
if pressed -> load pattern R15
check pin P0.4
if not pressed -> goto next
if pressed -> load pattern R15
timer / port module
parallel port feature
TPD.0
TP.0
TPE.0
TPD.1
TP.1
TPE.1
TPD.2
five outputs
one bidirectional channel
TP.2
TPE.2
TPD.3
TP.3
TPE.3
TPD.4
TP.4
TPE.4
TPD.5
TP.5
TPE.5
two register used for control

TP O/P data register
TP data enable register
TPD
TPE
004Eh
004Fh

timer / port module
program example
configures TP0 .. TP5 as output and writes a pattern
OUT
mov.b
mov.b
mov.b
#0FFh,&TPE
#015h,R15
R15,&TPD
; enable outputs of Timer/Port

; load pattern R15
; output pattern
ADC
parallel port feature

AIN.0
A.0
AEN.0
AIN.1
A.1
AEN.1
six inputs
AIN.2
A.2
AEN.2
A.3
AIN.3
AEN.3
A.4
AIN.4
AEN.4
AIN.5
A.5
AEN.5
two register used for control

input data register
input enable register
AIN
AEN
0110h
0112h
use word instructions

ADC
program example
configures all AD-pins as inputs and checks two pins
MAIN
A1
next
mov
bit
jnc
mov.b
bit
jnc
bis.b
nop
#0FFh,&AEN
#01h,&AIN
A1
#015h,R15
#02h,&AIN
next
#02Ah,R15
;
;
;
;
;
;
;
all AD-pins dig.inputs

check pin AIN.0
if LO -> check pin AIN.1
if HI -> load pattern R15
check pin AIN.1
if LO -> goto next
if HI -> add pattern to R15
basic timer 1
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
basic timer 1
Three functions of the Basic Timer 1

LCD driver frequency
basic timings
real-time clock
DIV
Hold
Hold
EN1
ACLK
CLK1
EN2
BTCNT1
CLK2
Q4 Q5 Q6 Q7
FRFQ1
FRFQ0
BTCNT2
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
SSEL DIV
IP2
IP1
IP0
Set_Int._Flag
0
ACLK / 256
1
2
MCLK
fLCD
basic timer 1

basic timer1control register BTCTL
basic timer1 counter 1 register BTCNT1
basic timer1 counter 2 register BTCNT2
basic timer interrupt flag BTIFG IFG2.7
basic timer interrupt enable BTIE IE2.7
0040h
0046h
0047h
0003h
0001h
BTCTL basic timer1 control register

7
SSEL Hold
DIV FRFQ1 FRFQ0 IP2
IP1
IP0

basic timer 1 - examples
simple generation of timings
LCD timing
example MUX4
Hold
EN2
CLK2
LCD data sheet

fframing=100Hz..30Hz
BTCNT2
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
ACLK=32768Hz
IP2
IP1
IP0
Set_Int._Flag
64
32
16
16384 8192 4096 2048 1024 512
0.5
ACLK / 256
256
128
ACLK
depends on MCLK
Interrupt frequency [Hz]
MCLK
CLK2
FRFQ:
fLCD=8x100Hz..8x30Hz
fLCD=800Hz..240Hz
select fLCD
1024Hz/512Hz/256Hz/128Hz
fLCD=256Hz
FRFQ1=1 / FRFQ2=0
basic timer 1
program example
configures basic timer1 as clock source for LCD module
mov.b #050h,&BTCTL
bis.b #BTME,&ME2
LOOP
mov.b
mov
clr.b
dec
jnz
#0FFh,&LCDCTL
#0008h,R7
LCDM-1(R7)
R7
LOOP
; set up Basic Timer

; for LCD operation
; enable Basic Timer
; set up LCD driver
; clear display
LCD driver module
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
LCD driver module
features
different driving methods
static
2MUX
3MUX
4MUX
memory structure for the segment bits

up to 30 segment lines per module
up to 15 digits in 4MUX mode
On/ Off of analog generator capability
select groups of segment/ digital outputs
LCD driver module
LCD Module
MSP430
Mux
Mux
Memory
15 i 8 bit
S29 / O29 / CMPI
Segment
Display
Mux
Output
Control
Mux
Basic Timer 1
Module
fLCD
LCD Control & Mode

Register
Timing Generator
Common
Output
Control
Analog
Voltage
Multiplexer
S2 / O2
S1
S0
COM3
COM2
COM1
COM0
R33
R23
R13
R03
LCD driver module
7 segment display
a
f
segment n
b
a
e
d
f
e
4MUX mode
A digit consists of seven
segments driven from
two segment and four
common lines.
segment n+1
d
z COM0
z COM1
z COM2
z COM3
LCD driver module
Display memory, 4MUX drive
MDB
MAB
segment n
segment n+1
a
f
e
d
z COM0
z COM1
z COM2
z COM3
BIT
COM
003Fh
003Eh
003Dh
003Ch
003Bh
003Ah
0039h
0038h
0037h
0036h
0035h
0034h
0033h
0032h
0031h
7
3
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
6
2
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
5
1
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
4
0
h
h
h
h
h
h
h
h
h
h
h
h
h
h
h
3
3
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
2
2
g
g
g
g
g
g
g
g
g
g
g
g
g
g
g
1
1
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
0
0
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
digit 15
digit 14
digit 13
digit 12
digit 11
digit 10
digit 9
digit 8
digit 7
digit 6
digit 5
digit 4
digit 3
digit 2
digit 1
segm. n+1 segm. n

segment n
segment n+1
LCD_TYPE
;STK/EVK LCD
a .equ
b .equ
c .equ
d .equ
e .equ
f .equ
g .equ
h .equ
a
f
MAB
z COM0
z COM1
z COM2
z COM3
MDB
BIT
COM
0037h
0036h
0035h
0034h
0033h
0032h
0031h
h
7
3
e
e
e
e
e
e
e
6
2
h
h
h
h
h
h
h
5 4
1 0
f c
f c
f c
f c
f c
f c
f c
3
3
g
g
g
g
g
g
g
2
2
d
d
d
d
d
d
d
1
1
b
b
b
b
b
b
b
01h
02h
10h
04h
80h
20h
08h
40h
LCD of the starter kit

MSP430
;--- character definitions

LCD_Tab
0
0
a
a
a
a
a
a
a
digit
digit
digit
digit
digit
digit
digit
segm. n segm. n+1
7
6
5
4
3
2
1
.byte
.byte
.byte
.byte
.byte
.byte
.byte
.byte
.byte
.byte
.byte
.byte
.byte
.byte
.byte
.byte
a+b+c+d+e+f
b+c
a+b+d+e+g
a+b+c+d+g
b+c+f+g
a+c+d+f+g
a+c+d+e+f+g
a+b+c
a+b+c+d+e+f+g
a+b+c+d+f+g
a+b+c+e+f+g
c+d+e+f+g
a+d+e+f
b+c+d+e+g
a+d+e+f+g
a+e+f+g
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
displays
displays
displays
displays
displays
displays
displays
displays
displays
displays
displays
displays
displays
displays
displays
displays
"0"
"1"
"2"
"3"
"4"
"5"
"6"
"7"
"8"
"9"
"A"
"B" b
"C"
"D" d
"E"
"F"
LCD driver module
one register used for control

LCD control and mode register
LCDCTL
0030h
Use word instructions and absolute address mode.
LCDCTL LCD control and mode register

7
LCDM7 LCDM6 LCDM5 LCDM4 LCDM3 LCDM2 LCDM1 LCDM0
segment selection
mode selection
LCD driver module
program example
mov.b
mov
LOOP
clr.b
dec
jnz
MAIN
mov
clr
PRINT mov
and
mov.b
rra
rra
rra
rra
inc
cmp
jne
nop
#0FFh,&LCDCTL
; set up LCD driver
#0008h,R7
; clear display
LCDM-1(R7)
R7
LOOP
&NUMBER,R6
; load value of NUMBER in R6
R7
; register R7 := 00h
R6,R8
; move R6 to R8
#000Fh,R8
; keep lower 4 bits
LCD_Tab(R8),LCDM(R7)
; display digit on LCD
R6
; rotate right four times
R6
R6
R6
R7
#04h,R7
; all 4 digits one
PRINT
; no -> go to next digit
ADC
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
ADC
features
Programmable 12bit or 14 bit resolution
Four programmable ranges
Conversion time <100sec,
96(12 bit) / 132(14 bit) ADCLK cycles
Sample&Hold
Eight Analog/Digital inputs
Programmable current source
Ratiometric or Absolute measurement
Low current consumption, typ. 200A
Power-Down feature
to stop current consumption
Large supply voltage range, 2.5V ..... 5.5V
external or internal reference supply
Range
SVCC
D
0.75*SVCC
C
0.50*SVCC
B
0.25*SVCC
A
AVSS
0
1000h 2000h 3000h 4000h
A/D-C
Value
ADC
AVCC
ACTL1
ACTL12
SVCC
Current MUX
128
A
AVSS
delay
SVCC
2
5
ACTL0
ACTL11
ACTL10
ACTL9
Input Buffer
AIN
Successive Approximation
Register
:1
:2
:3
:4
MCLK
Int. flag
ACTL14
ACTL13
ACTL12
ACTL11
ACTL10
ACTL9
ACTL8
ACTL7
ACTL6
ACTL5
ACTL4
ACTL3
ACTL2
ACTL1
ACTL0
Input MUX
ACTL2
ACTL3
ACTL4
ACTL5
: 12
ADCLK
analog
digital
MSP430
x32x
A0
A1
A2
A3
A4
A5
A6
A7
ADCLK/12
ACTL 13
ACTL 14
ACTL6
ACTL7
128
B
Capacitor ARRAY
C
ACTL8
Range MUX
Rext
128
ACTL10
ACTL9
0.75 * SVCC
Resistor Decode
128
D
Input Buffer Enable

AEN
Control Register
ACTL
16
Conversion Result
ADAT
16
MDB, 16 bit
ADC
radiometric measurement
SVCC
R1
Ri
MSP430x325
A1
R2
AVSS
N = 214 / [R2/(R2+R1)]
DVSS
0V
DVCC AVCC
+5.5V ... +2.5V
SVCC
R1
Ri
A1
MSP430x325
R2
N = 214 * 0.25 * R1 / R2
AVSS
DVSS
0V
DVCC AVCC
+5.5V ... +2.5V
ADC
absolute measurement
voltage
regulator
SVCC
supply
input
Ri
A1
MSP430x325
Analog
input
AVSS
SVCC ~ AVCC
SVCC switch closed
DVSS
supply
input
DVCC AVCC
voltage
regulator
SVCC
Ri
A1
MSP430x325
Analog
input
0 < SVCC < AVCC

SVCC switch open
AVSS
DVSS
0V
DVCC AVCC
+5.5V ... +2.5V
ADC
four register used for control
input register
input enable register
ADC control register
ADC data register

end-of-conversion flag ADIFG
clear by software
AIN
AEN
ACTL
ADAT
IFG2.2
0110h
0112h
0114h
0118h
0004h
ACTL ADC control register

15 14 13 12
11 10
0 ADCLK Pd range select c. source AD input sel. Vref CS

ADC
program example
configures the ADC and works as converter
mov
#0900h,&ACTL
bis.b #020h,&P0DIR
bis.b #020h,&P0OUT
MAIN
EOC
bis
#CS,&ACTL
bit.b #ADCIFG,&IFG2
jnc
EOC
bic.b #ADCIFG,&IFG2
mov
&ADAT,R6
; set up ADC :
; - external reference
; - ADC input A0
; - no current source
; - automatic range select
; - power on, ADCLK = MCLK
; switch on external
; on-board reference
; start conversion
; wait for end of
; conversion
; clear flag
; load conv. result in R6
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
features
three major functions
serial communication or data exchange
pulse counting or pulse accumulation
timer

T/C control register
TCCTL
pre-load register
TCPLD
counter register
TCDAT
P0.1 or counter interrupt flag P0IFG IFG1.3
P0.1 or counter interrupt enable P0IE.1 IE1.3
P0.1 interrupt edge select P0IES.1 P0IES
0042h
0043h
0044h
0002h
0000h
0014h


P0IES.1
P0.1
ISCTL
P0IE.1
Interrupt
request
IRQP0.1
Set
1
T/C Control Reg.

TCCTL
0
1
2
3
ACLK
Clear
Pre-load Register
TCPLD
SSEL
0 1
MCLK
IRQA
SSEL0
SSEL1
ISCTL
ENCNT
RXACT
RXD
TXD
TXE
interrupt logic
P0.1 and 8bit T/C
Q0 ...Q7
CLK2
EN
counter, preload
and control register
Counter
TCDAT
Load
RC
ENCNT
Clear
RXACT
Q
serial communication
support
Set
RXD
Set
TXD_FF
TXE
TXD
Q
P0DIR.2
P0OUT.2
'Write' to TCDAT
PUC
Output
control
P0.2
RXD_FF
PUC
serial asynchronous data format
LSB
MSB
high
D0
D1
D2
D3 D4 D5
D6 D7
low
eight data bits

start bit
stop bit
serial asynchronous data format (reading)

begin of frame
is the falling
edge of start bit
high
LSB
MSB
D0 D1 D2 D3 D4 D5 D6 D7
low
level detection
in the middle
of the bit
eight data bit

start bit
stop bit
timer / port module
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
timer / port module
features
six tri-state output ports (one bidirectional)
precision comparator CMPI for slope A/D conversion
or standard digital input CIN
two 8-bit counters, cascadable for 16-bit counter
three clock sources for counting up the counter
three interrupt sources
timer / port module
CIN
TPD.0
TPD.3
TPE.3
TP.4
TPIN.5
ACLK
MCLK
TPD.4
Data Register
TPD
RC1
TPSSEL2
0
1
2
3
EN2
Data Enable Register

TPE
CLK2
RC2
TPE.4
TP.5
CLK1
Set_RC1FG
TPSSEL3
TPD.5
Control Register
TPCTL
EN1
B16
TPIN.5
TPD.2
TPE.2
TP.3
0
1
2
3
TPD.1
TPE.1
TP.2
TPSSEL0
CMP
ACLK
MCLK
TPE.0
TP.1
Set_EN1FG
ENB ENA
CPON
TPSSEL1
TP.0
TPSSEL0
TPSEL1
TPSEL0
ENB
ENA
EN1
RC2FG
RC1FG
EN1FG
VCC/4
Enable
Control
B16
CPON
TPD.5
TPD.4
TPD.3
TPD.2
TPD.1
TPD.0
CMPI
CMP
TPIN.5
Set_RC2FG
TPSEL3
TPSEL2
TPE.5
TPE.4
TPE.3
TPE.2
TPE.1
TPE.0
0
1
TPE.5
Timer/Port
timer / port module
five register used for control

TP control register
TP counter 1 register
TP counter 2 register
TP O/P data register
TP data enable register
timer/port interrupt enable TPIE
TPCTL
TPCNT1
TPCNT2
TPD
TPE
IE2.3
004Bh
004Ch
004Dh
004Eh
004Fh
0001h
timer / port module
program example
pulse with measurement with timer / port
MAIN
mov.b
mov.b
mov.b
clr.b
clr.b
bis.b
eint
jmp
#060h,&TPCTL
#00h,&TPE
#080h,&TPD
&TPCNT2
&TPCNT1
#TPIE,&IE2
MAIN
;
;
;
;
set clock for TPCNT1 enable TPCNT1 with TP.5-IN

disable outputs
select 16-bit mode
set timer start values
; enable Timer/Port interrupt

; global interrupt enable
; infinite loop
; Timer/Port Interrupt Service Routine

TPISR bit.b
jnc
clr
mov.b
swpb
clr
mov.b
bis
OUT
...
#EN1FG,&TPCTL
TPI_EX
R5
&TPCNT2,R5
R5
R6
&TPCNT1,R6
R6,R5
;
;
;
;
;
;
;
;
detect interrupt source

jump if source = overflow
prepare counter result
read high part of counter result
swap low- and high part
prepare counter result
read low part of counter
build the counter result by logic OR
; print counter result to LCD
clr.b &TPCNT2
; set timer start values
clr.b &TPCNT1
TPI_EX bic.b #(RC2FG+EN1FG),&TPCTL
; clear interrupt flags
reti
; return from interrupt
CPU
Power
FLL
ROM
RAM
JTAG
ADC
12+2 bit
MAB
MDB
Bus conv.
8 bit Timer Basic

Timer Port Timer
Watch
LCD
I/O
Port
features
eight software selectable time intervals
two operation modes
watchdog
expiration of time interval generates a system reset
interval timer
expiration of time interval generates a interrupt request
write the watchdog control register is only possible

using a password
MDB, HighByte
MDB, LowByte
R/W
Password Compare
WDT Control Register
EQU
Read: HighByte is 069h

HOLD
Write: HighByte is 05Ah, otherwise

security key is violated
NMI
CNTCL
IS1
NMIES TMSEL SSEL
IS0
CNTCL
WDT control register

with protection
VCC
PUC
HOLD
Power-up
Circuitry
SSEL
EN
MCLK 0
CLK
ACLK
Clear
____
RST/NMI
16-bit Counter
Q6
Q9
Q13 Q15
NMI
IS1
IS0
1
POR
TMSEL
WDTQn
PUC
Resetwd1
IFG1.0
WDTIFG
EQU
Clear
Resetwd2
POR
IRQA
TMSEL
IRQ
IRQ: Interrupt Request

IRQA: Interrupt Request Accepted
timer/counter and
interrupt logic
IE1.0
WDTIE
Clear
PUC
power-on reset POR and

power-up clear PUC
logic
one register used for control

watchdog timer control register WDTCTL
0120h
WDTCTL watchdog control register (write)

15 14 13 12 11 10 9 8
0 1 0 1 1 0 1 0 HOLD NMIES NMI TMSEL CNTCL SSEL IS1 IS0
Password (5Ah)
WDTCTL watchdog control register (read)

15 14 13 12 11 10 9 8
0 1 1 0 1 0 0 1 HOLD NMIES NMI TMSEL CNTCL SSEL IS1 IS0
Password (69h)
program example
disables the watchdog timer
WDTCTL
WDTHold
WDT_wrkey
Marke
mov
.equ
.equ
.equ
0120h
80h
05A00h
#(WDTHold+WDT_wrkey),&WDTCTL
; stop Watchdog
MSP430 roadmap
Price
CPU,
A/D converter
Timer/Port
CPU,
H/W MPY
USART,
Timer_A
Timer/Port
with LCD
driver
x330
x320
CPU,
Timer/Port
x310
without LCD
driver
More to come
x11x
Complexity
architectural overview: configuration 330
CPU
Power
FLL
ROM
RAM
MUL
Watch
Timer
A
I/O
Port
I/O
Port
JTAG
MAB
MDB
Bus conv.
8 bit Timer Basic

USART Timer Port Timer
Univ.
LCD
I/O
Port
I/O
Port
Special thanks for listening the
a description based on TIs MSP430
author and speaker
Prof. Dr. Matthias Sturm

based on TIs design seminar MSP430

430 5

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microcontroller basics

a description based on TIs MSP430

author and speaker

Prof. Dr. Matthias Sturm

Prof. Dr. Matthias Sturm HTWK Leipzig

typically microcontroller applications for the MSP430 family

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R3 const. generator CG2

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R10 universal register

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8000h 7FFFh 32767

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special function register

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special function register

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RAM-area in starter kit

user address range

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RAM-area for monitor

instruction set and addressing modes

8 bit Timer Basic

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byte and word processing

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emulated instructions are:

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emulated instructions benefits:

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