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Analogue Electronics 1 ENEL3TA

Differential Amplifiers

Differential Amplifiers
Differential amplifiers, the concepts of differential and common-mode signals and gains, and
common-mode rejection ratio (CMRR) have been introduced previously.1 Differential amplifiers
are widely used for their ability to reject common-mode noise. The input stage of every op-amp is a
differential amplifier and we shall now consider some typical circuits used to produce differential
amplifiers and their associated biasing.

1.

The BJT Differential Pair

(Emitter-coupled Pair, Long-tailed Pair)

This (and its FET counterpart) forms the most widely used circuit building block in
analogue ICs;
This forms the basis for a very high-speed logic family (ECL: emitter-coupled logic);
It is widely used in ICs such as op-amps, voltage comparators, voltage regulators etc.

The basic BJT differential pair is shown in Fig. 1 where the BJTs are assumed identical (matched)
and the dc biasing is controlled by a constant current source which is usually a transistor current
source such as a current mirror (studied later), or in the simplest case just a resistor.
+VCC
RC

RC
vC1

iC1

vC2
Q2

Q1

vB1

iC2

iE1

VE i
E2

IT

vB2

REE
VEE

Figure 1
The dc transfer characteristic which gives the relation between the input and output voltages can be
determined from the large-signal analysis. The large-signal analysis can be simplified by making
the following assumptions:
1. The output resistances of the BJTs are infinite: ro = ,
2. The output resistance of the current source is infinite: R EE = (the current source is ideal).
Common-mode operation
Consider first the operation of the circuit with the two bases joined and a pure common-mode
voltage vCM applied to both inputs i.e. v CM = v B1 = v B2 . Following the above assumptions, the tail
current IT will remain constant and from symmetry will divide equally between the two BJTs so that
i E1 = i E 2 = I T 2 .
1

Electrical Principles 2 (ENEL2EB), Op-amp notes: p7,8 etc.

H Jay

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Analogue Electronics 1 ENEL3TA

Differential Amplifiers

Assuming the BJTs are biased into the active region, i C1 = i C 2 = i E1 = i E 2 = I T 2 thus the
I
voltage at each collector will be v C1 = v C 2 = VCC i C R C = VCC T R C .
2
If the common-mode input signal is varied, as long as the BJTs remain in the active region, the tail
current will still divide equally and the collector voltages will not change. Thus the differential pair
does not respond to (i.e. it rejects) common-mode input signals.

Large-signal operation
Recall that for a BJT in active mode: i C = IS e v BE VT

i E =

i C IS v BE
= e

VT

IS (v B1 v E ) VT
I
e
and i E2 = S e (v B 2 v E ) VT

i E1 + i E 2 = I T , and hence after some manipulation we obtain:

i E1 =

differential pair:
Also

i E1 =
i C1 =

IT

1 + e (v B 2 v B1 ) VT

and i E2 =

1 + e (v B 2 v B1 ) VT

and i C2 =

IT

, so for the
(1)

1 + e (v B1 v B 2 ) VT

IT

(2)

IT

1 + e (v B1 v B 2 ) VT

(3)

Using equation 3 and substituting v id = v B1 v B2 we may thus plot the transfer characteristics of
the BJT differential pair as shown in Fig. 2.

Normalised collector current, iC/IT

Linear region

1.0

i C2
IT

i C1
IT

0.5

0
-10 -8

-6

-4

-2

10

Normalised differential input voltage, v id / VT = (v BE1-v BE2) / VT

Figure 2
Note from Fig. 2 that a relatively small difference voltage of about 4VT (approx. 100 mV) is
sufficient to switch the current almost entirely to one side of the BJT pair and is one reason this
circuit can be used as a fast current switch.
We are here concerned specifically with the application of the BJT differential pair as a linear
small-signal amplifier and thus as seen from Fig. 2 the differential input voltage should thus be
limited to less than about VT/2 ( 12 mV) in order to operate in the linear region of the
characteristics around the midpoint x.
H Jay

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Analogue Electronics 1 ENEL3TA

Differential Amplifiers

Often to extend the linear region of operation, small equal value resistances (RE1 & RE2) are
included in series with the emitters of BJTs Q1 & Q2 as shown in Figure 3.
+VCC
RC

RC
vC1

iC1

vC2
Q2

Q1
RE1

vB1

iC2

RE2

IT

vB2

REE
VEE

Figure 3

Normalised collector current, iC/IT

This is termed emitter degeneration since the emitter resistances introduce some negative
feedback to the circuit. This has the effect of increasing the differential input voltage that may be
applied while keeping the operation in the linear region, but reducing the gm (which is the slope of
the transfer curve at vid = 0) as seen (dotted) in Fig. 4. The differential input resistance is also
increased (resistance reflection of RE into the base circuit).
1.0

IT
RE = 0
2

i C1
IT

0.5

IT
R E = 5 VT
2

0
-10 -8

-6

-4

-2

10

Normalised differential input voltage, v id / VT = (v BE1-v BE2) / VT

Figure 4
Thus the linearity is improved, (i.e. distortion reduced), the gm and hence the voltage gain is
reduced, and the input resistance is increased. (This is the same effect that the addition of an
unbypassed emitter resistance has to a single stage BJT common-emitter amplifier.)

Differential or Single-ended output

The output of the differential pair may be taken differentially between the two collectors (by
feeding this difference into another differential stage), hence the differential output is
v od = v C1 v C 2 . The output may also be taken single-ended from just one collector with respect
to ground, hence the single-ended output is v os = v C1 or v os = v C 2 .

H Jay

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Analogue Electronics 1 ENEL3TA

Differential Amplifiers

Small-signal operation
The small-signal operation is easiest analysed by considering the circuit response to the differential
and common-mode components of the signals separately and working with the relevant
half -circuit model for each case (as shown below).
In the following analysis external load resistance RL has been omitted for simplicity, hence where
necessary replace RC by R L = R C // R L etc. as appropriate.

a.
Pure differential signals:
Consider the BJT differential pair of Fig. 3 with differential signals applied as in Fig. 5. For pure
differential signals (i.e. signals with zero common-mode component), points on the line of
symmetry are virtual grounds. (The dc supply rails are signal grounds, and at points such as
x in Fig. 5, by symmetry, the increase in signal current in one BJT is exactly matched by the
decrease in signal current in the other BJT hence the signal voltage at x is zero.)
line of
symmetry
+VCC
RC

RC
vC1

vC2
Q2

Q1

Vid
2

RE

RE

Vid
2

IT

REE
VEE

Figure 5
Hence for differential signals, the circuit is effectively two identical half-circuits each comprising
a single BJT (in common-emitter) with opposite polarity differential signal components applied.
We may thus draw an equivalent half-circuit and replace the BJT by an appropriate model (e.g.
T model) as in Fig. 6:
ie

vC1
V
+ id
2

Q1

RC

Vid
2

RE

ib

vC1

ie
re

T-model

RC

RE

Figure 6
Hence the small-signal equivalent circuit has been simplified to effectively two half-circuits each
of which is a simple familiar BJT CE circuit (with or without RE) and can thus be simply analysed.
H Jay

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Analogue Electronics 1 ENEL3TA

Differential Amplifiers

From the equivalent half-circuit:

v
v v
2v
v
RC
ie R C
RC
A Vd (diff. o/p) od = C1 C2 = C1 = C1 =
=

...(4)
v
id
v id
v id
v id
i e (re + R E )
(re + R E )
(re + R E )
2

A Vds (single - ended o/p)

v os v C1
ie R C
RC
RC
=
=
=

v id v id
2 i e (re + R E )
2 (re + R E )
2 (re + R E )

v id
= i e ( re + R E )
v id = 2 i e ( re + R E ) = 2 i b ( + 1) ( re + R E )
2
v
2 i b ( + 1) ( re + R E )
Hence R id id =
= 2 ( + 1) ( re + R E )
ib
ib

...(5)

...(6)

(as expected using the familiar resistance reflection rule)

Thus, without RE: (substitute RE = 0 in (4),(5),(6))

A Vd =

RC
g R
= g m R C and A Vds = m C ;
re
2

R id = 2 ( + 1) re = 2 r

(7)

b. Pure common-mode signals:

Consider the BJT differential pair of Fig. 3 redrawn in fully-symmetric form with identical
common-mode signals applied as in Fig. 7. For pure common-mode signals (i.e. signals with
zero differential component), points on the line of symmetry are open circuits since no current
flows in these links. (By symmetry with equal common-mode signals applied, the signal voltages at
x and y will be equal.)
line of
symmetry
+VCC
RC

RC
vC1

vC2
Q2

Q1

v ic

RE

RE

x
2REE

v ic

y
IT
2

IT
2

2REE
VEE

Figure 7
Hence for common-mode signals, the circuit is effectively two identical half-circuits each
comprising a single BJT (common-emitter with RE) with equal common-mode signal components
applied. We may thus draw an equivalent half-circuit and replace the BJT by an appropriate
model (e.g. T model) as in Fig. 8:
H Jay

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Analogue Electronics 1 ENEL3TA

ie

vC1
Q1

v ic

Differential Amplifiers

ib
v ic

RC

ie
re

RE

vC1

T-model

RC

RE

2REE

2REE

Figure 8
If the output is taken single-endedly, then from the equivalent half-circuit in Fig. 8:
A Vcs (single - ended)

v C1
RC
ie R C
RC
=
=

v ic
i e (re + R E + 2R EE )
(re + R E + 2R EE )
(re + R E + 2R EE )

RC
2R EE

[ since usually 2R EE >> (re + R E ) ]

...(8)

(r + R E + 2R EE ) (re + R E + 2R EE ) R EE
A Vds
RC
...(9)

e
=

(re + R E )
A Vcs 2(re + R E )
2(re + R E )
RC
R
Also, if R E = 0, then CMRR EE g m R EE
re
and hence, CMRR

If the output is taken differentially, then assuming perfect symmetry, the output common-mode
voltage v oc = v C1 v C 2 will be zero, and hence the common-mode voltage gain will also be zero
and the CMRR will be infinite.
In practice circuits are not perfectly symmetrical hence even if the output is taken differentially, the
common-mode gain will not be zero. For example, consider the case where the circuit is symmetric
except for a mismatch RC in the collector resistances i.e. Q1 has load resistance RC but Q2 has load
resistance RC + RC. Hence, using (8):

v C1 =

RC
v ic ;
(re + R E + 2R EE )

v C2 =

the common - mode output will be :

A Vcd =

(R C + R C )
v ic
(re + R E + 2R EE )

v oc = v C1 v C 2 =

R C
v ic
(re + R E + 2R EE )

v oc
R C
R C
=

v ic (re + R E + 2R EE ) 2R EE

This can be rewritten as : A Vcd

R C R C

;
2R EE R C

and from (8) : A Vcd A Vcs

R C
RC

...(10)

From (10) it can be seen that the common-mode gain is much smaller with differential output than
with single-ended output. Thus, for example, to achieve maximum CMRR for an op-amp, the input
differential stage is often a balanced one with the output taken differentially.
H Jay

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Analogue Electronics 1 ENEL3TA

Differential Amplifiers

Common-mode Input Resistance

v ic
. Adding the BJT output
2 ib
resistance ro to the equivalent half-circuit of Fig. 8 and omitting RE, we obtain Fig. 9. Since the
common-mode gain is very small (<<1, ideally zero) the output voltage will be close to zero and
hence effectively grounded. Using this simplification, we obtain the equivalent circuit of Fig. 10.

Following Fig. 7, the common-mode input resistance R i cm

ie

ie
ib
2.Ri cm

v ic

v C1 0V

ie
re

ro

ib
2.Ri cm

v ic

RC

ie
re

T-model

2REE

2REE

Figure 9

ro

Figure 10

From Fig. 10, neglecting re (since re << 2REE // ro),

r
v ic ( + 1) i b (2R EE // ro )

= ( + 1) (2R EE // ro ) R i cm ( + 1) R EE // o
2
ib
ib
This should be obvious from Fig. 10 using resistance reflection (neglecting re).
Since REE & ro are usually large, Ri cm typically will be very large.
2R i cm =

(11)

Exercise 1
+15 V

The differential amplifier in Fig. 11 uses

BJTs with = 100. Evaluate the following:
(a)
(b)

(c)
(d)
(e)

The input differential resistance Rid.

The differential voltage gains:
vo
vo
and
(neglecting ro).
v sig
v id
The worst-case common-mode gain
if the collector resistors are matched
to within 1%.
The CMRR, in dB.
The common-mode input resistance
Ri cm (assuming VA = 100 V).

RC
10k

RC
10k

v sig

v sig

Q1

RE
150

+
vid

RS
5k

vO +

vC1

RS
5k

Rid
IT = 1mA

vC2

Q2
RE
150

REE
200k

Figure 11
With the output voltage reference polarity as shown, identify the inverting and non-inverting inputs.

H Jay

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2.

Analogue Electronics 1 ENEL3TA

Differential Amplifiers

Biasing of BJT and MOS Integrated Circuits

Integrated circuit technology does not allow for fabrication of high-value resistors (e.g. > 30 k ) or
high-value capacitors (e.g. > 50 pF). Hence the biasing techniques used for discrete BJT circuits
(such as in Electrical Principles 2) which typically required high-valued resistors ( > 100 k ) and
high-value coupling and bypass capacitors ( > 1 F) cannot be implemented in ICs.
The biasing in IC design is based on the use of constant-current sources. On an IC chip with several
amplifier stages, typically a constant dc reference current is generated at one location and this is
then replicated at other locations to bias the various amplifier stages through a process known as
current-steering. The amplifier stages in ICs are direct-coupled (dc-coupled).
The current sources used in ICs are formed from interconnected transistors known as current
mirrors. There are many different current mirror circuits of varying complexity and these can be
combined in various ways to form current-steering circuits. Current mirrors are used to implement
the biasing current source (IT, REE) such as in the BJT differential pair of Fig. 1 and they are also
used to replace load (collector) resistances (RC) in active loads.

Current Mirrors
2.1 Basic 2-BJT current mirror
+ VCC
Rref

RO

Iref
VCE1
= VBE

IC
Q1

2.IB

IB

IB

VBE

IC = IO
Q2

VCE2

-VEE

Figure 12
Fig. 12 shows the basic 2-BJT current mirror circuit with input reference current Iref and output
current Io. In this npn version both currents flow into the mirror producing a current sink.
From the circuit connection VBE1 = VBE 2 = VBE , thus for identical (matched) BJTs:
Assuming VCE1 = VCE 2 then I B1 = I B2 = I B and I C1 = I C 2 = I C = I O
I ref = I C + 2 I B = I C + 2

IC
2
2
= IC 1 +
= IO 1 +

I O = I ref

1
2
1+

(12)

Usually >> 2 , hence I O I ref so the output current mirrors the reference, hence the name.
The output resistance RO is determined by BJT Q2 :

H Jay

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R O = ro (Q 2 ) =

VA + VCE 2 VA

IO
IO

(13)

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Differential Amplifiers

The input current Iref may be a current source (or signal), or, as usual in bias circuits, a constant
reference current, typically produced via +VCC and Rref as in Fig. 12 giving:

I ref =

VCC ( VEE ) VBE VCC + VEE VBE

=
R ref
R ref

(14)

Mirror Ratio:
We define the ratio of output current IO to input current Iref to be the mirror ratio (MR).
I
1
Hence from (12) assuming identical (matched) BJTs: MR O =
[ 1 for >> 2 ]
I ref
2
1+

Mirror ratio scaling:

A very useful modification of the basic current mirror results if the mirror ratio can be changed
from unity. To alter the BJT mirror ratio we use the fact that the reverse saturation current (IS) of
the BJT is proportional to emitter area. Hence by changing the relative areas of the emitters
(emitter area scaling) of the BJTs, the IC designer can modify the mirror ratio.
A
Assume in Fig. 12 the emitter areas AE1 for Q1 and AE2 for Q2 are scaled such that E 2 = m .
A E1
Then I C 2 = m I C1 ; I B2 = m I B1 and from (12):
1
m
I O = m I ref
and MR =
thus if >> (m + 1) I O m I ref
(15)
m +1
m +1
1+
1+

Early Effect:
The above analysis has assumed the BJTs have the same VCE. Usually VCE 2 > VCE1 (= VBE ) and
thus due to the Early effect2 and hence the finite output resistance of Q2 there will be a mismatch
between IO and Iref with I O > I ref as shown in Fig. 13.
IC
IO = IC2
IC1

-VA

0 VCE1= VBE

VCE2

VCE

Figure 13
This may be accounted for by modifying (12) or (15) as follows:
V
VBE
V
VBE
1
1
I O = I ref
1 + CE 2
or
I O = m I ref
1 + CE 2
VA
VA
2
m +1
1+
1+

(16)

Current mirror sources and sinks:

The mirror circuit in Fig. 12 uses npn BJTs producing a current mirror sink. A similar circuit in
inverted form using pnp BJTs may be used to create a current mirror source with both currents
flowing out of the BJT collectors (see texts).
2

Electrical Principles 2: Notes on BJTs: p4.

H Jay

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Analogue Electronics 1 ENEL3TA

Differential Amplifiers

2.2 Multiple-output mirror (repeated mirror, or current repeater)

+ VCC
Rref
Iref
(n+1)IB

IC
VCE1
= VBE

IB

Q1

IO1

IO2

IO3

nIB
Q2

VBE

Q3

-VEE

Q4

n outputs

Figure 14
The basic 2-BJT mirror may be simply extended to have multiple identical current outputs by
connecting several identical output BJTs to the diode-connected biasing BJT Q1 as shown above.
1
(17)
Hence replacing 2IB by (n+1)IB equation (12) becomes: I O1 = I O 2 = I O3 = ..... = I ref
n +1
1+

Obviously, this may be developed further by scaling the areas of the output BJTs so that, for
example, area Q3 is m times area Q1, Q2 and hence I O 2 = m I O1 ... etc. Thus multiple output
currents of different ratios to the reference current may easily be generated and this is used
extensively in the biasing circuits of ICs 3 (e.g. in current steering circuits see later).

Improved Current Mirrors

2.3 Buffered current mirror (mirror with base-current compensation) 4
The error caused by finite in the above current mirrors may become substantial if
error may be greatly reduced by adding a BJT buffer (Q3) as in the circuit of Fig. 15.

is low. This

+ VCC
Rref
Iref
VCE1
= 2.VBE

RO

IB3

Q3

I C = IO
Q1

IB

2.IB
IB

VBE

I C = IO
Q2

VCE2

-VEE

Figure 15
3
4

Sedra & Smith: 4th Ed: p513-514, 5th Ed: p570-571; Jaeger & Blalock: 2nd Ed: p333-335, 1186-1189, 3rd Ed: p899-902
Sedra & Smith: 4th Ed: p515-516, 5th Ed: p650-651; Jaeger & Blalock: 2nd Ed: p1189-90, 3rd Ed: p902

H Jay

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Analogue Electronics 1 ENEL3TA

Differential Amplifiers

From the circuit in Fig. 15: VBE1 = VBE 2 = VBE

Hence for matched BJTs I B1 = I B2 = I B I C1 = I C 2 = I O

I ref = I O + I B3 = I O +

also I E3 = 2 I B I B3 =

2 IO
2 IB
2
= IO +
= IO 1 +
+1
+1
2 +

I O = I ref
1+

Hence the circuit provides I O I ref even for relatively low values.

2 IB
+1

...(18)

2 +

V
Also R O = ro (Q 2) A
IO

2.4 Wilson current mirror 5

+ VCC

RO

Rref
IO

Iref

VCE1
=2.VBE

IE3

IC
Q1

VO

Q3

IB3

ro ( Q 3)
2

2.IB

IB

IC

IB

Q2

VBE

-VEE

Figure 16
The Wilson current mirror of Fig. 16 is a clever modification to the buffered current mirror. It also
achieves base-current compensation and hence provides I O I ref even for relatively low values.

RO

In addition, it also provides a much greater output resistance:

ro ( Q3)
2

...(19)

The disadvantage is that output voltage cannot go as close to the negative supply rail as in the
previous circuits: VO > VBE + VCEsat (Q3) 1V (to keep Q3 in active mode).

Exercise 2
Show that for the Wilson current mirror:

I O = I ref
1+

(20)

2 + 2

Sedra & Smith: 4th Ed: p516-517, 5th Ed: p651-652; Jaeger & Blalock: 2nd Ed: p1198-1201, 3rd Ed: p909-912

H Jay

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Differential Amplifiers

2.5 Widlar current mirror 6

Scaling of BJT areas can provide mirror ratios of at most about 10:1 or 1:10. When much larger
mirror ratios are required, the Widlar current mirror provides output current that can typically be
several orders of magnitude smaller than the input reference current. This is achieved by including
a small series resistance in the emitter of the output BJT that reduces VBE. Since IC is exponentially
related to VBE a small reduction in VBE can produce a very large reduction in IC.
It also provides a much larger output resistance R O (1 + g m R E ) ro where R E = R E // r
+ VCC
Rref

RO

Iref

IO

Q1

Q2
VBE1

VBE2
RE

VRE

-VEE

Figure 17
Recall for a BJT: I C = IS e VBE

VT

and thus VBE = VT ln (I C IS ) .

Hence in Figure 17, neglecting base currents and assuming matched BJTs:

VBE1 = VT ln (I REF IS )
VBE 2 = VT ln (I O IS )

VBE1 VBE 2 = VT ln (I REF I O )

But VBE1 = VBE 2 + VR E

VR E = I O R E = VT ln (I REF I O )

(21)

Thus the introduction of RE reduces the current IO and the value of the resistor required can be
determined using equation (21).
The design and advantages of the Widlar current mirror are illustrated in the following example.

Example 1
Figure 18 shows two circuits for generating a constant current sink of 10 A which operate from a
10 V supply. Determine the value of the resistors required assuming that VBE = 0,7 V at IC = 1 mA
and neglecting the effect of finite .

Sedra & Smith: 4th Ed: p517-520, 5th Ed: p653-656, 611-612; Jaeger & Blalock: 2nd Ed: p1194-1196, 3rd Ed. p906-907

H Jay

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Analogue Electronics 1 ENEL3TA

Differential Amplifiers

+ 10 V

+ 10 V

R1

R2

Iref

Iref

IO

Q1

IO

Q1

Q2

Q2

VBE1

VBE1

(a)

(b)

Figure 18

VBE2
R3

For circuit (a) we need to find VBE1 for Iref = 10 A. We know VBE = 0,7 V at IC = 1 mA.
Hence
10 A = I e VBE1 VT
S

1mA = IS e 0,7

VT

( )

VBE1 = 0,7 + VT ln(10 A 1mA ) = 0,7 + 0,025 ln 10 2 = 0,585 V

Thus

R1 =

10 0,585 V
= 942 k (which is rather large, unsuitable for IC design).
10 A

For the Widlar circuit (b) we first select a suitable Iref .

10 0,7 V
Choosing Iref = 1 mA requires R 2 =
= 9,3 k which is suitable for IC design.
1mA
Using (21): 10 A R 3 = 0,025 ln(1 mA 10 A ) R 3 = 11,5 k which is now also suitably small.
An additional advantage of the Widlar mirror is that the output resistance is large. To determine an
expression for the output resistance, replace Q2 in Figure 17 with its small-signal -model and apply
a test voltage vx to the collector as shown in Figure 19. The base of Q2 is connected to signal
ground (VEE) via the diode-connected BJT Q1which has a small incremental resistance (re). Since
re << r the base of Q2 is thus assumed to be grounded.
c ix

ro

gm v

vx

e
RE

Figure 19
H Jay

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Differential Amplifiers

In Figure 19 RE and r are in parallel hence let R E = R E // r

To determine the output resistance RO apply vx and determine ix then R O = v x i x
v
ix =
R E
v + v
ix = gmv + x
ro
v x = v + (i x g m v ) ro
Subst. (22) into (24):

v x = v

v
1
ro g m v ro = v g m +
v ro
R E
R E

(22)
(23)
(24)
...(25)

Subst. (v x + v ) from (25) into (23):

ix = g m v g m +

RO =

Now

vx
=
ix

1
v
R E

v gm +

1
v ro
R E

1
gmv gm +
v
R E

...(26)

1+ gm +
=

1
ro
R E

1
R E

= R E + (1 + g m R E ) ro
Since R'E is small:

R O (1 + g m R E ) ro

...(27)

Example 2
Find the output resistance of each of the current mirror circuits in Example 1. Use VA = 100 V and
= 100.

V
100 V
RO = A =
= 10 M
I O 10 A

(a)

No RE and I O = 10 A :

(b)

R E = 11,5 k and I O = 10 A :
V
100 V
ro = A =
= 10 M
I O 10 A

gm =
r =

I O 10 A
=
= 0,4 mA / V
VT 25 mV

100
=
= 250 k
g m 0,4 mA / V

R E = R E // r = 11,5 k // 250 k = 11k

R O = 1 + 0,4 10 3 11 103 10 M = 54 M

H Jay

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Multiple output mirrors (current repeaters or current steering circuits) as outlined in section 2.2
(p.10) may also be extended using the Widlar principle (i.e. adding emitter resistances) to produce
multiple output currents with ratios to the reference current much larger than possible by area ratios.
The high output resistance may be another reason for using the Widlar principle in such current
steering circuits.

2.6 MOS current mirrors 7

MOS current mirrors may be implemented in similar fashion to most of the BJT current mirrors, but
inaccuracy in mirror ratio due to finite has no counterpart in MOS mirrors, hence there is no need
for buffering. The simple basic MOS current mirror sink using n-channel MOSFETs is shown in
Fig. 20.
VDD
Rref

IO

Iref
VO
Q1
VSS

Q2

VDS2

VGS

Figure 20
Q1 is in saturation by connection; hence assuming matched MOSFETs with identical Vt , k n , and
and providing Q2 is in saturation, then:
I O = I ref

(W L)2
[1 + (VDS2 VGS ) ]
(W L)1

The output resistance is:

RO

provided VDS2 (VGS Vt ) .

VA
1
=
IO IO

...(28)
(29)

In similar fashion to BJT mirrors, multiple outputs may be connected to form current repeaters, and
using p-channel MOSFETs, mirror sources may be produced. The Widlar technique may be
implemented in MOS mirrors, and the Wilson mirror may be implemented in MOS form to provide
increased output resistance.

Notes (MOSFETs): p81-82;

Sedra & Smith: 4th Ed: p402-408, 533-535; 5th Ed: p562-567, 649-650, 652-653;
Jaeger & Blalock: 2nd Ed: p1181-1184, 3rd Ed: p894-897

H Jay

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2.7 Current-Steering Circuits (using current mirrors)

Once a constant current is generated it can replicated to provide dc bias currents for various stages
in an IC, and this is easily achieved using current mirrors.

2.7.1

BJT current-steering circuit

A simple example using BJT current repeaters to
produce current sources and sinks is shown in Fig.
21.

+VCC
Q3

Q1

Q5

IREF

Q6

I1

I3

I2

I4

In IC form, the paralleled BJTs would be

implemented by varying the junction areas, e.g.
Q5 & Q6 would be one BJT twice the area of Q1 and
Q7, Q8 & Q9 would be one BJT three times the area
of Q2.
Hence in Fig. 21, neglecting the
effect and
assuming VA
, I1 = I 2 = I REF ; I 3 = 2 I REF ;
I 4 = 3 I REF

Q2

Q4

Q7

Q8

Q9

VEE

Figure 21

2.7.2

The Widlar principle may also be used, by

including emitter resistances to produce current
ratios much larger than possible with variation in
junction areas.

MOS current-steering circuit

A similar example using CMOS
technology is shown in Fig. 22.

+VDD
VSG5
R

IREF

Q4

sink

Q5

I2
Q1

Q2

I5

I4 = I3
Q3

Q1, Q2 & Q3 form a two-output current

mirror where Q2, Q3 sink currents I2, I3.
I4 = I3 is the input of the PMOS mirror
Q4 & Q5 where Q5 sources current I5.
Assuming = 0 :

source

I 2 = I REF

VGS1
VSS

I 4 = I3 ;
Figure 22
To keep Q2, Q3 in saturation: VD 2 , VD3 VSS + VGS Vtn

(W L )3
(W L )2
; I 3 = I REF
(W L )1
(W L )1
(W L )5
I5 = I 4
(W L )4

i.e. VD 2 , VD3 VSS + VOV1

Similarly to keep Q5 in saturation: VD5 VDD VOV5

Exercise 3
H Jay

Sedra & Smith: Exercise 5.25 p408 4th Ed. or Exercise 6.5 p567 5th Ed.
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The BJT Differential Amplifier with Active Load 8

+VCC
Q3

Q4
v
gm d
2
vd
gm
2
Q2

v
gm d
2

Q1

VO

RL

Vd

IT

RO

Figure 23
An important application of a current mirror is as a replacement for the load resistors of differential
amplifier stages in an IC op-amp. The basic circuit using a BJT differential amplifier is shown in
Fig. 23 where the current mirror is said to be an active load. The signal output current (and hence
the voltage gain) is effectively doubled by the active load mirror action, thus although the output is
single ended, the voltage gain is the same as would be obtained for a differential output with the
same loading conditions without an active load. Drawing a small-signal equivalent circuit:
VO

+
Vd

Rid

g m vd

rO
(Q2)

rO
(Q4)

RL

Figure 24
A Vd

VO g m Vd [ro (Q 2) // ro (Q 4) // R L ]
=
= g m [ro (Q 2) // ro (Q 4) // R L ]
Vd
Vd

To determine the maximum differential voltage gain achievable, assume RL is very large, hence:
I
I /2
V
V
g m = C = T ; ro (Q2) , ro (Q4) = A = A
VT
VT
IC IT / 2
A Vd

VO
I / 2 1 VA
V
= g m [ro (Q 2) // ro (Q 4) ] = T
= A
Vd
VT 2 I T / 2
2 VT

Thus, for example, if VA = 100 V; A Vd

100 V
= 2000
2 25 mV

Self-study Consider the MOS equivalent: a CMOS Differential Amplifier with Active Load 9
8
9

Sedra & Smith: 4th Ed. p522 - 525; 5th Ed. p733 - 736; Jaeger & Blalock: p1228 1232, 3rd Ed. P931 - 935
Sedra & Smith: 4th Ed. p536 - 537; 5th Ed. p728 - 731; Jaeger & Blalock: p1221 1226, 3rd Ed. P924 - 928

H Jay

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Multistage Amplifiers

4.1 Simple four-stage BJT op-amp

As an example of a multistage amplifier consider the four-stage BJT op-amp shown in Fig. 25.
The input stage of Q1 & Q2 is biased by the current source Q3 and is differential-in, differential-out
to give maximum common-mode rejection. The second stage of Q4 & Q5 is biased by the current
source Q6 and is also differential-in but the output is taken single-endedly which results in a factor
of 2 loss of gain. An alternative would be to use an active load (as described in section 3 above)
which would avoid the loss of gain.
The third stage comprising the pnp Q7 provides some voltage gain and dc level shifting to produce
zero output when the inputs are zero. The fourth and output stage comprises the emitter-follower
Q8 which provides the desired low output resistance and current drive capability.
+15 V
R1
20k

+
Vid

R3
3k

R2
20k

Q1

Q2

Q7
Q4

Q8

Q5

VO

RREF
28.6k
IREF
Q9

R4
2.3k

R5
15.7k
Q6
A6 = 4X

Q3

R6
3k

15 V

Figure 25

Exercise 4
4.1

Taking the inputs as grounded, perform an approximate dc analysis of the circuit of Fig. 25
and calculate the dc currents and voltages
assuming
is large, VBE = 0,7 V , VA
everywhere in the circuit. Note that Q6 has four times the area of Q9 and Q3.

4.2

Calculate the quiescent power dissipation in this circuit.

4.3

If Q1 and Q2 have

4.4

What is the common-mode range of this op-amp?

= 100, calculate the input bias current of this op-amp.

Exercise 5
Using the dc bias quantities determined in Exercise 4 to analyse the circuit in Fig. 25 to determine
the differential input resistance, differential voltage gain and output resistance. Assume = 100.

H Jay

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The MOSFET Differential Pair

The basic MOSFET differential pair is shown in Fig. 26 where the MOSFETs are assumed identical
(matched) and the dc biasing is controlled by a constant current source in similar fashion to the BJT
differential pair studied in section 1.
+VDD
RD

ID1

RD
VD1
Q1

VD2

ID2
Q2

VS

vG1

vG2
IT

RSS
VSS

Figure 26

DC analysis
The dc analysis can be simplified by making the following assumptions:
1. The output resistances of the MOSFETs are infinite: ro = ,
2. The output resistance of the current source is infinite: R SS = (the current source is ideal).
Assume VG1 = VG 2 = 0 . From the symmetry of the circuit it is obvious that the bias tail current
divides equally between the two MOSFETs so I D1 = I D 2 = I T 2 . Assuming the MOSFETs are
biased into the saturation region, the voltage at each drain will be VD1 = VD 2 = VDD I D R D .
VGS may be determined using the usual MOSFET saturation mode equation:
2 ID
IT
1
= Vt +
I D = k W
(VGS Vt ) 2 and hence VGS = Vt +
W
L
2
k
k W

( )

(L )

(L )

VS = VGS hence VDS = VD VS = VDD I D R D + VGS and for saturation VDS VGS Vt .

Small-signal operation
As for BJTs, the small-signal operation is easiest analysed by considering the circuit response to the
differential and common-mode components of the signals separately and working with the relevant
half -circuit model for each case. In the following analysis external load resistance RL has been
omitted for simplicity, hence where necessary replace RD by R L = R D // R L etc. as appropriate.
a.
Pure differential signals:
Consider the MOSFET differential pair with differential signals applied as in Fig. 27. For pure
differential signals (i.e. signals with zero common-mode component), points on the line of
symmetry are virtual grounds. (The dc supply rails are signal grounds, and at points such as
x in Fig. 27, by symmetry, the increase in signal current in one MOSFET is exactly matched by
the decrease in signal current in the other MOSFET hence the signal voltage at x is zero.)
H Jay

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line of
symmetry
+VDD
RD

iD1

RD
vD1

iD2

vD2
Q2

Q1
v
+ id
2

IT

v id
2

RSS
VSS

Figure 27
Hence for differential signals, the circuit is effectively two identical half-circuits each comprising
a single MOSFET (in common-source) with opposite polarity differential signal components
applied. We may thus draw an equivalent half-circuit and replace the MOSFET by an appropriate
model (e.g. model) as in Fig. 28:
g
+

v id
2
gm

vid
2

vD1
RD

Figure 28
The small-signal equivalent circuit has been simplified to effectively two half-circuits each of
which is a simple familiar MOSFET CS circuit. From the equivalent half-circuit:
v

id
v od v D1 v D 2 2 v D1 v D1 g m 2 R D
A Vd (diff. o/p)
=
=
=
=
= g m R D ...(30)
v
v
id
id
v id
v id
v id

v id

gm R D
v
v
v
1
2
A Vds (single - ended o/p) os = D1 = D1 =
= (g m R D )
v
v id v id 2 v id
2
2 id
2

...(31)

and obviously R id =

b. Pure common-mode signals:

Consider the MOSFET differential pair redrawn in fully-symmetric form with identical
common-mode signals applied as in Fig. 29. For pure common-mode signals (i.e. signals with
zero differential component), points on the line of symmetry are open circuits since no current
flows in these links.

H Jay

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line of
symmetry
+VDD
RD

RD
vD1

vD2
Q2

Q1
v ic

v ic
2RSS

IT
2

IT
2

2RSS

VSS

Figure 29
Hence for common-mode signals, the circuit is effectively two identical half-circuits each
comprising a single MOSFET (common-source with RS) with equal common-mode signal
components applied. We may thus draw an equivalent half-circuit and replace the MOSFET by
an appropriate model (e.g. model) as in Fig. 30:
g

vD1

g m v gs
v ic

v gs
s

RD

2RSS

Figure 30
If the output is taken single-endedly, then from the equivalent half-circuit in Fig. 30:
g m v GS R D
v
gm R D
A Vcs (single - ended) D1 =
=
(1 + g m 2R SS )
vic v GS + g m v GS 2R SS
R
D (if g m 2R SS >> 1)
2R SS
and hence, CMRR

H Jay

A Vds g m R D 2R SS

= g m R SS
A Vcs
2
RD

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...(32)

...(33)

Jan 2010