The Synchronous Digital Hierarchy (SDH) : - I Part

The Synchronous Digital Hierarchy (SDH)
- I part by JM Caballero
Trend Communications
PDH limitations
the multiplexing is bit oriented (second, third and

fourth hierarchy)
it is not possible to execute direct add&drop of

low speed tributaries
poor monitoring capacity

because computers are
byte oriented
lack of management standards and short space to

implement them (S bits)
lack of standardization
between Japan, USA and
rest of the world
lack of optic standards

just proprietary solutions
no mechanisms to manage the quality, just for

2Mbit/s with CRC4
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Causes to define SDH
The Antitrust law at US followed by Bell break into

small companies.
Was necessary to interconnect new PTTs: SONET

definition
B-ISDN specification to integrate any traffic: SDH

and ATM standardization
Advanced management
needs: computers and telecom must work together
Requirement for having

new infrastructures to fit
any traffic: data, voice,
multimedia
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bytes vs. bits
frame 1
125 s
0
frame 2
125 s
1 byte
n 0
rate =
8 bits
12510-6seg.
= 64Kbit/s
Standardize since 1988 when appeared the G707, G708, G709 CCITT recommendations
SDH is byte oriented, it means that a byte is the unit for mapping and multiplexing
STM-N is the name for the transport frames. They have always a period of 125s
An important consequence is that in SDH 1 byte represents a 64 Kbit/s channel
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SDH objectives (i)
direct internetworking
between equipments
scalability in transmission speeds until 0 Gbit/s
direct add&drop for low

speed tributaries
capabilities for new control channels supervision, maintenance &

service
support to fit any application: audio, video, voice
remote and centralized

management
easy migration from PDH

networks
fault tolerance
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SDH is a flexible architecture
SDH has a reference model
It is an standard universally accepted
SDH is highly compatible with SONET
very efficient to manage circuits
fast circuit definition from a centralized point
advanced facilities for quality monitoring
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Circuit provisioning
services
Internet
Frame Relay
RTB
ATM
GSM
multiplexing, transport, routing, management, reliability
transport network
SDH
transmission media
cable/fiber/radio
SDH provides an efficient, reliable and flexible transport for circuits
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SDH architecture
client
server
Section
The network is a function of the connectivity
inputs
Function of
outputs
connectivity
The model considers the network as a connectivity function
it has a set of input/output interfaces
there are function to match requirement with capacities
The complexity of the functions moves to use simplified models which allow to define interfaces
and overheads
SDH architecture
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Topologic partitioning
The topology describes the potential connections and are expressed as relations between
points on the network
the network is an encapsulation that is able to be splitted repeatedly in subnetworks interconnected through links
the subnetworks are decomposed until the desired level or when nodes and transmission
media are visible (the last layer)
nodes are the network elements: switches, multiplexers, and regenerators
SDH architecture
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Functional partitioning
network connection
Client layer
digitalization
codification
Server layer
add/drop
overheads
path
Layer Adaptation: unifies the information format using

techniques like mapping, justification, multiplexion, overheads
Layer Termination: adds/drops overheads in order to allow
a service monitoring and supervision
The model allow to define independent structures but connected. Each layer can be seen as a
network which can be divided in sublayers
In PDH the relationships are directs, in SDH are complex and the transport service has been
divided in two layers:
one to connect terminal points (paths)
one to connect routes (sections)
The model permits also a control of the network elements and a full connection compatibility
because all the vendor refer to the same abstract model.
SDH architecture
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Reference points
Network connection
Layer Adaptation
Layer Adaptation
AP
AP
Layer Termination
Network connection
Layer Termination
Subnetwork
link
TCP
CP
CP
TCP
CP
CP
AP - Access Point: it is the place where are executed the adaptation functions like framing,
justification, multiplexing, and alignment. There are two by connection. They are the edge
points which can interchange client information
CP - Connection Point: it is the place where are implemented the atomic connections. The
CP association is known a Subnetwork. A link is the association of two subnetworks. These
points are monitored in order to know the network status
TCP - Terminal Connection Point: it is the edge CP where it is checked the data integrity. A
Network Connection is the association of two TCP
SDH architecture
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Connectivity
Client Path
Client layer
Server layer
AP
AP
Network Connection
Link Connection
Subnetwork
Connection
Subnetwork
Connection
TCP
TCP
CP
CP
CP
CP
Server Path
A Network Connection is a concatenation of basic elements. The edge points (in/out) are
TCP
Basis elements are subnetwork connections between CP and links between Subnetworks.
The connections can be half-duplex, full-duplex, point to point, point to multipoint, multipoint
to multipoint
The connection monitors the client information integrity
SDH architecture
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Transport stratification
2 Mbit/s circuit
2 Mbit/s level
VC12 level
DXC
DXC
Subnetwork
Subnetwork
connection
VC12 level path
connection
VC4 level
Layer Adaptation
Layer Termination
VC4 level path

STM level
Layer Adaptation
Layer Termination
STM-1 section
transmission media
There is a client/server relationship with headers and adaptation function similar to the OSI
layered model used to explain protocols
SDH architecture
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Transference integrity: trails

client connection
Layer Adaptation
Layer Adaptation
trail
AP
overheads management
TCP
CP
CP
CP
TCP
CP
The source delivers information which is adapted: digitalization, codification,...
The trail define the transport capabilities and it is able to monitor the integrity and quality of
the information interchanged between AP
These functions allow to implement the OAM functions (Operation, Administration, and
Maintenance)
The trails have associated the overhead between the interchange units
SDH architecture
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Network Node Interface (NNI) location

NNI
NNI
NNI
NNI
Tributaries
Tributaries
Tributaries
MUX
sinc.
Media :
PDH
ATM
MUX
sinc.
CXC
DIGITAL CONNETION
fiber
wireless
MUX
sinc.
Media :
fiber
wireless
MUX
sinc.
ACCESS
PDH
ATM
MUX
sinc.
MUX
sinc.
Tributaries
NNI (Network Node Interface) are the connection between subnetworks:
NNI are internal network interfaces used to transmit the STM-N frames
NNI interface is defined at the access, the transport network; and the interconnection units
NNI, PDH, and ATM are SDH network interfaces. They are standards to guarantee the world
network interconnections
SDH architecture
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Reference model
IP
Frame
RTB ISDN Relay
IP
ATM
ATM
Frame
Relay ISDN RTB
interchange unit
paths
sections
SDH frame
VC-12
low order VC-12
low order VC-12
high order VC-4
VC-4
high order VC-4
seccin
multiplexing
de multiplexin
section
MSOH
multiplexing section
seccin
regeneration
de regeneracin
section
RSOH
regeneration section
physical interface
STM-1
physical interface
optical/electrical/radio
NNI
SDH architecture
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Network elements and topologies
Section
Regenerators (REG)
STM-N
REG
STM-N
It maintains the physical the signal by means of strength, shape and delay
attenuation: reduction of strength of the signal per distance. Amplification
delay distortion: the velocity of propagation varies with frequency causing intersymbol interference. Signal needs equalization
noise: different causes like thermal noise, intermodulation, crosstalk, impulse noise is always present. The signal must be digitally filtered
SDH architecture
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Line Termination Multiplexors (LTMUX)
2M
8M
STM-1
L O -P T E
34M
H O -P T E
SDH
MUX
STM-N
45M
140M
Mux/Demux of plesiochronous circuits to/from STM-N frames
The input and the output of the circuit from the SDH network define the paths
Are useful for line topologies providing easy migration form legacy PDH networks
Overhead management
SDH architecture
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Multiplexers (Mux/Demux)
STM-N
SDH
MUX
STM-M
M >N
STM-N
Mux/Demux of STM-N signals in/from STM-M
Does not modify the contents of transported information
Multiplexion of four SDH signals:

4 x STM-1 = STM4
4 x STM-4 = STM16
4 x STM-16 = STM64
SDH architecture
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Add & Drop Multiplexer (ADM)
West
East
STM-M
STM-M
STM-N, PDH
Put / get PDH circuits in/from STM-N frames
configures SDH rings topologies
can provide the network with fault tolerant capacities
SDH architecture
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Digital Cross-Connect (DXC)
STM-N
STM-N
STM-N
STM-N
Switchs STM signals as well as add&drop funcionalities.
implements all the network element capacities
absolutly flexible for subnetwork interconnections
allows SDH networks interconnection
SDH architecture
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Point to point topology
MUX
2M
34M
LPT
HPT
MUX
STM-1 SDH
MUX
REG
STM-N MUX
MUX STM-N
SDH STM-1
MUX
2M
HPT
LPT
34M
45M
45M
140M
140M
Simples but scalable to complex topologies
Transport STM signal between two points
Allows an smooth migration from legacy PDH networks to SDH
SDH architecture
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Ring topology
back up ring
ADM
ADM
ADM
tributary
active ring
tributary
ADM
flexible and scalable
provide a native way for reservation circuits
allow circuits add&drop at any node
SDH architecture
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Star and hub configurations

E
A
B
C
Star PDH network
C
SDH Network
physical topology with star configuration
and logical topology with ring configuration
Both configurations allow an smooth migration from PDH infrastructures
SDH architecture
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Transport design
National Backbone
STM-16
Primary Network
STM-4
Access Network
STM-1 or PDH
The networks are designed with topologies that try to drive a lot of traffic through the same ring
and a few inter rings or inter layer
SDH architecture
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Low Order Paths & High Order Paths

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
The Virtual Container (VC) across the SDH defining a path and two edge points. One where
the VC is inserted and the other where it is dropped. There are two types of paths:
The High Order Path (HOP) links two points with a high rate transport capacity. The content
can be a a circuit of 140 Mbit/s or combination of circuit of 1.5, 2, 6, or 8 Mbit/s
The Low Order Path (LOP) links two points with a high rate transport capacity. The content
can be a a circuit of 1.5, 2, 6, or 8 Mbit/s
The circuits of 34 and 45 Mbit/s can be transported both, into High or Low Order Path
SDH architecture
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Multiplexing Section (MS)

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
A section is the space limited by two network elements linked by a transmission media. There
are two types: the Multiplexing Section (MS) and the Regeneration Section (RS)
The MS is the space defined by two contigous multiplexers. Each MS manages an specifc
overhead to control the multiplexers by means of :
quality monitoring with alarms/errors detection between Multiplexers
provide voice and data channels to configure and operate the Multiplexers
facilities for synchonization and automatic protection (APS)
SDH architecture
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Regeneration Section (RS)

LTMUX
LO HO
MUX
REG
REG
SECT
DXC
REG
SECT
REG
REG
SECT
ADM
REG
SECT
LTMUX
HO LO
REG
REG
SECT
REG
SECT
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
HIGH ORDER PATH

LOW ORDER PATH
The RS is the space betwen two regenerators united by the any media: fiber, wireless, coaxial.
(Pay attention that a Multiplexer works as a Regenerator too.)
Each RS manages an specifc overhead to control the Regenerators by means of:
quality monitoring with alarms/errors detection between Regenerators
provide voice and data channels to configure and operate the Regenerators
framing and contents information
SDH architecture
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Regeneration process
Regeneration Section
Original signal
Regenerated signal
REG
REG
ADM
attenuation
Regenerator
Multiplexer
noise
distortion
Regenerator
The optical signal must be amplified to compense the attenuation, distortion, and noise during the fiber, cable or wireless propagation.
the signal is converted to an electronic signal, then it is filtered and amplified and finally it is
converted back to its original nature
onother technique to amplifly optical signals is to use Optical Fiber Amplifier (OPA). It consists of a fiber segment (about 70 mtr long) doped with erbiumis and pumped with a light
that excites the erbium. And then when a signal passes through the fiber more photons out
than photons in: the signal has been amplified
SDH architecture
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Transport Services
2 Mbit/s PSTN
2 Mbit/s
34 Mbit/s
34 Mbit/s
ADM
ADM
ADM
ADM
ADM
A
DM
STM-16
STM-1
DXC
STM-1
ADM
ADM
STM-1,4
STM-1
ADM
ADM
2 Mbit/s
34 Mbit/s
140 Mbit/s
C
irc
ui
t
ADM
ADM
Internet
STM-4
LTMUX
140 Mbit/s
ADM
ADM
ADM
ADM
155 Mbit/s
ISDN
LTMUX
ATM
ATM
2 Mbit/s
GSM
SDH provides circuit to public switched and routed networks
SDH architecture
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Security
Section
Security services
When a circuit goes down traffic can not stopped. Reliability is one of the strongest
characteristics of SDH networks. In order to assure that has been defined the following
strategies:
diversification
all the traffic between two sites are divided in several circuits. When one of them goes down
the rest of the circuits continue working on
restoration
the routing is a task of the client network (IP, ATM)
when a circuit goes down an specialized multiplexer looks for an available circuit and switches the traffic to the alternate path
protection
the routing is a task of the transport network (SDH)
alternate circuits have been assigned previously, when a circuit goes down the multiplexer
switched the traffic to the back up resource
SDH architecture
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Diversification
route 1 (50% C1-C2)
C1
C2
D
route 2 (50% C1-C2)
The circuits, between two points, are established using different physical routes. A fault in a
transmission route interrupts just a part of the traffic.
It has been used for PDH voice traffic
It is an acceptable strategy for no critical circuits
In order to provide the same service level it is required to duplicate the number of circuits
But most of the times it is no admissible, or possible, to reserve an unused route for each of
the network circuits
SDH architecture
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Restoration
A
(5,2)
(4,2)
(7,0)
(6,0)
(4,5)
(3,4)
(7,7)
(5,2)
(11,3)
(a,p) =(active circuits, protection circuits)

There is not a previous assignation of the circuits.
If an active circuit gets down then a protection protocol is executed in order to provide an
alternative route
The protection circuits share the same network elements and transmission media that are
used by the active circuits
Pay attention on that: the number of protection circuits is smaller than the active. Using a
relation equals to 1/2 for protection circuits could be enough
Usually the relation goes from 40% to 80%
SDH architecture
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Protection (i)
The mechanism is similar to the restoration technic, but there is an previous assignation of
circuits before the fault appears
SDH path protection
multiplexing section protection for line topologies
multiplexing section protection for ring topologies
multiplexing section shared protection for line topologies
virtual container protection
SDH subnetwork protection

Is a specialized protection mechanism for all network topologies. It can be used for protecting
parts of the network or all the network
with internal supervision (witch uses information about the own network for switching)
with no intrusive supervision (witch uses associated information for switching)
SDH architecture
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Linear protection of multiplexing section
Same traffic in S and P
MUX
1+1
MUX
high priority
Different traffic in S and P
service (S)
protection (P)
MUX
MUX
low priority
1:1
1:N
MUX
MUX
SDH architecture
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Specialized protection: 1 fiber rings

Circuit in normal conditions
A circuit in bakup
B circuit
protection ring
service ring
B circuit
ADM
ADM
ADM
ADM
ADM
A circuit
Circuit under protection
ADM
A circuit
B circuit
A circuit in bakup
one active ring and one protection ring
a new protection ring is established at the multiplexer edge of the fault
all the rings are unidirectional
B circuit
SDH architecture
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Ring shared protection with 2 fiber


service circuits using
protection services
service circuits
ADM
ADM
ADM
service and protection rings
two active rings in a single fibre
service circuits
two active rings of one fiber
n/2 active circuits and n/2 protection circuits per section
to implement uses K1, K2 bytes

protection services
SDH architecture
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Specialized protection in 2 fiber rings


circuito A
en back up
A circuit
service&protection rings
ADM
ADM
1 active ring of two fibers
1 protection ring of two fibers
Note that rings are bidirectional
ADM
ADM
AD
M
ADM
circuito A
circuito A
en back up
SDH architecture
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SDH transport services

STM-1
AUG
VC-n
C-n
+ AU
+ HO POH
(pointer)
Mbit/s
140,
33 44 ,, 44 55
+ stuffing bits
+ justificati on bits
+ overhead bits
TUG
TU-n
+ TU
(( pp oo ii nn tt ee rr ))
VC-n
+LO POH
C-n
M
Mbbiitt//ss
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
Section
The SDH multiplexing map

10 Gbit/s
STM-64
2,5 Gbit/s
STM-16
622 Mbit/s
STM-4
155 Mbit/s
x1
AUG16
x4
x1
AUG16
x4
x1
AUG4
x1
x1
x4
x1 AUG
STM-1
x1
AU416c
VC416c
AU44c
VC44c
AU-4
VC-4
x1
C416c
x1
C-44c
x1
C-4
ATM:149760 kbit/s
E4: 139264kbit/s
C-3
ATM:48384kbit/s
T3:44736kbit/s
E3: 34368 kbit/s
x3
SI)
( AN
51 Mbit/s
x1
STM-0
x1
TUG-3
x3
AU-3
TU-3
VC-3
(ANSI)
VC-3
x7
(AN
SI)
x7
x1
TUG-2
TU-2
VC-2
C-2
ATM:6874kbit/s
T2: 6312kbit/s
TU-12
VC-12
C-12
ATM:2144kbit/s
E1:2048kbit/s
TU-11
VC-11
C-11
ATM 1600 kbit/s

T1: 1544kbit/s
x3
Frame
Pointer processing
Aliingning
Multiplexing
POH addition
Tributary mapping
SI)
(AN
x4
Container
Group
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Transport of PDH circuits, ATM cells and IP datagrams
S T M -1
A U G
V C -n
C -n
+ AU
+ HO POH
(pointer)
M b i t /s
140,
34, 45
+ stuffing bits
+ justificatio n bits
+ overhead bits
TUG
T U -n
+ TU
(pointer)
V C -n
+L O P O H
C -n
Mbit/s
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
The mapping in standarized structures to provide circuits
PDH, and T-Carrier hierarchies are mapped in specific Containers (C-n)
ATM cells are mapped also in Containers C-n
IP datagrams are mapped in Containers C-n
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Containers
autonomous
master clock
synchronized
master clock
synchronism
PDH frames
SDH container
mapping
stuffing
justification
bit oriented
2Mbit/s
MUX
8Mbit/s
mapping
stuffing
justification
byte oriented
MUX
155Mbit/s
2Mbit/s
The mapping operation:
Multiplexers adjusts the capacity of containers with the provided info using byte stuffing
The containers have justification mechanism byte oriented also
The multiplexing function is a synchronous operation because all the network multiplexers
must use the same clock.
With PDH it is not mandatory to synchronize the network equipments
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The container C-4

C-4
11
Byte sequence in every row of a C-4 (260 bytes)
270
12
12
12
12
12
1 C-4 row
column 11
column 270
: information byte(s) from a 139264 Kbit/s s i g n a l
= CSSSSSOO
= I I I I I IJ S
: stuffing byte
I: Information bit
S: Stuffing bit
C: Justification control bit
J: Justification opportunity bit
O: Overhead bit
During the mapping operation the multiplexer receives the tributary which is placed into the
container, justification bytes are used to accomodate the clock differencies, and the stuffing to
fill the extra space up.
The C-4 container provides big capacity services
It provides transport for E4 circuits (139264 kbit/s)
ATM cell can be mapped directly in C-4
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The VC-4 Virtual Container

C -4 into a V C -4
10
1
11
270
J1
B3
C2
G1
F2
H4
F3
VC-4 Path
Overhead
(POH) is added
K3
9
N1
C4+POH=VC4
The Path Overhead (POH) is added and will travel together until the termination point
Only the termination multiplexer is allowed to modify the POH contents
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AU pointer association
1
STM-1
9 10
RSOH
10
270
VC-4
11
270
J1
B3
AUG
C2
G1
MSOH
F2
H4
F3
K3
POH
N1
The ALIGNING process associates a pointer
The pointer allows to find the VC-4
The pointer occupies always a fixed position inside the STM-1 frame. The VC-4 does not
occupies a fixed position in the frame to adapt clock impairments
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VC4 insertion to the STM-1 frame

V=150 km/h
VC-4
155 km/h
STM-1
STM-1
VC-4
VC-4
VC-4
STM-1
Containers exactly allocated
perfect synchronization
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VC4 insertion to the STM-1 frame (ii)

V<150 km/h
VC-4
VC-4
VC-4
VC-4
155 km/h
STM-1
STM-1
STM-1
Containers allocated
between two frames
common synchronization
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The STM-1 frame
Regenerator
Section
Overhead
S T M -1
9 10
RSOH
10
270
VC-4
11
270
J1
Administrative
Unit Group
B3
C2
Multiplexer
Section
Overhead
G1
MSOH
F2
H4
F3
K3
POH
N1
STM-1 = AUG + RSOH + MSOH
In the carrier STM-1 frame are included the section overheads RSOH y MSOH to control
and manage the network elements
The VC4 is floating inside the STM-1, it may change it position an integer number of bytes
inside the space reserved in the STM-1 frame. In this way, clock fluctuations between the
STM-1 and the VC-4 are absorved
The AU pointer always points to the position where the VC4 starts and follows possible fluctuations
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How to fill up the payload:

STM-1
1
270
9 10
RSOH
10
VC-4
11
270
J1
B3
C2
G1
MSOH
F2
H4
Z3
Z4
POH
Z5
Composition
2Mbit/s
34Mbit/s
140Mbit/s
1 VC4
3 VC3
21 VC12 + 2 VC3
21
42 VC12 + 1 VC3
42
63 VC12
63
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The STM-N frames

0
1
2
3
x4
0123
4
5
6
7
x4
4567
x4
8
9
A
B
x4
89AB
C
D
E
F
x4
CDEF
direct multiplexing
x16
0123456789ABCDEF
0123456789ABCDEF
Frame
Binary rate (kbit/s)
Short Id.
STM-1
155.520 kbit/s 155 Mbit/s
STM-4
155.520 x 4 = 622.080 kbit/s 622 Mbit/s
STM-16
622.080 x 4 = 2.488.320 kbit/s 2,5 Gbit/s
STM-64
2.488.320 x 4 = 9.953.280 kbit/s 10 Gbit/s
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The sequence transmission
J0 A2 A2 A2 A1 A1 A1
A1 A1
A1 A2
A2 A2 J0
Sequence is from top to down and letf to right

125s
The top left corner is frame alignment word.

This word is the first transmitted in order to get
sinchronization
125s
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Example: transport of 45 Mbit/s
45Mbit/s
SDH
45 Mbit/s
Section
Transport of 45 Mbit/s as Low Order Path (i)

TUG-3
TU-3
VC-3
x3
34
+ TU
pointer
STM-1
+ SOH
AUG
+ AU
pointer
VC-n
C-3
+ LO POH
+ stuffing bits
+ justification bits
+ overhead bits
+ HO POH
Complete sequence of mapping, framing, alignment and multiplexing of a circuit of 45 Mbit/s

in a STM-1 frame of 155 Mbit/s
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Asynchronous mapping in a C-3 container (ii)

1 1 1
25
1 1 1
25
Y I
1 1 1
Z I
25
I
Public Network
: Information bytes from a 43 Mbit/s tributary
X = SSC I I I I I
Y = CCSSSSSS
I: Information bit
S: Stuffing bit
O: Overhead bit
Z = CCSSOOSJ
C-3
3
45Mbit/s
86
C-3
VC-3
The public network can be a circuit for Interned, Frame Relay, ATM, leased....
mapping of a 45 Mbit/s signal in the C-3 container that is network synchronous
is also used for 34 Mbit/s transport with other mapping in the C-3
the frame period is 125 s
There are pointer justifications for clock differences adjustment
57/
63
Creation of the Virtual Container VC3 (iii)
2Mbit/s
VC-3
2
1
(85 columnas)
86
J1
C-3
B3
C2
G1
F2
VC-3
H4
F3
K3
9
N1
C -3
TU-3
Path overhead (POH) is added to the multiframe creating the VC3

58/
63
Multiplexing and creation of the TU3 (iv)
VC-3
T U -3
2
H1
H2
H3
86
J1
x1
B3
C2
G1
TU-3
F2
H4
F3
Pointer bytes
K3
9
N1
V C -3
a VC-3 plus a pointer is a TU-3
The pointer is always accessible and points to the frame start
TUG-3
59/
63
Creation of the TUG3 (v)
TU-3
T U G -3
1
1
86
H1
H2
J1
H3
B3
x1
C2
TUG-3
G1
F2
R
H4
x3
F3
9
K3
N1
VC-4
Using only a TU-3 a TUG-3 is created adding the corresponding stuffing bits
The pointer is still located in accessible positions
60/
63
Creation of the Virtual Container VC-4 (vi)
11
1
12
13
270
14
TUG-3
J1
B3
x3
C2
G1
F2 R
byte interleaving
3 TUG-3
VC-4
H4
F3
K3
9
( 3 x 86 = 258 columns )
N1
AU-4
stuffing bytes
A new structure is used for group all the three TUG-3 together
Then the POH overhead and the stuffing bits are added until the frame is completed
61/
63
Creation of the AU4 adding a pointer (vii)
STM-1
9 10
RSOH
10
VC-4
11
VC-4
270
270
J1
B3
C2
G1
MSOH
AU-4
F2
H4
F3
K3
N1
POH
STM-1
A new pointer is added, the AU-4 pointer that points to the first byte of the VC-4
The AU4 is in a fixed position of the frame and thus it can be easily located
This operation is known as alignment
62/
63
Creation of the STM-1 frame (viii)
VC-4
9 10
STM-1
270
RSOH
AU-4
AUG
MSOH
STM-1
RSOH: Regenerator Section Overhead
M S O H : Multiplexer Section Overhead
Section overheads, RSOH and MSOH, are added
The AUG administrative unit is placed in the frame
63/
63

PDH limitations

fourth hierarchy)


byte oriented

rest of the world


2Mbit/s with CRC4
2/
63

small companies.

definition

Advanced management

multimedia
3/
63
bytes vs. bits
frame 1
125 s
0
frame 2
125 s
1 byte
n 0
rate =
8 bits
12510-6seg.
= 64Kbit/s
4/
63
SDH objectives (i)
between equipments

speed tributaries

service

management

networks
fault tolerance
5/
63
6/
63
services
Internet
Frame Relay
RTB
ATM
GSM
transport network
SDH
transmission media
cable/fiber/radio
7/
63
SDH architecture
client
server
Section
inputs
Function of
outputs
connectivity
and overheads
SDH architecture
9/
63
SDH architecture
10/
63
network connection
Client layer
digitalization
codification
Server layer
add/drop
overheads
path

SDH architecture
11/
63
Reference points
Network connection
Layer Adaptation
Layer Adaptation
AP
AP
Layer Termination
Network connection
Layer Termination
Subnetwork
link
TCP
CP
CP
TCP
CP
CP
SDH architecture
12/
63
Connectivity
Client Path
Client layer
Server layer
AP
AP
Network Connection
Link Connection
Subnetwork
Connection
Subnetwork
Connection
TCP
TCP
CP
CP
CP
CP
Server Path
TCP
to multipoint
SDH architecture
13/
63
2 Mbit/s circuit
2 Mbit/s level
VC12 level
DXC
DXC
Subnetwork
Subnetwork
connection
VC12 level path
connection
VC4 level
Layer Adaptation
Layer Termination
VC4 level path

STM level
Layer Adaptation
Layer Termination
STM-1 section
transmission media
SDH architecture
14/
63

client connection
Layer Adaptation
Layer Adaptation
trail
AP
TCP
CP
CP
CP
TCP
CP
Maintenance)
SDH architecture
15/
63

NNI
NNI
NNI
NNI
Tributaries
Tributaries
Tributaries
MUX
sinc.
Media :
PDH
ATM
MUX
sinc.
CXC
DIGITAL CONNETION
fiber
wireless
MUX
sinc.
Media :
fiber
wireless
MUX
sinc.
ACCESS
PDH
ATM
MUX
sinc.
MUX
sinc.
Tributaries
SDH architecture
16/
63
Reference model
IP
Frame
RTB ISDN Relay
IP
ATM
ATM
Frame
Relay ISDN RTB
interchange unit
paths
sections
SDH frame
VC-12
low order VC-12
low order VC-12
high order VC-4
VC-4
high order VC-4
seccin
multiplexing
de multiplexin
section
MSOH
seccin
regeneration
de regeneracin
section
RSOH
physical interface
STM-1
physical interface
NNI
SDH architecture
17/
63
Section
Regenerators (REG)
STM-N
REG
STM-N
SDH architecture
19/
63
2M
8M
STM-1
L O -P T E
34M
H O -P T E
SDH
MUX
STM-N
45M
140M
Overhead management
SDH architecture
20/
63
STM-N
SDH
MUX
STM-M
M >N
STM-N

4 x STM-1 = STM4
4 x STM-4 = STM16
4 x STM-16 = STM64
SDH architecture
21/
63
West
East
STM-M
STM-M
STM-N, PDH
SDH architecture
22/
63
STM-N
STM-N
STM-N
STM-N
SDH architecture
23/
63
MUX
2M
34M
LPT
HPT
MUX
STM-1 SDH
MUX
REG
STM-N MUX
MUX STM-N
SDH STM-1
MUX
2M
HPT
LPT
34M
45M
45M
140M
140M
SDH architecture
24/
63
Ring topology
back up ring
ADM
ADM
ADM
tributary
active ring
tributary
ADM
SDH architecture
25/
63

E
A
B
C
Star PDH network
C
SDH Network
SDH architecture
26/
63
Transport design
National Backbone
STM-16
Primary Network
STM-4
Access Network
STM-1 or PDH
SDH architecture
27/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
28/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
29/
63

LTMUX
LO HO
MUX
REG
REG
SECT
DXC
REG
SECT
REG
REG
SECT
ADM
REG
SECT
LTMUX
HO LO
REG
REG
SECT
REG
SECT
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
30/
63
Original signal
Regenerated signal
REG
REG
ADM
attenuation
Regenerator
Multiplexer
noise
distortion
Regenerator
SDH architecture
31/
63
Transport Services
2 Mbit/s PSTN
2 Mbit/s
34 Mbit/s
34 Mbit/s
ADM
ADM
ADM
ADM
ADM
A
DM
STM-16
STM-1
DXC
STM-1
ADM
ADM
STM-1,4
STM-1
ADM
ADM
2 Mbit/s
34 Mbit/s
140 Mbit/s
C
irc
ui
t
ADM
ADM
Internet
STM-4
LTMUX
140 Mbit/s
ADM
ADM
ADM
ADM
155 Mbit/s
ISDN
LTMUX
ATM
ATM
2 Mbit/s
GSM
SDH architecture
32/
63
Security
Section
Security services
strategies:
diversification
restoration
protection
SDH architecture
34/
63
Diversification
route 1 (50% C1-C2)
C1
C2
D
route 2 (50% C1-C2)
SDH architecture
35/
63
Restoration
A
(5,2)
(4,2)
(7,0)
(6,0)
(4,5)
(3,4)
(7,7)
(5,2)
(11,3)

alternative route
SDH architecture
36/
63
Protection (i)
SDH path protection

SDH architecture
37/
63
MUX
1+1
MUX
high priority
service (S)
protection (P)
MUX
MUX
low priority
1:1
1:N
MUX
MUX
SDH architecture
38/
63

A circuit in bakup
B circuit
protection ring
service ring
B circuit
ADM
ADM
ADM
ADM
ADM
A circuit
ADM
A circuit
B circuit
A circuit in bakup
B circuit
SDH architecture
39/
63


protection services
service circuits
ADM
ADM
ADM
service circuits

protection services
SDH architecture
40/
63


circuito A
en back up
A circuit
ADM
ADM
ADM
ADM
AD
M
ADM
circuito A
circuito A
en back up
SDH architecture
41/
63

STM-1
AUG
VC-n
C-n
+ AU
+ HO POH
(pointer)
Mbit/s
140,
33 44 ,, 44 55
+ stuffing bits
+ overhead bits
TUG
TU-n
+ TU
VC-n
+LO POH
C-n
M
Mbbiitt//ss
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
Section

10 Gbit/s
STM-64
2,5 Gbit/s
STM-16
622 Mbit/s
STM-4
155 Mbit/s
x1
AUG16
x4
x1
AUG16
x4
x1
AUG4
x1
x1
x4
x1 AUG
STM-1
x1
AU416c
VC416c
AU44c
VC44c
AU-4
VC-4
x1
C416c
x1
C-44c
x1
C-4
ATM:149760 kbit/s
E4: 139264kbit/s
C-3
ATM:48384kbit/s
T3:44736kbit/s
E3: 34368 kbit/s
x3
SI)
( AN
51 Mbit/s
x1
STM-0
x1
TUG-3
x3
AU-3
TU-3
VC-3
(ANSI)
VC-3
x7
(AN
SI)
x7
x1
TUG-2
TU-2
VC-2
C-2
ATM:6874kbit/s
T2: 6312kbit/s
TU-12
VC-12
C-12
ATM:2144kbit/s
E1:2048kbit/s
TU-11
VC-11
C-11
ATM 1600 kbit/s

T1: 1544kbit/s
x3
Frame
Pointer processing
Aliingning
Multiplexing
POH addition
Tributary mapping
SI)
(AN
x4
Container
Group
43/
63
S T M -1
A U G
V C -n
C -n
+ AU
+ HO POH
(pointer)
M b i t /s
140,
34, 45
+ stuffing bits
+ overhead bits
TUG
T U -n
+ TU
(pointer)
V C -n
+L O P O H
C -n
Mbit/s
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
44/
63
Containers
autonomous
master clock
synchronized
master clock
synchronism
PDH frames
SDH container
mapping
stuffing
justification
bit oriented
2Mbit/s
MUX
8Mbit/s
mapping
stuffing
justification
byte oriented
MUX
155Mbit/s
2Mbit/s
45/
63
The container C-4

C-4
11
270
12
12
12
12
12
1 C-4 row
column 11
column 270
= CSSSSSOO
= I I I I I IJ S
: stuffing byte
I: Information bit
S: Stuffing bit
O: Overhead bit
46/
63

C -4 into a V C -4
10
1
11
270
J1
B3
C2
G1
F2
H4
F3
VC-4 Path
Overhead
(POH) is added
K3
9
N1
C4+POH=VC4
47/
63
1
STM-1
9 10
RSOH
10
270
VC-4
11
270
J1
B3
AUG
C2
G1
MSOH
F2
H4
F3
K3
POH
N1
48/
63

V=150 km/h
VC-4
155 km/h
STM-1
STM-1
VC-4
VC-4
VC-4
STM-1
49/
63

V<150 km/h
VC-4
VC-4
VC-4
VC-4
155 km/h
STM-1
STM-1
STM-1
between two frames
50/
63
The STM-1 frame
Regenerator
Section
Overhead
S T M -1
9 10
RSOH
10
270
VC-4
11
270
J1
Administrative
Unit Group
B3
C2
Multiplexer
Section
Overhead
G1
MSOH
F2
H4
F3
K3
POH
N1
51/
63

STM-1
1
270
9 10
RSOH
10
VC-4
11
270
J1
B3
C2
G1
MSOH
F2
H4
Z3
Z4
POH
Z5
Composition
2Mbit/s
34Mbit/s
140Mbit/s
1 VC4
3 VC3
21 VC12 + 2 VC3
21
42 VC12 + 1 VC3
42
63 VC12
63
52/
63
The STM-N frames

0
1
2
3
x4
0123
4
5
6
7
x4
4567
x4
8
9
A
B
x4
89AB
C
D
E
F
x4
CDEF
direct multiplexing
x16
0123456789ABCDEF
0123456789ABCDEF
Frame
Short Id.
STM-1
STM-4
155.520 x 4 = 622.080 kbit/s 622 Mbit/s
STM-16
622.080 x 4 = 2.488.320 kbit/s 2,5 Gbit/s
STM-64
2.488.320 x 4 = 9.953.280 kbit/s 10 Gbit/s
53/
63
J0 A2 A2 A2 A1 A1 A1
A1 A1
A1 A2
A2 A2 J0

125s

sinchronization
125s
54/
63
45Mbit/s
SDH
45 Mbit/s
Section

TUG-3
TU-3
VC-3
x3
34
+ TU
pointer
STM-1
+ SOH
AUG
+ AU
pointer
VC-n
C-3
+ LO POH
+ stuffing bits
+ overhead bits
+ HO POH

56/
63

1 1 1
25
1 1 1
25
Y I
1 1 1
Z I
25
I
Public Network
X = SSC I I I I I
Y = CCSSSSSS
I: Information bit
S: Stuffing bit
O: Overhead bit
Z = CCSSOOSJ
C-3
3
45Mbit/s
86
C-3
VC-3
57/
63
2Mbit/s
VC-3
2
1
(85 columnas)
86
J1
C-3
B3
C2
G1
F2
VC-3
H4
F3
K3
9
N1
C -3
TU-3

58/
63
VC-3
T U -3
2
H1
H2
H3
86
J1
x1
B3
C2
G1
TU-3
F2
H4
F3
Pointer bytes
K3
9
N1
V C -3
TUG-3
59/
63
TU-3
T U G -3
1
1
86
H1
H2
J1
H3
B3
x1
C2
TUG-3
G1
F2
R
H4
x3
F3
9
K3
N1
VC-4
60/
63
11
1
12
13
270
14
TUG-3
J1
B3
x3
C2
G1
F2 R
byte interleaving
3 TUG-3
VC-4
H4
F3
K3
9
( 3 x 86 = 258 columns )
N1
AU-4
stuffing bytes
61/
63
STM-1
9 10
RSOH
10
VC-4
11
VC-4
270
270
J1
B3
C2
G1
MSOH
AU-4
F2
H4
F3
K3
N1
POH
STM-1
62/
63
VC-4
9 10
STM-1
270
RSOH
AU-4
AUG
MSOH
STM-1
63/
63

PDH limitations

fourth hierarchy)


byte oriented

rest of the world


2Mbit/s with CRC4
2/
63

small companies.

definition

Advanced management

multimedia
3/
63
bytes vs. bits
frame 1
125 s
0
frame 2
125 s
1 byte
n 0
rate =
8 bits
12510-6seg.
= 64Kbit/s
4/
63
SDH objectives (i)
between equipments

speed tributaries

service

management

networks
fault tolerance
5/
63
6/
63
services
Internet
Frame Relay
RTB
ATM
GSM
transport network
SDH
transmission media
cable/fiber/radio
7/
63
SDH architecture
client
server
Section
inputs
Function of
outputs
connectivity
and overheads
SDH architecture
9/
63
SDH architecture
10/
63
network connection
Client layer
digitalization
codification
Server layer
add/drop
overheads
path

SDH architecture
11/
63
Reference points
Network connection
Layer Adaptation
Layer Adaptation
AP
AP
Layer Termination
Network connection
Layer Termination
Subnetwork
link
TCP
CP
CP
TCP
CP
CP
SDH architecture
12/
63
Connectivity
Client Path
Client layer
Server layer
AP
AP
Network Connection
Link Connection
Subnetwork
Connection
Subnetwork
Connection
TCP
TCP
CP
CP
CP
CP
Server Path
TCP
to multipoint
SDH architecture
13/
63
2 Mbit/s circuit
2 Mbit/s level
VC12 level
DXC
DXC
Subnetwork
Subnetwork
connection
VC12 level path
connection
VC4 level
Layer Adaptation
Layer Termination
VC4 level path

STM level
Layer Adaptation
Layer Termination
STM-1 section
transmission media
SDH architecture
14/
63

client connection
Layer Adaptation
Layer Adaptation
trail
AP
TCP
CP
CP
CP
TCP
CP
Maintenance)
SDH architecture
15/
63

NNI
NNI
NNI
NNI
Tributaries
Tributaries
Tributaries
MUX
sinc.
Media :
PDH
ATM
MUX
sinc.
CXC
DIGITAL CONNETION
fiber
wireless
MUX
sinc.
Media :
fiber
wireless
MUX
sinc.
ACCESS
PDH
ATM
MUX
sinc.
MUX
sinc.
Tributaries
SDH architecture
16/
63
Reference model
IP
Frame
RTB ISDN Relay
IP
ATM
ATM
Frame
Relay ISDN RTB
interchange unit
paths
sections
SDH frame
VC-12
low order VC-12
low order VC-12
high order VC-4
VC-4
high order VC-4
seccin
multiplexing
de multiplexin
section
MSOH
seccin
regeneration
de regeneracin
section
RSOH
physical interface
STM-1
physical interface
NNI
SDH architecture
17/
63
Section
Regenerators (REG)
STM-N
REG
STM-N
SDH architecture
19/
63
2M
8M
STM-1
L O -P T E
34M
H O -P T E
SDH
MUX
STM-N
45M
140M
Overhead management
SDH architecture
20/
63
STM-N
SDH
MUX
STM-M
M >N
STM-N

4 x STM-1 = STM4
4 x STM-4 = STM16
4 x STM-16 = STM64
SDH architecture
21/
63
West
East
STM-M
STM-M
STM-N, PDH
SDH architecture
22/
63
STM-N
STM-N
STM-N
STM-N
SDH architecture
23/
63
MUX
2M
34M
LPT
HPT
MUX
STM-1 SDH
MUX
REG
STM-N MUX
MUX STM-N
SDH STM-1
MUX
2M
HPT
LPT
34M
45M
45M
140M
140M
SDH architecture
24/
63
Ring topology
back up ring
ADM
ADM
ADM
tributary
active ring
tributary
ADM
SDH architecture
25/
63

E
A
B
C
Star PDH network
C
SDH Network
SDH architecture
26/
63
Transport design
National Backbone
STM-16
Primary Network
STM-4
Access Network
STM-1 or PDH
SDH architecture
27/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
28/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
29/
63

LTMUX
LO HO
MUX
REG
REG
SECT
DXC
REG
SECT
REG
REG
SECT
ADM
REG
SECT
LTMUX
HO LO
REG
REG
SECT
REG
SECT
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
30/
63
Original signal
Regenerated signal
REG
REG
ADM
attenuation
Regenerator
Multiplexer
noise
distortion
Regenerator
SDH architecture
31/
63
Transport Services
2 Mbit/s PSTN
2 Mbit/s
34 Mbit/s
34 Mbit/s
ADM
ADM
ADM
ADM
ADM
A
DM
STM-16
STM-1
DXC
STM-1
ADM
ADM
STM-1,4
STM-1
ADM
ADM
2 Mbit/s
34 Mbit/s
140 Mbit/s
C
irc
ui
t
ADM
ADM
Internet
STM-4
LTMUX
140 Mbit/s
ADM
ADM
ADM
ADM
155 Mbit/s
ISDN
LTMUX
ATM
ATM
2 Mbit/s
GSM
SDH architecture
32/
63
Security
Section
Security services
strategies:
diversification
restoration
protection
SDH architecture
34/
63
Diversification
route 1 (50% C1-C2)
C1
C2
D
route 2 (50% C1-C2)
SDH architecture
35/
63
Restoration
A
(5,2)
(4,2)
(7,0)
(6,0)
(4,5)
(3,4)
(7,7)
(5,2)
(11,3)

alternative route
SDH architecture
36/
63
Protection (i)
SDH path protection

SDH architecture
37/
63
MUX
1+1
MUX
high priority
service (S)
protection (P)
MUX
MUX
low priority
1:1
1:N
MUX
MUX
SDH architecture
38/
63

A circuit in bakup
B circuit
protection ring
service ring
B circuit
ADM
ADM
ADM
ADM
ADM
A circuit
ADM
A circuit
B circuit
A circuit in bakup
B circuit
SDH architecture
39/
63


protection services
service circuits
ADM
ADM
ADM
service circuits

protection services
SDH architecture
40/
63


circuito A
en back up
A circuit
ADM
ADM
ADM
ADM
AD
M
ADM
circuito A
circuito A
en back up
SDH architecture
41/
63

STM-1
AUG
VC-n
C-n
+ AU
+ HO POH
(pointer)
Mbit/s
140,
33 44 ,, 44 55
+ stuffing bits
+ overhead bits
TUG
TU-n
+ TU
VC-n
+LO POH
C-n
M
Mbbiitt//ss
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
Section

10 Gbit/s
STM-64
2,5 Gbit/s
STM-16
622 Mbit/s
STM-4
155 Mbit/s
x1
AUG16
x4
x1
AUG16
x4
x1
AUG4
x1
x1
x4
x1 AUG
STM-1
x1
AU416c
VC416c
AU44c
VC44c
AU-4
VC-4
x1
C416c
x1
C-44c
x1
C-4
ATM:149760 kbit/s
E4: 139264kbit/s
C-3
ATM:48384kbit/s
T3:44736kbit/s
E3: 34368 kbit/s
x3
SI)
( AN
51 Mbit/s
x1
STM-0
x1
TUG-3
x3
AU-3
TU-3
VC-3
(ANSI)
VC-3
x7
(AN
SI)
x7
x1
TUG-2
TU-2
VC-2
C-2
ATM:6874kbit/s
T2: 6312kbit/s
TU-12
VC-12
C-12
ATM:2144kbit/s
E1:2048kbit/s
TU-11
VC-11
C-11
ATM 1600 kbit/s

T1: 1544kbit/s
x3
Frame
Pointer processing
Aliingning
Multiplexing
POH addition
Tributary mapping
SI)
(AN
x4
Container
Group
43/
63
S T M -1
A U G
V C -n
C -n
+ AU
+ HO POH
(pointer)
M b i t /s
140,
34, 45
+ stuffing bits
+ overhead bits
TUG
T U -n
+ TU
(pointer)
V C -n
+L O P O H
C -n
Mbit/s
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
44/
63
Containers
autonomous
master clock
synchronized
master clock
synchronism
PDH frames
SDH container
mapping
stuffing
justification
bit oriented
2Mbit/s
MUX
8Mbit/s
mapping
stuffing
justification
byte oriented
MUX
155Mbit/s
2Mbit/s
45/
63
The container C-4

C-4
11
270
12
12
12
12
12
1 C-4 row
column 11
column 270
= CSSSSSOO
= I I I I I IJ S
: stuffing byte
I: Information bit
S: Stuffing bit
O: Overhead bit
46/
63

C -4 into a V C -4
10
1
11
270
J1
B3
C2
G1
F2
H4
F3
VC-4 Path
Overhead
(POH) is added
K3
9
N1
C4+POH=VC4
47/
63
1
STM-1
9 10
RSOH
10
270
VC-4
11
270
J1
B3
AUG
C2
G1
MSOH
F2
H4
F3
K3
POH
N1
48/
63

V=150 km/h
VC-4
155 km/h
STM-1
STM-1
VC-4
VC-4
VC-4
STM-1
49/
63

V<150 km/h
VC-4
VC-4
VC-4
VC-4
155 km/h
STM-1
STM-1
STM-1
between two frames
50/
63
The STM-1 frame
Regenerator
Section
Overhead
S T M -1
9 10
RSOH
10
270
VC-4
11
270
J1
Administrative
Unit Group
B3
C2
Multiplexer
Section
Overhead
G1
MSOH
F2
H4
F3
K3
POH
N1
51/
63

STM-1
1
270
9 10
RSOH
10
VC-4
11
270
J1
B3
C2
G1
MSOH
F2
H4
Z3
Z4
POH
Z5
Composition
2Mbit/s
34Mbit/s
140Mbit/s
1 VC4
3 VC3
21 VC12 + 2 VC3
21
42 VC12 + 1 VC3
42
63 VC12
63
52/
63
The STM-N frames

0
1
2
3
x4
0123
4
5
6
7
x4
4567
x4
8
9
A
B
x4
89AB
C
D
E
F
x4
CDEF
direct multiplexing
x16
0123456789ABCDEF
0123456789ABCDEF
Frame
Short Id.
STM-1
STM-4
155.520 x 4 = 622.080 kbit/s 622 Mbit/s
STM-16
622.080 x 4 = 2.488.320 kbit/s 2,5 Gbit/s
STM-64
2.488.320 x 4 = 9.953.280 kbit/s 10 Gbit/s
53/
63
J0 A2 A2 A2 A1 A1 A1
A1 A1
A1 A2
A2 A2 J0

125s

sinchronization
125s
54/
63
45Mbit/s
SDH
45 Mbit/s
Section

TUG-3
TU-3
VC-3
x3
34
+ TU
pointer
STM-1
+ SOH
AUG
+ AU
pointer
VC-n
C-3
+ LO POH
+ stuffing bits
+ overhead bits
+ HO POH

56/
63

1 1 1
25
1 1 1
25
Y I
1 1 1
Z I
25
I
Public Network
X = SSC I I I I I
Y = CCSSSSSS
I: Information bit
S: Stuffing bit
O: Overhead bit
Z = CCSSOOSJ
C-3
3
45Mbit/s
86
C-3
VC-3
57/
63
2Mbit/s
VC-3
2
1
(85 columnas)
86
J1
C-3
B3
C2
G1
F2
VC-3
H4
F3
K3
9
N1
C -3
TU-3

58/
63
VC-3
T U -3
2
H1
H2
H3
86
J1
x1
B3
C2
G1
TU-3
F2
H4
F3
Pointer bytes
K3
9
N1
V C -3
TUG-3
59/
63
TU-3
T U G -3
1
1
86
H1
H2
J1
H3
B3
x1
C2
TUG-3
G1
F2
R
H4
x3
F3
9
K3
N1
VC-4
60/
63
11
1
12
13
270
14
TUG-3
J1
B3
x3
C2
G1
F2 R
byte interleaving
3 TUG-3
VC-4
H4
F3
K3
9
( 3 x 86 = 258 columns )
N1
AU-4
stuffing bytes
61/
63
STM-1
9 10
RSOH
10
VC-4
11
VC-4
270
270
J1
B3
C2
G1
MSOH
AU-4
F2
H4
F3
K3
N1
POH
STM-1
62/
63
VC-4
9 10
STM-1
270
RSOH
AU-4
AUG
MSOH
STM-1
63/
63

PDH limitations

fourth hierarchy)


byte oriented

rest of the world


2Mbit/s with CRC4
2/
63

small companies.

definition

Advanced management

multimedia
3/
63
bytes vs. bits
frame 1
125 s
0
frame 2
125 s
1 byte
n 0
rate =
8 bits
12510-6seg.
= 64Kbit/s
4/
63
SDH objectives (i)
between equipments

speed tributaries

service

management

networks
fault tolerance
5/
63
6/
63
services
Internet
Frame Relay
RTB
ATM
GSM
transport network
SDH
transmission media
cable/fiber/radio
7/
63
SDH architecture
client
server
Section
inputs
Function of
outputs
connectivity
and overheads
SDH architecture
9/
63
SDH architecture
10/
63
network connection
Client layer
digitalization
codification
Server layer
add/drop
overheads
path

SDH architecture
11/
63
Reference points
Network connection
Layer Adaptation
Layer Adaptation
AP
AP
Layer Termination
Network connection
Layer Termination
Subnetwork
link
TCP
CP
CP
TCP
CP
CP
SDH architecture
12/
63
Connectivity
Client Path
Client layer
Server layer
AP
AP
Network Connection
Link Connection
Subnetwork
Connection
Subnetwork
Connection
TCP
TCP
CP
CP
CP
CP
Server Path
TCP
to multipoint
SDH architecture
13/
63
2 Mbit/s circuit
2 Mbit/s level
VC12 level
DXC
DXC
Subnetwork
Subnetwork
connection
VC12 level path
connection
VC4 level
Layer Adaptation
Layer Termination
VC4 level path

STM level
Layer Adaptation
Layer Termination
STM-1 section
transmission media
SDH architecture
14/
63

client connection
Layer Adaptation
Layer Adaptation
trail
AP
TCP
CP
CP
CP
TCP
CP
Maintenance)
SDH architecture
15/
63

NNI
NNI
NNI
NNI
Tributaries
Tributaries
Tributaries
MUX
sinc.
Media :
PDH
ATM
MUX
sinc.
CXC
DIGITAL CONNETION
fiber
wireless
MUX
sinc.
Media :
fiber
wireless
MUX
sinc.
ACCESS
PDH
ATM
MUX
sinc.
MUX
sinc.
Tributaries
SDH architecture
16/
63
Reference model
IP
Frame
RTB ISDN Relay
IP
ATM
ATM
Frame
Relay ISDN RTB
interchange unit
paths
sections
SDH frame
VC-12
low order VC-12
low order VC-12
high order VC-4
VC-4
high order VC-4
seccin
multiplexing
de multiplexin
section
MSOH
seccin
regeneration
de regeneracin
section
RSOH
physical interface
STM-1
physical interface
NNI
SDH architecture
17/
63
Section
Regenerators (REG)
STM-N
REG
STM-N
SDH architecture
19/
63
2M
8M
STM-1
L O -P T E
34M
H O -P T E
SDH
MUX
STM-N
45M
140M
Overhead management
SDH architecture
20/
63
STM-N
SDH
MUX
STM-M
M >N
STM-N

4 x STM-1 = STM4
4 x STM-4 = STM16
4 x STM-16 = STM64
SDH architecture
21/
63
West
East
STM-M
STM-M
STM-N, PDH
SDH architecture
22/
63
STM-N
STM-N
STM-N
STM-N
SDH architecture
23/
63
MUX
2M
34M
LPT
HPT
MUX
STM-1 SDH
MUX
REG
STM-N MUX
MUX STM-N
SDH STM-1
MUX
2M
HPT
LPT
34M
45M
45M
140M
140M
SDH architecture
24/
63
Ring topology
back up ring
ADM
ADM
ADM
tributary
active ring
tributary
ADM
SDH architecture
25/
63

E
A
B
C
Star PDH network
C
SDH Network
SDH architecture
26/
63
Transport design
National Backbone
STM-16
Primary Network
STM-4
Access Network
STM-1 or PDH
SDH architecture
27/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
28/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
29/
63

LTMUX
LO HO
MUX
REG
REG
SECT
DXC
REG
SECT
REG
REG
SECT
ADM
REG
SECT
LTMUX
HO LO
REG
REG
SECT
REG
SECT
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
30/
63
Original signal
Regenerated signal
REG
REG
ADM
attenuation
Regenerator
Multiplexer
noise
distortion
Regenerator
SDH architecture
31/
63
Transport Services
2 Mbit/s PSTN
2 Mbit/s
34 Mbit/s
34 Mbit/s
ADM
ADM
ADM
ADM
ADM
A
DM
STM-16
STM-1
DXC
STM-1
ADM
ADM
STM-1,4
STM-1
ADM
ADM
2 Mbit/s
34 Mbit/s
140 Mbit/s
C
irc
ui
t
ADM
ADM
Internet
STM-4
LTMUX
140 Mbit/s
ADM
ADM
ADM
ADM
155 Mbit/s
ISDN
LTMUX
ATM
ATM
2 Mbit/s
GSM
SDH architecture
32/
63
Security
Section
Security services
strategies:
diversification
restoration
protection
SDH architecture
34/
63
Diversification
route 1 (50% C1-C2)
C1
C2
D
route 2 (50% C1-C2)
SDH architecture
35/
63
Restoration
A
(5,2)
(4,2)
(7,0)
(6,0)
(4,5)
(3,4)
(7,7)
(5,2)
(11,3)

alternative route
SDH architecture
36/
63
Protection (i)
SDH path protection

SDH architecture
37/
63
MUX
1+1
MUX
high priority
service (S)
protection (P)
MUX
MUX
low priority
1:1
1:N
MUX
MUX
SDH architecture
38/
63

A circuit in bakup
B circuit
protection ring
service ring
B circuit
ADM
ADM
ADM
ADM
ADM
A circuit
ADM
A circuit
B circuit
A circuit in bakup
B circuit
SDH architecture
39/
63


protection services
service circuits
ADM
ADM
ADM
service circuits

protection services
SDH architecture
40/
63


circuito A
en back up
A circuit
ADM
ADM
ADM
ADM
AD
M
ADM
circuito A
circuito A
en back up
SDH architecture
41/
63

STM-1
AUG
VC-n
C-n
+ AU
+ HO POH
(pointer)
Mbit/s
140,
33 44 ,, 44 55
+ stuffing bits
+ overhead bits
TUG
TU-n
+ TU
VC-n
+LO POH
C-n
M
Mbbiitt//ss
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
Section

10 Gbit/s
STM-64
2,5 Gbit/s
STM-16
622 Mbit/s
STM-4
155 Mbit/s
x1
AUG16
x4
x1
AUG16
x4
x1
AUG4
x1
x1
x4
x1 AUG
STM-1
x1
AU416c
VC416c
AU44c
VC44c
AU-4
VC-4
x1
C416c
x1
C-44c
x1
C-4
ATM:149760 kbit/s
E4: 139264kbit/s
C-3
ATM:48384kbit/s
T3:44736kbit/s
E3: 34368 kbit/s
x3
SI)
( AN
51 Mbit/s
x1
STM-0
x1
TUG-3
x3
AU-3
TU-3
VC-3
(ANSI)
VC-3
x7
(AN
SI)
x7
x1
TUG-2
TU-2
VC-2
C-2
ATM:6874kbit/s
T2: 6312kbit/s
TU-12
VC-12
C-12
ATM:2144kbit/s
E1:2048kbit/s
TU-11
VC-11
C-11
ATM 1600 kbit/s

T1: 1544kbit/s
x3
Frame
Pointer processing
Aliingning
Multiplexing
POH addition
Tributary mapping
SI)
(AN
x4
Container
Group
43/
63
S T M -1
A U G
V C -n
C -n
+ AU
+ HO POH
(pointer)
M b i t /s
140,
34, 45
+ stuffing bits
+ overhead bits
TUG
T U -n
+ TU
(pointer)
V C -n
+L O P O H
C -n
Mbit/s
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
44/
63
Containers
autonomous
master clock
synchronized
master clock
synchronism
PDH frames
SDH container
mapping
stuffing
justification
bit oriented
2Mbit/s
MUX
8Mbit/s
mapping
stuffing
justification
byte oriented
MUX
155Mbit/s
2Mbit/s
45/
63
The container C-4

C-4
11
270
12
12
12
12
12
1 C-4 row
column 11
column 270
= CSSSSSOO
= I I I I I IJ S
: stuffing byte
I: Information bit
S: Stuffing bit
O: Overhead bit
46/
63

C -4 into a V C -4
10
1
11
270
J1
B3
C2
G1
F2
H4
F3
VC-4 Path
Overhead
(POH) is added
K3
9
N1
C4+POH=VC4
47/
63
1
STM-1
9 10
RSOH
10
270
VC-4
11
270
J1
B3
AUG
C2
G1
MSOH
F2
H4
F3
K3
POH
N1
48/
63

V=150 km/h
VC-4
155 km/h
STM-1
STM-1
VC-4
VC-4
VC-4
STM-1
49/
63

V<150 km/h
VC-4
VC-4
VC-4
VC-4
155 km/h
STM-1
STM-1
STM-1
between two frames
50/
63
The STM-1 frame
Regenerator
Section
Overhead
S T M -1
9 10
RSOH
10
270
VC-4
11
270
J1
Administrative
Unit Group
B3
C2
Multiplexer
Section
Overhead
G1
MSOH
F2
H4
F3
K3
POH
N1
51/
63

STM-1
1
270
9 10
RSOH
10
VC-4
11
270
J1
B3
C2
G1
MSOH
F2
H4
Z3
Z4
POH
Z5
Composition
2Mbit/s
34Mbit/s
140Mbit/s
1 VC4
3 VC3
21 VC12 + 2 VC3
21
42 VC12 + 1 VC3
42
63 VC12
63
52/
63
The STM-N frames

0
1
2
3
x4
0123
4
5
6
7
x4
4567
x4
8
9
A
B
x4
89AB
C
D
E
F
x4
CDEF
direct multiplexing
x16
0123456789ABCDEF
0123456789ABCDEF
Frame
Short Id.
STM-1
STM-4
155.520 x 4 = 622.080 kbit/s 622 Mbit/s
STM-16
622.080 x 4 = 2.488.320 kbit/s 2,5 Gbit/s
STM-64
2.488.320 x 4 = 9.953.280 kbit/s 10 Gbit/s
53/
63
J0 A2 A2 A2 A1 A1 A1
A1 A1
A1 A2
A2 A2 J0

125s

sinchronization
125s
54/
63
45Mbit/s
SDH
45 Mbit/s
Section

TUG-3
TU-3
VC-3
x3
34
+ TU
pointer
STM-1
+ SOH
AUG
+ AU
pointer
VC-n
C-3
+ LO POH
+ stuffing bits
+ overhead bits
+ HO POH

56/
63

1 1 1
25
1 1 1
25
Y I
1 1 1
Z I
25
I
Public Network
X = SSC I I I I I
Y = CCSSSSSS
I: Information bit
S: Stuffing bit
O: Overhead bit
Z = CCSSOOSJ
C-3
3
45Mbit/s
86
C-3
VC-3
57/
63
2Mbit/s
VC-3
2
1
(85 columnas)
86
J1
C-3
B3
C2
G1
F2
VC-3
H4
F3
K3
9
N1
C -3
TU-3

58/
63
VC-3
T U -3
2
H1
H2
H3
86
J1
x1
B3
C2
G1
TU-3
F2
H4
F3
Pointer bytes
K3
9
N1
V C -3
TUG-3
59/
63
TU-3
T U G -3
1
1
86
H1
H2
J1
H3
B3
x1
C2
TUG-3
G1
F2
R
H4
x3
F3
9
K3
N1
VC-4
60/
63
11
1
12
13
270
14
TUG-3
J1
B3
x3
C2
G1
F2 R
byte interleaving
3 TUG-3
VC-4
H4
F3
K3
9
( 3 x 86 = 258 columns )
N1
AU-4
stuffing bytes
61/
63
STM-1
9 10
RSOH
10
VC-4
11
VC-4
270
270
J1
B3
C2
G1
MSOH
AU-4
F2
H4
F3
K3
N1
POH
STM-1
62/
63
VC-4
9 10
STM-1
270
RSOH
AU-4
AUG
MSOH
STM-1
63/
63

PDH limitations

fourth hierarchy)


byte oriented

rest of the world


2Mbit/s with CRC4
2/
63

small companies.

definition

Advanced management

multimedia
3/
63
bytes vs. bits
frame 1
125 s
0
frame 2
125 s
1 byte
n 0
rate =
8 bits
12510-6seg.
= 64Kbit/s
STM-N is the name for the transport frames. They have always a period of 125 s
4/
63
SDH objectives (i)
between equipments

speed tributaries

service

management

networks
fault tolerance
5/
63
6/
63
services
Internet
Frame Relay
RTB
ATM
GSM
transport network
SDH
transmission media
cable/fiber/radio
7/
63
SDH architecture
client
server
Section
inputs
Function of
outputs
connectivity
and overheads
SDH architecture
9/
63
SDH architecture
10/
63
network connection
Client layer
digitalization
codification
Server layer
add/drop
overheads
path

SDH architecture
11/
63
Reference points
Network connection
Layer Adaptation
Layer Adaptation
AP
AP
Layer Termination
Network connection
Layer Termination
Subnetwork
link
TCP
CP
CP
TCP
CP
CP
SDH architecture
12/
63
Connectivity
Client Path
Client layer
Server layer
AP
AP
Network Connection
Link Connection
Subnetwork
Connection
Subnetwork
Connection
TCP
TCP
CP
CP
CP
CP
Server Path
TCP
to multipoint
SDH architecture
13/
63
2 Mbit/s circuit
2 Mbit/s level
VC12 level
DXC
DXC
Subnetwork
Subnetwork
connection
VC12 level path
connection
VC4 level
Layer Adaptation
Layer Termination
VC4 level path

STM level
Layer Adaptation
Layer Termination
STM-1 section
transmission media
SDH architecture
14/
63

client connection
Layer Adaptation
Layer Adaptation
trail
AP
TCP
CP
CP
CP
TCP
CP
Maintenance)
SDH architecture
15/
63

NNI
NNI
NNI
NNI
Tributaries
Tributaries
Tributaries
MUX
sinc.
Media :
PDH
ATM
MUX
sinc.
CXC
DIGITAL CONNETION
fiber
wireless
MUX
sinc.
Media :
fiber
wireless
MUX
sinc.
ACCESS
PDH
ATM
MUX
sinc.
MUX
sinc.
Tributaries
SDH architecture
16/
63
Reference model
IP
Frame
RTB ISDN Relay
IP
ATM
ATM
Frame
Relay ISDN RTB
interchange unit
paths
sections
SDH frame
VC-12
low order VC-12
low order VC-12
high order VC-4
VC-4
high order VC-4
seccin
multiplexing
de multiplexin
section
MSOH
seccin
regeneration
de regeneracin
section
RSOH
physical interface
STM-1
physical interface
NNI
SDH architecture
17/
63
Section
Regenerators (REG)
STM-N
REG
STM-N
SDH architecture
19/
63
2M
8M
STM-1
L O -P T E
34M
H O -P T E
SDH
MUX
STM-N
45M
140M
Overhead management
SDH architecture
20/
63
STM-N
SDH
MUX
STM-M
M >N
STM-N

4 x STM-1 = STM4
4 x STM-4 = STM16
4 x STM-16 = STM64
SDH architecture
21/
63
West
East
STM-M
STM-M
STM-N, PDH
SDH architecture
22/
63
STM-N
STM-N
STM-N
STM-N
SDH architecture
23/
63
MUX
2M
34M
LPT
HPT
MUX
STM-1 SDH
MUX
REG
STM-N MUX
MUX STM-N
SDH STM-1
MUX
2M
HPT
LPT
34M
45M
45M
140M
140M
SDH architecture
24/
63
Ring topology
back up ring
ADM
ADM
ADM
tributary
active ring
tributary
ADM
SDH architecture
25/
63

E
A
B
C
Star PDH network
C
SDH Network
SDH architecture
26/
63
Transport design
National Backbone
STM-16
Primary Network
STM-4
Access Network
STM-1 or PDH
SDH architecture
27/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
28/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
29/
63

LTMUX
LO HO
MUX
REG
REG
SECT
DXC
REG
SECT
REG
REG
SECT
ADM
REG
SECT
LTMUX
HO LO
REG
REG
SECT
REG
SECT
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
30/
63
Original signal
Regenerated signal
REG
REG
ADM
attenuation
Regenerator
Multiplexer
noise
distortion
Regenerator
SDH architecture
31/
63
Transport Services
2 Mbit/s PSTN
2 Mbit/s
34 Mbit/s
34 Mbit/s
ADM
ADM
ADM
ADM
ADM
A
DM
STM-16
STM-1
DXC
STM-1
ADM
ADM
STM-1,4
STM-1
ADM
ADM
2 Mbit/s
34 Mbit/s
140 Mbit/s
C
irc
ui
t
ADM
ADM
Internet
STM-4
LTMUX
140 Mbit/s
ADM
ADM
ADM
ADM
155 Mbit/s
ISDN
LTMUX
ATM
ATM
2 Mbit/s
GSM
SDH architecture
32/
63
Security
Section
Security services
strategies:
diversification
restoration
protection
SDH architecture
34/
63
Diversification
route 1 (50% C1-C2)
C1
C2
D
route 2 (50% C1-C2)
SDH architecture
35/
63
Restoration
A
(5,2)
(4,2)
(7,0)
(6,0)
(4,5)
(3,4)
(7,7)
(5,2)
(11,3)

alternative route
SDH architecture
36/
63
Protection (i)
SDH path protection

SDH architecture
37/
63
MUX
1+1
MUX
high priority
service (S)
protection (P)
MUX
MUX
low priority
1:1
1:N
MUX
MUX
SDH architecture
38/
63

A circuit in bakup
B circuit
protection ring
service ring
B circuit
ADM
ADM
ADM
ADM
ADM
A circuit
ADM
A circuit
B circuit
A circuit in bakup
B circuit
SDH architecture
39/
63


protection services
service circuits
ADM
ADM
ADM
service circuits

protection services
SDH architecture
40/
63


circuito A
en back up
A circuit
ADM
ADM
ADM
ADM
AD
M
ADM
circuito A
circuito A
en back up
SDH architecture
41/
63

STM-1
AUG
VC-n
C-n
+ AU
+ HO POH
(pointer)
Mbit/s
140,
33 44 ,, 44 55
+ stuffing bits
+ overhead bits
TUG
TU-n
+ TU
VC-n
+LO POH
C-n
M
Mbbiitt//ss
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
Section

10 Gbit/s
STM-64
2,5 Gbit/s
STM-16
622 Mbit/s
STM-4
155 Mbit/s
x1
AUG16
x4
x1
AUG16
x4
x1
AUG4
x1
x1
x4
x1 AUG
STM-1
x1
AU416c
VC416c
AU44c
VC44c
AU-4
VC-4
x1
C416c
x1
C-44c
x1
C-4
ATM:149760 kbit/s
E4: 139264kbit/s
C-3
ATM:48384kbit/s
T3:44736kbit/s
E3: 34368 kbit/s
x3
SI)
( AN
51 Mbit/s
x1
STM-0
x1
TUG-3
x3
AU-3
TU-3
VC-3
(ANSI)
VC-3
x7
(AN
SI)
x7
x1
TUG-2
TU-2
VC-2
C-2
ATM:6874kbit/s
T2: 6312kbit/s
TU-12
VC-12
C-12
ATM:2144kbit/s
E1:2048kbit/s
TU-11
VC-11
C-11
ATM 1600 kbit/s

T1: 1544kbit/s
x3
Frame
Pointer processing
Aliingning
Multiplexing
POH addition
Tributary mapping
SI)
(AN
x4
Container
Group
43/
63
S T M -1
A U G
V C -n
C -n
+ AU
+ HO POH
(pointer)
M b i t /s
140,
34, 45
+ stuffing bits
+ overhead bits
TUG
T U -n
+ TU
(pointer)
V C -n
+L O P O H
C -n
Mbit/s
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
44/
63
Containers
autonomous
master clock
synchronized
master clock
synchronism
PDH frames
SDH container
mapping
stuffing
justification
bit oriented
2Mbit/s
MUX
8Mbit/s
mapping
stuffing
justification
byte oriented
MUX
155Mbit/s
2Mbit/s
45/
63
The container C-4

C-4
11
270
12
12
12
12
12
1 C-4 row
column 11
column 270
= CSSSSSOO
= I I I I I IJ S
: stuffing byte
I: Information bit
S: Stuffing bit
O: Overhead bit
46/
63

C -4 into a V C -4
10
1
11
270
J1
B3
C2
G1
F2
H4
F3
VC-4 Path
Overhead
(POH) is added
K3
9
N1
C4+POH=VC4
47/
63
1
STM-1
9 10
RSOH
10
270
VC-4
11
270
J1
B3
AUG
C2
G1
MSOH
F2
H4
F3
K3
POH
N1
48/
63

V=150 km/h
VC-4
155 km/h
STM-1
STM-1
VC-4
VC-4
VC-4
STM-1
49/
63

V<150 km/h
VC-4
VC-4
VC-4
VC-4
155 km/h
STM-1
STM-1
STM-1
between two frames
50/
63
The STM-1 frame
Regenerator
Section
Overhead
S T M -1
9 10
RSOH
10
270
VC-4
11
270
J1
Administrative
Unit Group
B3
C2
Multiplexer
Section
Overhead
G1
MSOH
F2
H4
F3
K3
POH
N1
51/
63

STM-1
1
270
9 10
RSOH
10
VC-4
11
270
J1
B3
C2
G1
MSOH
F2
H4
Z3
Z4
POH
Z5
Composition
2Mbit/s
34Mbit/s
140Mbit/s
1 VC4
3 VC3
21 VC12 + 2 VC3
21
42 VC12 + 1 VC3
42
63 VC12
63
52/
63
The STM-N frames

0
1
2
3
x4
0123
4
5
6
7
x4
4567
x4
8
9
A
B
x4
89AB
C
D
E
F
x4
CDEF
direct multiplexing
x16
0123456789ABCDEF
0123456789ABCDEF
Frame
Short Id.
STM-1
STM-4
155.520 x 4 = 622.080 kbit/s 622 Mbit/s
STM-16
622.080 x 4 = 2.488.320 kbit/s 2,5 Gbit/s
STM-64
2.488.320 x 4 = 9.953.280 kbit/s 10 Gbit/s
53/
63
J0 A2 A2 A2 A1 A1 A1
A1 A1
A1 A2
A2 A2 J0

125s

sinchronization
125s
54/
63
45Mbit/s
SDH
45 Mbit/s
Section

TUG-3
TU-3
VC-3
x3
34
+ TU
pointer
STM-1
+ SOH
AUG
+ AU
pointer
VC-n
C-3
+ LO POH
+ stuffing bits
+ overhead bits
+ HO POH

56/
63

1 1 1
25
1 1 1
25
Y I
1 1 1
Z I
25
I
Public Network
X = SSC I I I I I
Y = CCSSSSSS
I: Information bit
S: Stuffing bit
O: Overhead bit
Z = CCSSOOSJ
C-3
3
45Mbit/s
86
C-3
VC-3
57/
63
2Mbit/s
VC-3
2
1
(85 columnas)
86
J1
C-3
B3
C2
G1
F2
VC-3
H4
F3
K3
9
N1
C -3
TU-3

58/
63
VC-3
T U -3
2
H1
H2
H3
86
J1
x1
B3
C2
G1
TU-3
F2
H4
F3
Pointer bytes
K3
9
N1
V C -3
TUG-3
59/
63
TU-3
T U G -3
1
1
86
H1
H2
J1
H3
B3
x1
C2
TUG-3
G1
F2
R
H4
x3
F3
9
K3
N1
VC-4
60/
63
11
1
12
13
270
14
TUG-3
J1
B3
x3
C2
G1
F2 R
byte interleaving
3 TUG-3
VC-4
H4
F3
K3
9
( 3 x 86 = 258 columns )
N1
AU-4
stuffing bytes
61/
63
STM-1
9 10
RSOH
10
VC-4
11
VC-4
270
270
J1
B3
C2
G1
MSOH
AU-4
F2
H4
F3
K3
N1
POH
STM-1
62/
63
VC-4
9 10
STM-1
270
RSOH
AU-4
AUG
MSOH
STM-1
63/
63

PDH limitations

fourth hierarchy)


byte oriented

rest of the world


2Mbit/s with CRC4
2/
63

small companies.

definition

Advanced management

multimedia
3/
63
bytes vs. bits
frame 1
125 s
0
frame 2
125 s
1 byte
n 0
rate =
8 bits
12510-6seg.
= 64Kbit/s
4/
63
SDH objectives (i)
between equipments

speed tributaries

service

management

networks
fault tolerance
5/
63
6/
63
services
Internet
Frame Relay
RTB
ATM
GSM
transport network
SDH
transmission media
cable/fiber/radio
7/
63
SDH architecture
client
server
Section
inputs
Function of
outputs
connectivity
and overheads
SDH architecture
9/
63
SDH architecture
10/
63
network connection
Client layer
digitalization
codification
Server layer
add/drop
overheads
path

SDH architecture
11/
63
Reference points
Network connection
Layer Adaptation
Layer Adaptation
AP
AP
Layer Termination
Network connection
Layer Termination
Subnetwork
link
TCP
CP
CP
TCP
CP
CP
SDH architecture
12/
63
Connectivity
Client Path
Client layer
Server layer
AP
AP
Network Connection
Link Connection
Subnetwork
Connection
Subnetwork
Connection
TCP
TCP
CP
CP
CP
CP
Server Path
TCP
to multipoint
SDH architecture
13/
63
2 Mbit/s circuit
2 Mbit/s level
VC12 level
DXC
DXC
Subnetwork
Subnetwork
connection
VC12 level path
connection
VC4 level
Layer Adaptation
Layer Termination
VC4 level path

STM level
Layer Adaptation
Layer Termination
STM-1 section
transmission media
SDH architecture
14/
63

client connection
Layer Adaptation
Layer Adaptation
trail
AP
TCP
CP
CP
CP
TCP
CP
Maintenance)
SDH architecture
15/
63

NNI
NNI
NNI
NNI
Tributaries
Tributaries
Tributaries
MUX
sinc.
Media :
PDH
ATM
MUX
sinc.
CXC
DIGITAL CONNETION
fiber
wireless
MUX
sinc.
Media :
fiber
wireless
MUX
sinc.
ACCESS
PDH
ATM
MUX
sinc.
MUX
sinc.
Tributaries
SDH architecture
16/
63
Reference model
IP
Frame
RTB ISDN Relay
IP
ATM
ATM
Frame
Relay ISDN RTB
interchange unit
paths
sections
SDH frame
VC-12
low order VC-12
low order VC-12
high order VC-4
VC-4
high order VC-4
seccin
multiplexing
de multiplexin
section
MSOH
seccin
regeneration
de regeneracin
section
RSOH
physical interface
STM-1
physical interface
NNI
SDH architecture
17/
63
Section
Regenerators (REG)
STM-N
REG
STM-N
SDH architecture
19/
63
2M
8M
STM-1
L O -P T E
34M
H O -P T E
SDH
MUX
STM-N
45M
140M
Overhead management
SDH architecture
20/
63
STM-N
SDH
MUX
STM-M
M >N
STM-N

4 x STM-1 = STM4
4 x STM-4 = STM16
4 x STM-16 = STM64
SDH architecture
21/
63
West
East
STM-M
STM-M
STM-N, PDH
SDH architecture
22/
63
STM-N
STM-N
STM-N
STM-N
SDH architecture
23/
63
MUX
2M
34M
LPT
HPT
MUX
STM-1 SDH
MUX
REG
STM-N MUX
MUX STM-N
SDH STM-1
MUX
2M
HPT
LPT
34M
45M
45M
140M
140M
SDH architecture
24/
63
Ring topology
back up ring
ADM
ADM
ADM
tributary
active ring
tributary
ADM
SDH architecture
25/
63

E
A
B
C
Star PDH network
C
SDH Network
SDH architecture
26/
63
Transport design
National Backbone
STM-16
Primary Network
STM-4
Access Network
STM-1 or PDH
SDH architecture
27/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
28/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
29/
63

LTMUX
LO HO
MUX
REG
REG
SECT
DXC
REG
SECT
REG
REG
SECT
ADM
REG
SECT
LTMUX
HO LO
REG
REG
SECT
REG
SECT
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
30/
63
Original signal
Regenerated signal
REG
REG
ADM
attenuation
Regenerator
Multiplexer
noise
distortion
Regenerator
SDH architecture
31/
63
Transport Services
2 Mbit/s PSTN
2 Mbit/s
34 Mbit/s
34 Mbit/s
ADM
ADM
ADM
ADM
ADM
A
DM
STM-16
STM-1
DXC
STM-1
ADM
ADM
STM-1,4
STM-1
ADM
ADM
2 Mbit/s
34 Mbit/s
140 Mbit/s
C
irc
ui
t
ADM
ADM
Internet
STM-4
LTMUX
140 Mbit/s
ADM
ADM
ADM
ADM
155 Mbit/s
ISDN
LTMUX
ATM
ATM
2 Mbit/s
GSM
SDH architecture
32/
63
Security
Section
Security services
strategies:
diversification
restoration
protection
SDH architecture
34/
63
Diversification
route 1 (50% C1-C2)
C1
C2
D
route 2 (50% C1-C2)
SDH architecture
35/
63
Restoration
A
(5,2)
(4,2)
(7,0)
(6,0)
(4,5)
(3,4)
(7,7)
(5,2)
(11,3)

alternative route
SDH architecture
36/
63
Protection (i)
SDH path protection

SDH architecture
37/
63
MUX
1+1
MUX
high priority
service (S)
protection (P)
MUX
MUX
low priority
1:1
1:N
MUX
MUX
SDH architecture
38/
63

A circuit in bakup
B circuit
protection ring
service ring
B circuit
ADM
ADM
ADM
ADM
ADM
A circuit
ADM
A circuit
B circuit
A circuit in bakup
B circuit
SDH architecture
39/
63


protection services
service circuits
ADM
ADM
ADM
service circuits

protection services
SDH architecture
40/
63


circuito A
en back up
A circuit
ADM
ADM
ADM
ADM
AD
M
ADM
circuito A
circuito A
en back up
SDH architecture
41/
63

STM-1
AUG
VC-n
C-n
+ AU
+ HO POH
(pointer)
Mbit/s
140,
33 44 ,, 44 55
+ stuffing bits
+ overhead bits
TUG
TU-n
+ TU
VC-n
+LO POH
C-n
M
Mbbiitt//ss
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
Section

10 Gbit/s
STM-64
2,5 Gbit/s
STM-16
622 Mbit/s
STM-4
155 Mbit/s
x1
AUG16
x4
x1
AUG16
x4
x1
AUG4
x1
x1
x4
x1 AUG
STM-1
x1
AU416c
VC416c
AU44c
VC44c
AU-4
VC-4
x1
C416c
x1
C-44c
x1
C-4
ATM:149760 kbit/s
E4: 139264kbit/s
C-3
ATM:48384kbit/s
T3:44736kbit/s
E3: 34368 kbit/s
x3
SI)
( AN
51 Mbit/s
x1
STM-0
x1
TUG-3
x3
AU-3
TU-3
VC-3
(ANSI)
VC-3
x7
(AN
SI)
x7
x1
TUG-2
TU-2
VC-2
C-2
ATM:6874kbit/s
T2: 6312kbit/s
TU-12
VC-12
C-12
ATM:2144kbit/s
E1:2048kbit/s
TU-11
VC-11
C-11
ATM 1600 kbit/s

T1: 1544kbit/s
x3
Frame
Pointer processing
Aliingning
Multiplexing
POH addition
Tributary mapping
SI)
(AN
x4
Container
Group
43/
63
S T M -1
A U G
V C -n
C -n
+ AU
+ HO POH
(pointer)
M b i t /s
140,
34, 45
+ stuffing bits
+ overhead bits
TUG
T U -n
+ TU
(pointer)
V C -n
+L O P O H
C -n
Mbit/s
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
44/
63
Containers
autonomous
master clock
synchronized
master clock
synchronism
PDH frames
SDH container
mapping
stuffing
justification
bit oriented
2Mbit/s
MUX
8Mbit/s
mapping
stuffing
justification
byte oriented
MUX
155Mbit/s
2Mbit/s
45/
63
The container C-4

C-4
11
270
12
12
12
12
12
1 C-4 row
column 11
column 270
= CSSSSSOO
= I I I I I IJ S
: stuffing byte
I: Information bit
S: Stuffing bit
O: Overhead bit
46/
63

C -4 into a V C -4
10
1
11
270
J1
B3
C2
G1
F2
H4
F3
VC-4 Path
Overhead
(POH) is added
K3
9
N1
C4+POH=VC4
47/
63
1
STM-1
9 10
RSOH
10
270
VC-4
11
270
J1
B3
AUG
C2
G1
MSOH
F2
H4
F3
K3
POH
N1
48/
63

V=150 km/h
VC-4
155 km/h
STM-1
STM-1
VC-4
VC-4
VC-4
STM-1
49/
63

V<150 km/h
VC-4
VC-4
VC-4
VC-4
155 km/h
STM-1
STM-1
STM-1
between two frames
50/
63
The STM-1 frame
Regenerator
Section
Overhead
S T M -1
9 10
RSOH
10
270
VC-4
11
270
J1
Administrative
Unit Group
B3
C2
Multiplexer
Section
Overhead
G1
MSOH
F2
H4
F3
K3
POH
N1
51/
63

STM-1
1
270
9 10
RSOH
10
VC-4
11
270
J1
B3
C2
G1
MSOH
F2
H4
Z3
Z4
POH
Z5
Composition
2Mbit/s
34Mbit/s
140Mbit/s
1 VC4
3 VC3
21 VC12 + 2 VC3
21
42 VC12 + 1 VC3
42
63 VC12
63
52/
63
The STM-N frames

0
1
2
3
x4
0123
4
5
6
7
x4
4567
x4
8
9
A
B
x4
89AB
C
D
E
F
x4
CDEF
direct multiplexing
x16
0123456789ABCDEF
0123456789ABCDEF
Frame
Short Id.
STM-1
STM-4
155.520 x 4 = 622.080 kbit/s 622 Mbit/s
STM-16
622.080 x 4 = 2.488.320 kbit/s 2,5 Gbit/s
STM-64
2.488.320 x 4 = 9.953.280 kbit/s 10 Gbit/s
53/
63
J0 A2 A2 A2 A1 A1 A1
A1 A1
A1 A2
A2 A2 J0

125s

sinchronization
125s
54/
63
45Mbit/s
SDH
45 Mbit/s
Section

TUG-3
TU-3
VC-3
x3
34
+ TU
pointer
STM-1
+ SOH
AUG
+ AU
pointer
VC-n
C-3
+ LO POH
+ stuffing bits
+ overhead bits
+ HO POH

56/
63

1 1 1
25
1 1 1
25
Y I
1 1 1
Z I
25
I
Public Network
X = SSC I I I I I
Y = CCSSSSSS
I: Information bit
S: Stuffing bit
O: Overhead bit
Z = CCSSOOSJ
C-3
3
45Mbit/s
86
C-3
VC-3
57/
63
2Mbit/s
VC-3
2
1
(85 columnas)
86
J1
C-3
B3
C2
G1
F2
VC-3
H4
F3
K3
9
N1
C -3
TU-3

58/
63
VC-3
T U -3
2
H1
H2
H3
86
J1
x1
B3
C2
G1
TU-3
F2
H4
F3
Pointer bytes
K3
9
N1
V C -3
TUG-3
59/
63
TU-3
T U G -3
1
1
86
H1
H2
J1
H3
B3
x1
C2
TUG-3
G1
F2
R
H4
x3
F3
9
K3
N1
VC-4
60/
63
11
1
12
13
270
14
TUG-3
J1
B3
x3
C2
G1
F2 R
byte interleaving
3 TUG-3
VC-4
H4
F3
K3
9
( 3 x 86 = 258 columns )
N1
AU-4
stuffing bytes
61/
63
STM-1
9 10
RSOH
10
VC-4
11
VC-4
270
270
J1
B3
C2
G1
MSOH
AU-4
F2
H4
F3
K3
N1
POH
STM-1
62/
63
VC-4
9 10
STM-1
270
RSOH
AU-4
AUG
MSOH
STM-1
63/
63

PDH limitations

fourth hierarchy)


byte oriented

rest of the world


2Mbit/s with CRC4
2/
63

small companies.

definition

Advanced management

multimedia
3/
63
bytes vs. bits
frame 1
125 s
0
frame 2
125 s
1 byte
n 0
rate =
8 bits
12510-6seg.
= 64Kbit/s
4/
63
SDH objectives (i)
between equipments

speed tributaries

service

management

networks
fault tolerance
5/
63
6/
63
services
Internet
Frame Relay
RTB
ATM
GSM
transport network
SDH
transmission media
cable/fiber/radio
7/
63
SDH architecture
client
server
Section
inputs
Function of
outputs
connectivity
and overheads
SDH architecture
9/
63
SDH architecture
10/
63
network connection
Client layer
digitalization
codification
Server layer
add/drop
overheads
path

SDH architecture
11/
63
Reference points
Network connection
Layer Adaptation
Layer Adaptation
AP
AP
Layer Termination
Network connection
Layer Termination
Subnetwork
link
TCP
CP
CP
TCP
CP
CP
SDH architecture
12/
63
Connectivity
Client Path
Client layer
Server layer
AP
AP
Network Connection
Link Connection
Subnetwork
Connection
Subnetwork
Connection
TCP
TCP
CP
CP
CP
CP
Server Path
TCP
to multipoint
SDH architecture
13/
63
2 Mbit/s circuit
2 Mbit/s level
VC12 level
DXC
DXC
Subnetwork
Subnetwork
connection
VC12 level path
connection
VC4 level
Layer Adaptation
Layer Termination
VC4 level path

STM level
Layer Adaptation
Layer Termination
STM-1 section
transmission media
SDH architecture
14/
63

client connection
Layer Adaptation
Layer Adaptation
trail
AP
TCP
CP
CP
CP
TCP
CP
Maintenance)
SDH architecture
15/
63

NNI
NNI
NNI
NNI
Tributaries
Tributaries
Tributaries
MUX
sinc.
Media :
PDH
ATM
MUX
sinc.
CXC
DIGITAL CONNETION
fiber
wireless
MUX
sinc.
Media :
fiber
wireless
MUX
sinc.
ACCESS
PDH
ATM
MUX
sinc.
MUX
sinc.
Tributaries
SDH architecture
16/
63
Reference model
IP
Frame
RTB ISDN Relay
IP
ATM
ATM
Frame
Relay ISDN RTB
interchange unit
paths
sections
SDH frame
VC-12
low order VC-12
low order VC-12
high order VC-4
VC-4
high order VC-4
seccin
multiplexing
de multiplexin
section
MSOH
seccin
regeneration
de regeneracin
section
RSOH
physical interface
STM-1
physical interface
NNI
SDH architecture
17/
63
Section
Regenerators (REG)
STM-N
REG
STM-N
SDH architecture
19/
63
2M
8M
STM-1
L O -P T E
34M
H O -P T E
SDH
MUX
STM-N
45M
140M
Overhead management
SDH architecture
20/
63
STM-N
SDH
MUX
STM-M
M >N
STM-N

4 x STM-1 = STM4
4 x STM-4 = STM16
4 x STM-16 = STM64
SDH architecture
21/
63
West
East
STM-M
STM-M
STM-N, PDH
SDH architecture
22/
63
STM-N
STM-N
STM-N
STM-N
SDH architecture
23/
63
MUX
2M
34M
LPT
HPT
MUX
STM-1 SDH
MUX
REG
STM-N MUX
MUX STM-N
SDH STM-1
MUX
2M
HPT
LPT
34M
45M
45M
140M
140M
SDH architecture
24/
63
Ring topology
back up ring
ADM
ADM
ADM
tributary
active ring
tributary
ADM
SDH architecture
25/
63

E
A
B
C
Star PDH network
C
SDH Network
SDH architecture
26/
63
Transport design
National Backbone
STM-16
Primary Network
STM-4
Access Network
STM-1 or PDH
SDH architecture
27/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
28/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
29/
63

LTMUX
LO HO
MUX
REG
REG
SECT
DXC
REG
SECT
REG
REG
SECT
ADM
REG
SECT
LTMUX
HO LO
REG
REG
SECT
REG
SECT
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
30/
63
Original signal
Regenerated signal
REG
REG
ADM
attenuation
Regenerator
Multiplexer
noise
distortion
Regenerator
SDH architecture
31/
63
Transport Services
2 Mbit/s PSTN
2 Mbit/s
34 Mbit/s
34 Mbit/s
ADM
ADM
ADM
ADM
ADM
A
DM
STM-16
STM-1
DXC
STM-1
ADM
ADM
STM-1,4
STM-1
ADM
ADM
2 Mbit/s
34 Mbit/s
140 Mbit/s
C
irc
ui
t
ADM
ADM
Internet
STM-4
LTMUX
140 Mbit/s
ADM
ADM
ADM
ADM
155 Mbit/s
ISDN
LTMUX
ATM
ATM
2 Mbit/s
GSM
SDH architecture
32/
63
Security
Section
Security services
strategies:
diversification
restoration
protection
SDH architecture
34/
63
Diversification
route 1 (50% C1-C2)
C1
C2
D
route 2 (50% C1-C2)
SDH architecture
35/
63
Restoration
A
(5,2)
(4,2)
(7,0)
(6,0)
(4,5)
(3,4)
(7,7)
(5,2)
(11,3)

alternative route
SDH architecture
36/
63
Protection (i)
SDH path protection

SDH architecture
37/
63
MUX
1+1
MUX
high priority
service (S)
protection (P)
MUX
MUX
low priority
1:1
1:N
MUX
MUX
SDH architecture
38/
63

A circuit in bakup
B circuit
protection ring
service ring
B circuit
ADM
ADM
ADM
ADM
ADM
A circuit
ADM
A circuit
B circuit
A circuit in bakup
B circuit
SDH architecture
39/
63


protection services
service circuits
ADM
ADM
ADM
service circuits

protection services
SDH architecture
40/
63


circuito A
en back up
A circuit
ADM
ADM
ADM
ADM
AD
M
ADM
circuito A
circuito A
en back up
SDH architecture
41/
63

STM-1
AUG
VC-n
C-n
+ AU
+ HO POH
(pointer)
Mbit/s
140,
33 44 ,, 44 55
+ stuffing bits
+ overhead bits
TUG
TU-n
+ TU
VC-n
+LO POH
C-n
M
Mbbiitt//ss
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
Section

10 Gbit/s
STM-64
2,5 Gbit/s
STM-16
622 Mbit/s
STM-4
155 Mbit/s
x1
AUG16
x4
x1
AUG16
x4
x1
AUG4
x1
x1
x4
x1 AUG
STM-1
x1
AU416c
VC416c
AU44c
VC44c
AU-4
VC-4
x1
C416c
x1
C-44c
x1
C-4
ATM:149760 kbit/s
E4: 139264kbit/s
C-3
ATM:48384kbit/s
T3:44736kbit/s
E3: 34368 kbit/s
x3
SI)
( AN
51 Mbit/s
x1
STM-0
x1
TUG-3
x3
AU-3
TU-3
VC-3
(ANSI)
VC-3
x7
(AN
SI)
x7
x1
TUG-2
TU-2
VC-2
C-2
ATM:6874kbit/s
T2: 6312kbit/s
TU-12
VC-12
C-12
ATM:2144kbit/s
E1:2048kbit/s
TU-11
VC-11
C-11
ATM 1600 kbit/s

T1: 1544kbit/s
x3
Frame
Pointer processing
Aliingning
Multiplexing
POH addition
Tributary mapping
SI)
(AN
x4
Container
Group
43/
63
S T M -1
A U G
V C -n
C -n
+ AU
+ HO POH
(pointer)
M b i t /s
140,
34, 45
+ stuffing bits
+ overhead bits
TUG
T U -n
+ TU
(pointer)
V C -n
+L O P O H
C -n
Mbit/s
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
44/
63
Containers
autonomous
master clock
synchronized
master clock
synchronism
PDH frames
SDH container
mapping
stuffing
justification
bit oriented
2Mbit/s
MUX
8Mbit/s
mapping
stuffing
justification
byte oriented
MUX
155Mbit/s
2Mbit/s
45/
63
The container C-4

C-4
11
270
12
12
12
12
12
1 C-4 row
column 11
column 270
= CSSSSSOO
= I I I I I IJ S
: stuffing byte
I: Information bit
S: Stuffing bit
O: Overhead bit
46/
63

C -4 into a V C -4
10
1
11
270
J1
B3
C2
G1
F2
H4
F3
VC-4 Path
Overhead
(POH) is added
K3
9
N1
C4+POH=VC4
47/
63
1
STM-1
9 10
RSOH
10
270
VC-4
11
270
J1
B3
AUG
C2
G1
MSOH
F2
H4
F3
K3
POH
N1
48/
63

V=150 km/h
VC-4
155 km/h
STM-1
STM-1
VC-4
VC-4
VC-4
STM-1
49/
63

V<150 km/h
VC-4
VC-4
VC-4
VC-4
155 km/h
STM-1
STM-1
STM-1
between two frames
50/
63
The STM-1 frame
Regenerator
Section
Overhead
S T M -1
9 10
RSOH
10
270
VC-4
11
270
J1
Administrative
Unit Group
B3
C2
Multiplexer
Section
Overhead
G1
MSOH
F2
H4
F3
K3
POH
N1
51/
63

STM-1
1
270
9 10
RSOH
10
VC-4
11
270
J1
B3
C2
G1
MSOH
F2
H4
Z3
Z4
POH
Z5
Composition
2Mbit/s
34Mbit/s
140Mbit/s
1 VC4
3 VC3
21 VC12 + 2 VC3
21
42 VC12 + 1 VC3
42
63 VC12
63
52/
63
The STM-N frames

0
1
2
3
x4
0123
4
5
6
7
x4
4567
x4
8
9
A
B
x4
89AB
C
D
E
F
x4
CDEF
direct multiplexing
x16
0123456789ABCDEF
0123456789ABCDEF
Frame
Short Id.
STM-1
STM-4
155.520 x 4 = 622.080 kbit/s 622 Mbit/s
STM-16
622.080 x 4 = 2.488.320 kbit/s 2,5 Gbit/s
STM-64
2.488.320 x 4 = 9.953.280 kbit/s 10 Gbit/s
53/
63
J0 A2 A2 A2 A1 A1 A1
A1 A1
A1 A2
A2 A2 J0

125s

sinchronization
125s
54/
63
45Mbit/s
SDH
45 Mbit/s
Section

TUG-3
TU-3
VC-3
x3
34
+ TU
pointer
STM-1
+ SOH
AUG
+ AU
pointer
VC-n
C-3
+ LO POH
+ stuffing bits
+ overhead bits
+ HO POH

56/
63

1 1 1
25
1 1 1
25
Y I
1 1 1
Z I
25
I
Public Network
X = SSC I I I I I
Y = CCSSSSSS
I: Information bit
S: Stuffing bit
O: Overhead bit
Z = CCSSOOSJ
C-3
3
45Mbit/s
86
C-3
VC-3
57/
63
2Mbit/s
VC-3
2
1
(85 columnas)
86
J1
C-3
B3
C2
G1
F2
VC-3
H4
F3
K3
9
N1
C -3
TU-3

58/
63
VC-3
T U -3
2
H1
H2
H3
86
J1
x1
B3
C2
G1
TU-3
F2
H4
F3
Pointer bytes
K3
9
N1
V C -3
TUG-3
59/
63
TU-3
T U G -3
1
1
86
H1
H2
J1
H3
B3
x1
C2
TUG-3
G1
F2
R
H4
x3
F3
9
K3
N1
VC-4
60/
63
11
1
12
13
270
14
TUG-3
J1
B3
x3
C2
G1
F2 R
byte interleaving
3 TUG-3
VC-4
H4
F3
K3
9
( 3 x 86 = 258 columns )
N1
AU-4
stuffing bytes
61/
63
STM-1
9 10
RSOH
10
VC-4
11
VC-4
270
270
J1
B3
C2
G1
MSOH
AU-4
F2
H4
F3
K3
N1
POH
STM-1
62/
63
VC-4
9 10
STM-1
270
RSOH
AU-4
AUG
MSOH
STM-1
63/
63

PDH limitations

fourth hierarchy)


byte oriented

rest of the world


2Mbit/s with CRC4
2/
63

small companies.

definition

Advanced management

multimedia
3/
63
bytes vs. bits
frame 1
125 s
0
frame 2
125 s
1 byte
n 0
rate =
8 bits
12510-6seg.
= 64Kbit/s
4/
63
SDH objectives (i)
between equipments

speed tributaries

service

management

networks
fault tolerance
5/
63
6/
63
services
Internet
Frame Relay
RTB
ATM
GSM
transport network
SDH
transmission media
cable/fiber/radio
7/
63
SDH architecture
client
server
Section
inputs
Function of
outputs
connectivity
and overheads
SDH architecture
9/
63
SDH architecture
10/
63
network connection
Client layer
digitalization
codification
Server layer
add/drop
overheads
path

SDH architecture
11/
63
Reference points
Network connection
Layer Adaptation
Layer Adaptation
AP
AP
Layer Termination
Network connection
Layer Termination
Subnetwork
link
TCP
CP
CP
TCP
CP
CP
SDH architecture
12/
63
Connectivity
Client Path
Client layer
Server layer
AP
AP
Network Connection
Link Connection
Subnetwork
Connection
Subnetwork
Connection
TCP
TCP
CP
CP
CP
CP
Server Path
TCP
to multipoint
SDH architecture
13/
63
2 Mbit/s circuit
2 Mbit/s level
VC12 level
DXC
DXC
Subnetwork
Subnetwork
connection
VC12 level path
connection
VC4 level
Layer Adaptation
Layer Termination
VC4 level path

STM level
Layer Adaptation
Layer Termination
STM-1 section
transmission media
SDH architecture
14/
63

client connection
Layer Adaptation
Layer Adaptation
trail
AP
TCP
CP
CP
CP
TCP
CP
Maintenance)
SDH architecture
15/
63

NNI
NNI
NNI
NNI
Tributaries
Tributaries
Tributaries
MUX
sinc.
Media :
PDH
ATM
MUX
sinc.
CXC
DIGITAL CONNETION
fiber
wireless
MUX
sinc.
Media :
fiber
wireless
MUX
sinc.
ACCESS
PDH
ATM
MUX
sinc.
MUX
sinc.
Tributaries
SDH architecture
16/
63
Reference model
IP
Frame
RTB ISDN Relay
IP
ATM
ATM
Frame
Relay ISDN RTB
interchange unit
paths
sections
SDH frame
VC-12
low order VC-12
low order VC-12
high order VC-4
VC-4
high order VC-4
seccin
multiplexing
de multiplexin
section
MSOH
seccin
regeneration
de regeneracin
section
RSOH
physical interface
STM-1
physical interface
NNI
SDH architecture
17/
63
Section
Regenerators (REG)
STM-N
REG
STM-N
SDH architecture
19/
63
2M
8M
STM-1
L O -P T E
34M
H O -P T E
SDH
MUX
STM-N
45M
140M
Overhead management
SDH architecture
20/
63
STM-N
SDH
MUX
STM-M
M >N
STM-N

4 x STM-1 = STM4
4 x STM-4 = STM16
4 x STM-16 = STM64
SDH architecture
21/
63
West
East
STM-M
STM-M
STM-N, PDH
SDH architecture
22/
63
STM-N
STM-N
STM-N
STM-N
SDH architecture
23/
63
MUX
2M
34M
LPT
HPT
MUX
STM-1 SDH
MUX
REG
STM-N MUX
MUX STM-N
SDH STM-1
MUX
2M
HPT
LPT
34M
45M
45M
140M
140M
SDH architecture
24/
63
Ring topology
back up ring
ADM
ADM
ADM
tributary
active ring
tributary
ADM
SDH architecture
25/
63

E
A
B
C
Star PDH network
C
SDH Network
SDH architecture
26/
63
Transport design
National Backbone
STM-16
Primary Network
STM-4
Access Network
STM-1 or PDH
SDH architecture
27/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
28/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
29/
63

LTMUX
LO HO
MUX
REG
REG
SECT
DXC
REG
SECT
REG
REG
SECT
ADM
REG
SECT
LTMUX
HO LO
REG
REG
SECT
REG
SECT
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
30/
63
Original signal
Regenerated signal
REG
REG
ADM
attenuation
Regenerator
Multiplexer
noise
distortion
Regenerator
SDH architecture
31/
63
Transport Services
2 Mbit/s PSTN
2 Mbit/s
34 Mbit/s
34 Mbit/s
ADM
ADM
ADM
ADM
ADM
A
DM
STM-16
STM-1
DXC
STM-1
ADM
ADM
STM-1,4
STM-1
ADM
ADM
2 Mbit/s
34 Mbit/s
140 Mbit/s
C
irc
ui
t
ADM
ADM
Internet
STM-4
LTMUX
140 Mbit/s
ADM
ADM
ADM
ADM
155 Mbit/s
ISDN
LTMUX
ATM
ATM
2 Mbit/s
GSM
SDH architecture
32/
63
Security
Section
Security services
strategies:
diversification
restoration
protection
SDH architecture
34/
63
Diversification
route 1 (50% C1-C2)
C1
C2
D
route 2 (50% C1-C2)
SDH architecture
35/
63
Restoration
A
(5,2)
(4,2)
(7,0)
(6,0)
(4,5)
(3,4)
(7,7)
(5,2)
(11,3)

alternative route
SDH architecture
36/
63
Protection (i)
SDH path protection

SDH architecture
37/
63
MUX
1+1
MUX
high priority
service (S)
protection (P)
MUX
MUX
low priority
1:1
1:N
MUX
MUX
SDH architecture
38/
63

A circuit in bakup
B circuit
protection ring
service ring
B circuit
ADM
ADM
ADM
ADM
ADM
A circuit
ADM
A circuit
B circuit
A circuit in bakup
B circuit
SDH architecture
39/
63


protection services
service circuits
ADM
ADM
ADM
service circuits

protection services
SDH architecture
40/
63


circuito A
en back up
A circuit
ADM
ADM
ADM
ADM
AD
M
ADM
circuito A
circuito A
en back up
SDH architecture
41/
63

STM-1
AUG
VC-n
C-n
+ AU
+ HO POH
(pointer)
Mbit/s
140,
33 44 ,, 44 55
+ stuffing bits
+ overhead bits
TUG
TU-n
+ TU
VC-n
+LO POH
C-n
M
Mbbiitt//ss
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
Section

10 Gbit/s
STM-64
2,5 Gbit/s
STM-16
622 Mbit/s
STM-4
155 Mbit/s
x1
AUG16
x4
x1
AUG16
x4
x1
AUG4
x1
x1
x4
x1 AUG
STM-1
x1
AU416c
VC416c
AU44c
VC44c
AU-4
VC-4
x1
C416c
x1
C-44c
x1
C-4
ATM:149760 kbit/s
E4: 139264kbit/s
C-3
ATM:48384kbit/s
T3:44736kbit/s
E3: 34368 kbit/s
x3
SI)
( AN
51 Mbit/s
x1
STM-0
x1
TUG-3
x3
AU-3
TU-3
VC-3
(ANSI)
VC-3
x7
(AN
SI)
x7
x1
TUG-2
TU-2
VC-2
C-2
ATM:6874kbit/s
T2: 6312kbit/s
TU-12
VC-12
C-12
ATM:2144kbit/s
E1:2048kbit/s
TU-11
VC-11
C-11
ATM 1600 kbit/s

T1: 1544kbit/s
x3
Frame
Pointer processing
Aliingning
Multiplexing
POH addition
Tributary mapping
SI)
(AN
x4
Container
Group
43/
63
S T M -1
A U G
V C -n
C -n
+ AU
+ HO POH
(pointer)
M b i t /s
140,
34, 45
+ stuffing bits
+ overhead bits
TUG
T U -n
+ TU
(pointer)
V C -n
+L O P O H
C -n
Mbit/s
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
44/
63
Containers
autonomous
master clock
synchronized
master clock
synchronism
PDH frames
SDH container
mapping
stuffing
justification
bit oriented
2Mbit/s
MUX
8Mbit/s
mapping
stuffing
justification
byte oriented
MUX
155Mbit/s
2Mbit/s
45/
63
The container C-4

C-4
11
270
12
12
12
12
12
1 C-4 row
column 11
column 270
= CSSSSSOO
= I I I I I IJ S
: stuffing byte
I: Information bit
S: Stuffing bit
O: Overhead bit
46/
63

C -4 into a V C -4
10
1
11
270
J1
B3
C2
G1
F2
H4
F3
VC-4 Path
Overhead
(POH) is added
K3
9
N1
C4+POH=VC4
47/
63
1
STM-1
9 10
RSOH
10
270
VC-4
11
270
J1
B3
AUG
C2
G1
MSOH
F2
H4
F3
K3
POH
N1
48/
63

V=150 km/h
VC-4
155 km/h
STM-1
STM-1
VC-4
VC-4
VC-4
STM-1
49/
63

V<150 km/h
VC-4
VC-4
VC-4
VC-4
155 km/h
STM-1
STM-1
STM-1
between two frames
50/
63
The STM-1 frame
Regenerator
Section
Overhead
S T M -1
9 10
RSOH
10
270
VC-4
11
270
J1
Administrative
Unit Group
B3
C2
Multiplexer
Section
Overhead
G1
MSOH
F2
H4
F3
K3
POH
N1
51/
63

STM-1
1
270
9 10
RSOH
10
VC-4
11
270
J1
B3
C2
G1
MSOH
F2
H4
Z3
Z4
POH
Z5
Composition
2Mbit/s
34Mbit/s
140Mbit/s
1 VC4
3 VC3
21 VC12 + 2 VC3
21
42 VC12 + 1 VC3
42
63 VC12
63
52/
63
The STM-N frames

0
1
2
3
x4
0123
4
5
6
7
x4
4567
x4
8
9
A
B
x4
89AB
C
D
E
F
x4
CDEF
direct multiplexing
x16
0123456789ABCDEF
0123456789ABCDEF
Frame
Short Id.
STM-1
STM-4
155.520 x 4 = 622.080 kbit/s 622 Mbit/s
STM-16
622.080 x 4 = 2.488.320 kbit/s 2,5 Gbit/s
STM-64
2.488.320 x 4 = 9.953.280 kbit/s 10 Gbit/s
53/
63
J0 A2 A2 A2 A1 A1 A1
A1 A1
A1 A2
A2 A2 J0

125s

sinchronization
125s
54/
63
45Mbit/s
SDH
45 Mbit/s
Section

TUG-3
TU-3
VC-3
x3
34
+ TU
pointer
STM-1
+ SOH
AUG
+ AU
pointer
VC-n
C-3
+ LO POH
+ stuffing bits
+ overhead bits
+ HO POH

56/
63

1 1 1
25
1 1 1
25
Y I
1 1 1
Z I
25
I
Public Network
X = SSC I I I I I
Y = CCSSSSSS
I: Information bit
S: Stuffing bit
O: Overhead bit
Z = CCSSOOSJ
C-3
3
45Mbit/s
86
C-3
VC-3
57/
63
2Mbit/s
VC-3
2
1
(85 columnas)
86
J1
C-3
B3
C2
G1
F2
VC-3
H4
F3
K3
9
N1
C -3
TU-3

58/
63
VC-3
T U -3
2
H1
H2
H3
86
J1
x1
B3
C2
G1
TU-3
F2
H4
F3
Pointer bytes
K3
9
N1
V C -3
TUG-3
59/
63
TU-3
T U G -3
1
1
86
H1
H2
J1
H3
B3
x1
C2
TUG-3
G1
F2
R
H4
x3
F3
9
K3
N1
VC-4
60/
63
11
1
12
13
270
14
TUG-3
J1
B3
x3
C2
G1
F2 R
byte interleaving
3 TUG-3
VC-4
H4
F3
K3
9
( 3 x 86 = 258 columns )
N1
AU-4
stuffing bytes
61/
63
STM-1
9 10
RSOH
10
VC-4
11
VC-4
270
270
J1
B3
C2
G1
MSOH
AU-4
F2
H4
F3
K3
N1
POH
STM-1
62/
63
VC-4
9 10
STM-1
270
RSOH
AU-4
AUG
MSOH
STM-1
63/
63

PDH limitations

fourth hierarchy)


byte oriented

rest of the world


2Mbit/s with CRC4
2/
63

small companies.

definition

Advanced management

multimedia
3/
63
bytes vs. bits
frame 1
125 s
0
frame 2
125 s
1 byte
n 0
rate =
8 bits
12510-6seg.
= 64Kbit/s
4/
63
SDH objectives (i)
between equipments

speed tributaries

service

management

networks
fault tolerance
5/
63
6/
63
services
Internet
Frame Relay
RTB
ATM
GSM
transport network
SDH
transmission media
cable/fiber/radio
7/
63
SDH architecture
client
server
Section
inputs
Function of
outputs
connectivity
and overheads
SDH architecture
9/
63
SDH architecture
10/
63
network connection
Client layer
digitalization
codification
Server layer
add/drop
overheads
path

SDH architecture
11/
63
Reference points
Network connection
Layer Adaptation
Layer Adaptation
AP
AP
Layer Termination
Network connection
Layer Termination
Subnetwork
link
TCP
CP
CP
TCP
CP
CP
SDH architecture
12/
63
Connectivity
Client Path
Client layer
Server layer
AP
AP
Network Connection
Link Connection
Subnetwork
Connection
Subnetwork
Connection
TCP
TCP
CP
CP
CP
CP
Server Path
TCP
to multipoint
SDH architecture
13/
63
2 Mbit/s circuit
2 Mbit/s level
VC12 level
DXC
DXC
Subnetwork
Subnetwork
connection
VC12 level path
connection
VC4 level
Layer Adaptation
Layer Termination
VC4 level path

STM level
Layer Adaptation
Layer Termination
STM-1 section
transmission media
SDH architecture
14/
63

client connection
Layer Adaptation
Layer Adaptation
trail
AP
TCP
CP
CP
CP
TCP
CP
Maintenance)
SDH architecture
15/
63

NNI
NNI
NNI
NNI
Tributaries
Tributaries
Tributaries
MUX
sinc.
Media :
PDH
ATM
MUX
sinc.
CXC
DIGITAL CONNETION
fiber
wireless
MUX
sinc.
Media :
fiber
wireless
MUX
sinc.
ACCESS
PDH
ATM
MUX
sinc.
MUX
sinc.
Tributaries
SDH architecture
16/
63
Reference model
IP
Frame
RTB ISDN Relay
IP
ATM
ATM
Frame
Relay ISDN RTB
interchange unit
paths
sections
SDH frame
VC-12
low order VC-12
low order VC-12
high order VC-4
VC-4
high order VC-4
seccin
multiplexing
de multiplexin
section
MSOH
seccin
regeneration
de regeneracin
section
RSOH
physical interface
STM-1
physical interface
NNI
SDH architecture
17/
63
Section
Regenerators (REG)
STM-N
REG
STM-N
SDH architecture
19/
63
2M
8M
STM-1
L O -P T E
34M
H O -P T E
SDH
MUX
STM-N
45M
140M
Overhead management
SDH architecture
20/
63
STM-N
SDH
MUX
STM-M
M >N
STM-N

4 x STM-1 = STM4
4 x STM-4 = STM16
4 x STM-16 = STM64
SDH architecture
21/
63
West
East
STM-M
STM-M
STM-N, PDH
SDH architecture
22/
63
STM-N
STM-N
STM-N
STM-N
SDH architecture
23/
63
MUX
2M
34M
LPT
HPT
MUX
STM-1 SDH
MUX
REG
STM-N MUX
MUX STM-N
SDH STM-1
MUX
2M
HPT
LPT
34M
45M
45M
140M
140M
SDH architecture
24/
63
Ring topology
back up ring
ADM
ADM
ADM
tributary
active ring
tributary
ADM
SDH architecture
25/
63

E
A
B
C
Star PDH network
C
SDH Network
SDH architecture
26/
63
Transport design
National Backbone
STM-16
Primary Network
STM-4
Access Network
STM-1 or PDH
SDH architecture
27/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
28/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
29/
63

LTMUX
LO HO
MUX
REG
REG
SECT
DXC
REG
SECT
REG
REG
SECT
ADM
REG
SECT
LTMUX
HO LO
REG
REG
SECT
REG
SECT
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
30/
63
Original signal
Regenerated signal
REG
REG
ADM
attenuation
Regenerator
Multiplexer
noise
distortion
Regenerator
SDH architecture
31/
63
Transport Services
2 Mbit/s PSTN
2 Mbit/s
34 Mbit/s
34 Mbit/s
ADM
ADM
ADM
ADM
ADM
A
DM
STM-16
STM-1
DXC
STM-1
ADM
ADM
STM-1,4
STM-1
ADM
ADM
2 Mbit/s
34 Mbit/s
140 Mbit/s
C
irc
ui
t
ADM
ADM
Internet
STM-4
LTMUX
140 Mbit/s
ADM
ADM
ADM
ADM
155 Mbit/s
ISDN
LTMUX
ATM
ATM
2 Mbit/s
GSM
SDH architecture
32/
63
Security
Section
Security services
strategies:
diversification
restoration
protection
SDH architecture
34/
63
Diversification
route 1 (50% C1-C2)
C1
C2
D
route 2 (50% C1-C2)
SDH architecture
35/
63
Restoration
A
(5,2)
(4,2)
(7,0)
(6,0)
(4,5)
(3,4)
(7,7)
(5,2)
(11,3)

alternative route
SDH architecture
36/
63
Protection (i)
SDH path protection

SDH architecture
37/
63
MUX
1+1
MUX
high priority
service (S)
protection (P)
MUX
MUX
low priority
1:1
1:N
MUX
MUX
SDH architecture
38/
63

A circuit in bakup
B circuit
protection ring
service ring
B circuit
ADM
ADM
ADM
ADM
ADM
A circuit
ADM
A circuit
B circuit
A circuit in bakup
B circuit
SDH architecture
39/
63


protection services
service circuits
ADM
ADM
ADM
service circuits

protection services
SDH architecture
40/
63


circuito A
en back up
A circuit
ADM
ADM
ADM
ADM
AD
M
ADM
circuito A
circuito A
en back up
SDH architecture
41/
63

STM-1
AUG
VC-n
C-n
+ AU
+ HO POH
(pointer)
Mbit/s
140,
33 44 ,, 44 55
+ stuffing bits
+ overhead bits
TUG
TU-n
+ TU
VC-n
+LO POH
C-n
M
Mbbiitt//ss
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
Section

10 Gbit/s
STM-64
2,5 Gbit/s
STM-16
622 Mbit/s
STM-4
155 Mbit/s
x1
AUG16
x4
x1
AUG16
x4
x1
AUG4
x1
x1
x4
x1 AUG
STM-1
x1
AU416c
VC416c
AU44c
VC44c
AU-4
VC-4
x1
C416c
x1
C-44c
x1
C-4
ATM:149760 kbit/s
E4: 139264kbit/s
C-3
ATM:48384kbit/s
T3:44736kbit/s
E3: 34368 kbit/s
x3
SI)
( AN
51 Mbit/s
x1
STM-0
x1
TUG-3
x3
AU-3
TU-3
VC-3
(ANSI)
VC-3
x7
(AN
SI)
x7
x1
TUG-2
TU-2
VC-2
C-2
ATM:6874kbit/s
T2: 6312kbit/s
TU-12
VC-12
C-12
ATM:2144kbit/s
E1:2048kbit/s
TU-11
VC-11
C-11
ATM 1600 kbit/s

T1: 1544kbit/s
x3
Frame
Pointer processing
Aliingning
Multiplexing
POH addition
Tributary mapping
SI)
(AN
x4
Container
Group
43/
63
S T M -1
A U G
V C -n
C -n
+ AU
+ HO POH
(pointer)
M b i t /s
140,
34, 45
+ stuffing bits
+ overhead bits
TUG
T U -n
+ TU
(pointer)
V C -n
+L O P O H
C -n
Mbit/s
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
44/
63
Containers
autonomous
master clock
synchronized
master clock
synchronism
PDH frames
SDH container
mapping
stuffing
justification
bit oriented
2Mbit/s
MUX
8Mbit/s
mapping
stuffing
justification
byte oriented
MUX
155Mbit/s
2Mbit/s
45/
63
The container C-4

C-4
11
270
12
12
12
12
12
1 C-4 row
column 11
column 270
= CSSSSSOO
= I I I I I IJ S
: stuffing byte
I: Information bit
S: Stuffing bit
O: Overhead bit
46/
63

C -4 into a V C -4
10
1
11
270
J1
B3
C2
G1
F2
H4
F3
VC-4 Path
Overhead
(POH) is added
K3
9
N1
C4+POH=VC4
47/
63
1
STM-1
9 10
RSOH
10
270
VC-4
11
270
J1
B3
AUG
C2
G1
MSOH
F2
H4
F3
K3
POH
N1
48/
63

V=150 km/h
VC-4
155 km/h
STM-1
STM-1
VC-4
VC-4
VC-4
STM-1
49/
63

V<150 km/h
VC-4
VC-4
VC-4
VC-4
155 km/h
STM-1
STM-1
STM-1
between two frames
50/
63
The STM-1 frame
Regenerator
Section
Overhead
S T M -1
9 10
RSOH
10
270
VC-4
11
270
J1
Administrative
Unit Group
B3
C2
Multiplexer
Section
Overhead
G1
MSOH
F2
H4
F3
K3
POH
N1
51/
63

STM-1
1
270
9 10
RSOH
10
VC-4
11
270
J1
B3
C2
G1
MSOH
F2
H4
Z3
Z4
POH
Z5
Composition
2Mbit/s
34Mbit/s
140Mbit/s
1 VC4
3 VC3
21 VC12 + 2 VC3
21
42 VC12 + 1 VC3
42
63 VC12
63
52/
63
The STM-N frames

0
1
2
3
x4
0123
4
5
6
7
x4
4567
x4
8
9
A
B
x4
89AB
C
D
E
F
x4
CDEF
direct multiplexing
x16
0123456789ABCDEF
0123456789ABCDEF
Frame
Short Id.
STM-1
STM-4
155.520 x 4 = 622.080 kbit/s 622 Mbit/s
STM-16
622.080 x 4 = 2.488.320 kbit/s 2,5 Gbit/s
STM-64
2.488.320 x 4 = 9.953.280 kbit/s 10 Gbit/s
53/
63
J0 A2 A2 A2 A1 A1 A1
A1 A1
A1 A2
A2 A2 J0

125s

sinchronization
125s
54/
63
45Mbit/s
SDH
45 Mbit/s
Section

TUG-3
TU-3
VC-3
x3
34
+ TU
pointer
STM-1
+ SOH
AUG
+ AU
pointer
VC-n
C-3
+ LO POH
+ stuffing bits
+ overhead bits
+ HO POH

56/
63

1 1 1
25
1 1 1
25
Y I
1 1 1
Z I
25
I
Public Network
X = SSC I I I I I
Y = CCSSSSSS
I: Information bit
S: Stuffing bit
O: Overhead bit
Z = CCSSOOSJ
C-3
3
45Mbit/s
86
C-3
VC-3
57/
63
2Mbit/s
VC-3
2
1
(85 columnas)
86
J1
C-3
B3
C2
G1
F2
VC-3
H4
F3
K3
9
N1
C -3
TU-3

58/
63
VC-3
T U -3
2
H1
H2
H3
86
J1
x1
B3
C2
G1
TU-3
F2
H4
F3
Pointer bytes
K3
9
N1
V C -3
TUG-3
59/
63
TU-3
T U G -3
1
1
86
H1
H2
J1
H3
B3
x1
C2
TUG-3
G1
F2
R
H4
x3
F3
9
K3
N1
VC-4
60/
63
11
1
12
13
270
14
TUG-3
J1
B3
x3
C2
G1
F2 R
byte interleaving
3 TUG-3
VC-4
H4
F3
K3
9
( 3 x 86 = 258 columns )
N1
AU-4
stuffing bytes
61/
63
STM-1
9 10
RSOH
10
VC-4
11
VC-4
270
270
J1
B3
C2
G1
MSOH
AU-4
F2
H4
F3
K3
N1
POH
STM-1
62/
63
VC-4
9 10
STM-1
270
RSOH
AU-4
AUG
MSOH
STM-1
63/
63

PDH limitations

fourth hierarchy)


byte oriented

rest of the world


2Mbit/s with CRC4
2/
63

small companies.

definition

Advanced management

multimedia
3/
63
bytes vs. bits
frame 1
125 s
0
frame 2
125 s
1 byte
n 0
rate =
8 bits
12510-6seg.
= 64Kbit/s
4/
63
SDH objectives (i)
between equipments

speed tributaries

service

management

networks
fault tolerance
5/
63
6/
63
services
Internet
Frame Relay
RTB
ATM
GSM
transport network
SDH
transmission media
cable/fiber/radio
7/
63
SDH architecture
client
server
Section
inputs
Function of
outputs
connectivity
and overheads
SDH architecture
9/
63
SDH architecture
10/
63
network connection
Client layer
digitalization
codification
Server layer
add/drop
overheads
path

SDH architecture
11/
63
Reference points
Network connection
Layer Adaptation
Layer Adaptation
AP
AP
Layer Termination
Network connection
Layer Termination
Subnetwork
link
TCP
CP
CP
TCP
CP
CP
SDH architecture
12/
63
Connectivity
Client Path
Client layer
Server layer
AP
AP
Network Connection
Link Connection
Subnetwork
Connection
Subnetwork
Connection
TCP
TCP
CP
CP
CP
CP
Server Path
TCP
to multipoint
SDH architecture
13/
63
2 Mbit/s circuit
2 Mbit/s level
VC12 level
DXC
DXC
Subnetwork
Subnetwork
connection
VC12 level path
connection
VC4 level
Layer Adaptation
Layer Termination
VC4 level path

STM level
Layer Adaptation
Layer Termination
STM-1 section
transmission media
SDH architecture
14/
63

client connection
Layer Adaptation
Layer Adaptation
trail
AP
TCP
CP
CP
CP
TCP
CP
Maintenance)
SDH architecture
15/
63

NNI
NNI
NNI
NNI
Tributaries
Tributaries
Tributaries
MUX
sinc.
Media :
PDH
ATM
MUX
sinc.
CXC
DIGITAL CONNETION
fiber
wireless
MUX
sinc.
Media :
fiber
wireless
MUX
sinc.
ACCESS
PDH
ATM
MUX
sinc.
MUX
sinc.
Tributaries
SDH architecture
16/
63
Reference model
IP
Frame
RTB ISDN Relay
IP
ATM
ATM
Frame
Relay ISDN RTB
interchange unit
paths
sections
SDH frame
VC-12
low order VC-12
low order VC-12
high order VC-4
VC-4
high order VC-4
seccin
multiplexing
de multiplexin
section
MSOH
seccin
regeneration
de regeneracin
section
RSOH
physical interface
STM-1
physical interface
NNI
SDH architecture
17/
63
Section
Regenerators (REG)
STM-N
REG
STM-N
SDH architecture
19/
63
2M
8M
STM-1
L O -P T E
34M
H O -P T E
SDH
MUX
STM-N
45M
140M
Overhead management
SDH architecture
20/
63
STM-N
SDH
MUX
STM-M
M >N
STM-N

4 x STM-1 = STM4
4 x STM-4 = STM16
4 x STM-16 = STM64
SDH architecture
21/
63
West
East
STM-M
STM-M
STM-N, PDH
SDH architecture
22/
63
STM-N
STM-N
STM-N
STM-N
SDH architecture
23/
63
MUX
2M
34M
LPT
HPT
MUX
STM-1 SDH
MUX
REG
STM-N MUX
MUX STM-N
SDH STM-1
MUX
2M
HPT
LPT
34M
45M
45M
140M
140M
SDH architecture
24/
63
Ring topology
back up ring
ADM
ADM
ADM
tributary
active ring
tributary
ADM
SDH architecture
25/
63

E
A
B
C
Star PDH network
C
SDH Network
SDH architecture
26/
63
Transport design
National Backbone
STM-16
Primary Network
STM-4
Access Network
STM-1 or PDH
SDH architecture
27/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
28/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
29/
63

LTMUX
LO HO
MUX
REG
REG
SECT
DXC
REG
SECT
REG
REG
SECT
ADM
REG
SECT
LTMUX
HO LO
REG
REG
SECT
REG
SECT
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
30/
63
Original signal
Regenerated signal
REG
REG
ADM
attenuation
Regenerator
Multiplexer
noise
distortion
Regenerator
SDH architecture
31/
63
Transport Services
2 Mbit/s PSTN
2 Mbit/s
34 Mbit/s
34 Mbit/s
ADM
ADM
ADM
ADM
ADM
A
DM
STM-16
STM-1
DXC
STM-1
ADM
ADM
STM-1,4
STM-1
ADM
ADM
2 Mbit/s
34 Mbit/s
140 Mbit/s
C
irc
ui
t
ADM
ADM
Internet
STM-4
LTMUX
140 Mbit/s
ADM
ADM
ADM
ADM
155 Mbit/s
ISDN
LTMUX
ATM
ATM
2 Mbit/s
GSM
SDH architecture
32/
63
Security
Section
Security services
strategies:
diversification
restoration
protection
SDH architecture
34/
63
Diversification
route 1 (50% C1-C2)
C1
C2
D
route 2 (50% C1-C2)
SDH architecture
35/
63
Restoration
A
(5,2)
(4,2)
(7,0)
(6,0)
(4,5)
(3,4)
(7,7)
(5,2)
(11,3)

alternative route
SDH architecture
36/
63
Protection (i)
SDH path protection

SDH architecture
37/
63
MUX
1+1
MUX
high priority
service (S)
protection (P)
MUX
MUX
low priority
1:1
1:N
MUX
MUX
SDH architecture
38/
63

A circuit in bakup
B circuit
protection ring
service ring
B circuit
ADM
ADM
ADM
ADM
ADM
A circuit
ADM
A circuit
B circuit
A circuit in bakup
B circuit
SDH architecture
39/
63


protection services
service circuits
ADM
ADM
ADM
service circuits

protection services
SDH architecture
40/
63


circuito A
en back up
A circuit
ADM
ADM
ADM
ADM
AD
M
ADM
circuito A
circuito A
en back up
SDH architecture
41/
63

STM-1
AUG
VC-n
C-n
+ AU
+ HO POH
(pointer)
Mbit/s
140,
33 44 ,, 44 55
+ stuffing bits
+ overhead bits
TUG
TU-n
+ TU
VC-n
+LO POH
C-n
M
Mbbiitt//ss
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
Section

10 Gbit/s
STM-64
2,5 Gbit/s
STM-16
622 Mbit/s
STM-4
155 Mbit/s
x1
AUG16
x4
x1
AUG16
x4
x1
AUG4
x1
x1
x4
x1 AUG
STM-1
x1
AU416c
VC416c
AU44c
VC44c
AU-4
VC-4
x1
C416c
x1
C-44c
x1
C-4
ATM:149760 kbit/s
E4: 139264kbit/s
C-3
ATM:48384kbit/s
T3:44736kbit/s
E3: 34368 kbit/s
x3
SI)
( AN
51 Mbit/s
x1
STM-0
x1
TUG-3
x3
AU-3
TU-3
VC-3
(ANSI)
VC-3
x7
(AN
SI)
x7
x1
TUG-2
TU-2
VC-2
C-2
ATM:6874kbit/s
T2: 6312kbit/s
TU-12
VC-12
C-12
ATM:2144kbit/s
E1:2048kbit/s
TU-11
VC-11
C-11
ATM 1600 kbit/s

T1: 1544kbit/s
x3
Frame
Pointer processing
Aliingning
Multiplexing
POH addition
Tributary mapping
SI)
(AN
x4
Container
Group
43/
63
S T M -1
A U G
V C -n
C -n
+ AU
+ HO POH
(pointer)
M b i t /s
140,
34, 45
+ stuffing bits
+ overhead bits
TUG
T U -n
+ TU
(pointer)
V C -n
+L O P O H
C -n
Mbit/s
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
44/
63
Containers
autonomous
master clock
synchronized
master clock
synchronism
PDH frames
SDH container
mapping
stuffing
justification
bit oriented
2Mbit/s
MUX
8Mbit/s
mapping
stuffing
justification
byte oriented
MUX
155Mbit/s
2Mbit/s
45/
63
The container C-4

C-4
11
270
12
12
12
12
12
1 C-4 row
column 11
column 270
= CSSSSSOO
= I I I I I IJ S
: stuffing byte
I: Information bit
S: Stuffing bit
O: Overhead bit
46/
63

C -4 into a V C -4
10
1
11
270
J1
B3
C2
G1
F2
H4
F3
VC-4 Path
Overhead
(POH) is added
K3
9
N1
C4+POH=VC4
47/
63
1
STM-1
9 10
RSOH
10
270
VC-4
11
270
J1
B3
AUG
C2
G1
MSOH
F2
H4
F3
K3
POH
N1
48/
63

V=150 km/h
VC-4
155 km/h
STM-1
STM-1
VC-4
VC-4
VC-4
STM-1
49/
63

V<150 km/h
VC-4
VC-4
VC-4
VC-4
155 km/h
STM-1
STM-1
STM-1
between two frames
50/
63
The STM-1 frame
Regenerator
Section
Overhead
S T M -1
9 10
RSOH
10
270
VC-4
11
270
J1
Administrative
Unit Group
B3
C2
Multiplexer
Section
Overhead
G1
MSOH
F2
H4
F3
K3
POH
N1
51/
63

STM-1
1
270
9 10
RSOH
10
VC-4
11
270
J1
B3
C2
G1
MSOH
F2
H4
Z3
Z4
POH
Z5
Composition
2Mbit/s
34Mbit/s
140Mbit/s
1 VC4
3 VC3
21 VC12 + 2 VC3
21
42 VC12 + 1 VC3
42
63 VC12
63
52/
63
The STM-N frames

0
1
2
3
x4
0123
4
5
6
7
x4
4567
x4
8
9
A
B
x4
89AB
C
D
E
F
x4
CDEF
direct multiplexing
x16
0123456789ABCDEF
0123456789ABCDEF
Frame
Short Id.
STM-1
STM-4
155.520 x 4 = 622.080 kbit/s 622 Mbit/s
STM-16
622.080 x 4 = 2.488.320 kbit/s 2,5 Gbit/s
STM-64
2.488.320 x 4 = 9.953.280 kbit/s 10 Gbit/s
53/
63
J0 A2 A2 A2 A1 A1 A1
A1 A1
A1 A2
A2 A2 J0

125s

sinchronization
125s
54/
63
45Mbit/s
SDH
45 Mbit/s
Section

TUG-3
TU-3
VC-3
x3
34
+ TU
pointer
STM-1
+ SOH
AUG
+ AU
pointer
VC-n
C-3
+ LO POH
+ stuffing bits
+ overhead bits
+ HO POH

56/
63

1 1 1
25
1 1 1
25
Y I
1 1 1
Z I
25
I
Public Network
X = SSC I I I I I
Y = CCSSSSSS
I: Information bit
S: Stuffing bit
O: Overhead bit
Z = CCSSOOSJ
C-3
3
45Mbit/s
86
C-3
VC-3
57/
63
2Mbit/s
VC-3
2
1
(85 columnas)
86
J1
C-3
B3
C2
G1
F2
VC-3
H4
F3
K3
9
N1
C -3
TU-3

58/
63
VC-3
T U -3
2
H1
H2
H3
86
J1
x1
B3
C2
G1
TU-3
F2
H4
F3
Pointer bytes
K3
9
N1
V C -3
TUG-3
59/
63
TU-3
T U G -3
1
1
86
H1
H2
J1
H3
B3
x1
C2
TUG-3
G1
F2
R
H4
x3
F3
9
K3
N1
VC-4
60/
63
11
1
12
13
270
14
TUG-3
J1
B3
x3
C2
G1
F2 R
byte interleaving
3 TUG-3
VC-4
H4
F3
K3
9
( 3 x 86 = 258 columns )
N1
AU-4
stuffing bytes
61/
63
STM-1
9 10
RSOH
10
VC-4
11
VC-4
270
270
J1
B3
C2
G1
MSOH
AU-4
F2
H4
F3
K3
N1
POH
STM-1
62/
63
VC-4
9 10
STM-1
270
RSOH
AU-4
AUG
MSOH
STM-1
63/
63

PDH limitations

fourth hierarchy)


byte oriented

rest of the world


2Mbit/s with CRC4
2/
63

small companies.

definition

Advanced management

multimedia
3/
63
bytes vs. bits
frame 1
125 s
0
frame 2
125 s
1 byte
n 0
rate =
8 bits
12510-6seg.
= 64Kbit/s
4/
63
SDH objectives (i)
between equipments

speed tributaries

service

management

networks
fault tolerance
5/
63
6/
63
services
Internet
Frame Relay
RTB
ATM
GSM
transport network
SDH
transmission media
cable/fiber/radio
7/
63
SDH architecture
client
server
Section
inputs
Function of
outputs
connectivity
and overheads
SDH architecture
9/
63
SDH architecture
10/
63
network connection
Client layer
digitalization
codification
Server layer
add/drop
overheads
path

SDH architecture
11/
63
Reference points
Network connection
Layer Adaptation
Layer Adaptation
AP
AP
Layer Termination
Network connection
Layer Termination
Subnetwork
link
TCP
CP
CP
TCP
CP
CP
SDH architecture
12/
63
Connectivity
Client Path
Client layer
Server layer
AP
AP
Network Connection
Link Connection
Subnetwork
Connection
Subnetwork
Connection
TCP
TCP
CP
CP
CP
CP
Server Path
TCP
to multipoint
SDH architecture
13/
63
2 Mbit/s circuit
2 Mbit/s level
VC12 level
DXC
DXC
Subnetwork
Subnetwork
connection
VC12 level path
connection
VC4 level
Layer Adaptation
Layer Termination
VC4 level path

STM level
Layer Adaptation
Layer Termination
STM-1 section
transmission media
SDH architecture
14/
63

client connection
Layer Adaptation
Layer Adaptation
trail
AP
TCP
CP
CP
CP
TCP
CP
Maintenance)
SDH architecture
15/
63

NNI
NNI
NNI
NNI
Tributaries
Tributaries
Tributaries
MUX
sinc.
Media :
PDH
ATM
MUX
sinc.
CXC
DIGITAL CONNETION
fiber
wireless
MUX
sinc.
Media :
fiber
wireless
MUX
sinc.
ACCESS
PDH
ATM
MUX
sinc.
MUX
sinc.
Tributaries
SDH architecture
16/
63
Reference model
IP
Frame
RTB ISDN Relay
IP
ATM
ATM
Frame
Relay ISDN RTB
interchange unit
paths
sections
SDH frame
VC-12
low order VC-12
low order VC-12
high order VC-4
VC-4
high order VC-4
seccin
multiplexing
de multiplexin
section
MSOH
seccin
regeneration
de regeneracin
section
RSOH
physical interface
STM-1
physical interface
NNI
SDH architecture
17/
63
Section
Regenerators (REG)
STM-N
REG
STM-N
SDH architecture
19/
63
2M
8M
STM-1
L O -P T E
34M
H O -P T E
SDH
MUX
STM-N
45M
140M
Overhead management
SDH architecture
20/
63
STM-N
SDH
MUX
STM-M
M >N
STM-N

4 x STM-1 = STM4
4 x STM-4 = STM16
4 x STM-16 = STM64
SDH architecture
21/
63
West
East
STM-M
STM-M
STM-N, PDH
SDH architecture
22/
63
STM-N
STM-N
STM-N
STM-N
SDH architecture
23/
63
MUX
2M
34M
LPT
HPT
MUX
STM-1 SDH
MUX
REG
STM-N MUX
MUX STM-N
SDH STM-1
MUX
2M
HPT
LPT
34M
45M
45M
140M
140M
SDH architecture
24/
63
Ring topology
back up ring
ADM
ADM
ADM
tributary
active ring
tributary
ADM
SDH architecture
25/
63

E
A
B
C
Star PDH network
C
SDH Network
SDH architecture
26/
63
Transport design
National Backbone
STM-16
Primary Network
STM-4
Access Network
STM-1 or PDH
SDH architecture
27/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
28/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
29/
63

LTMUX
LO HO
MUX
REG
REG
SECT
DXC
REG
SECT
REG
REG
SECT
ADM
REG
SECT
LTMUX
HO LO
REG
REG
SECT
REG
SECT
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
30/
63
Original signal
Regenerated signal
REG
REG
ADM
attenuation
Regenerator
Multiplexer
noise
distortion
Regenerator
SDH architecture
31/
63
Transport Services
2 Mbit/s PSTN
2 Mbit/s
34 Mbit/s
34 Mbit/s
ADM
ADM
ADM
ADM
ADM
A
DM
STM-16
STM-1
DXC
STM-1
ADM
ADM
STM-1,4
STM-1
ADM
ADM
2 Mbit/s
34 Mbit/s
140 Mbit/s
C
irc
ui
t
ADM
ADM
Internet
STM-4
LTMUX
140 Mbit/s
ADM
ADM
ADM
ADM
155 Mbit/s
ISDN
LTMUX
ATM
ATM
2 Mbit/s
GSM
SDH architecture
32/
63
Security
Section
Security services
strategies:
diversification
restoration
protection
SDH architecture
34/
63
Diversification
route 1 (50% C1-C2)
C1
C2
D
route 2 (50% C1-C2)
SDH architecture
35/
63
Restoration
A
(5,2)
(4,2)
(7,0)
(6,0)
(4,5)
(3,4)
(7,7)
(5,2)
(11,3)

alternative route
SDH architecture
36/
63
Protection (i)
SDH path protection

SDH architecture
37/
63
MUX
1+1
MUX
high priority
service (S)
protection (P)
MUX
MUX
low priority
1:1
1:N
MUX
MUX
SDH architecture
38/
63

A circuit in bakup
B circuit
protection ring
service ring
B circuit
ADM
ADM
ADM
ADM
ADM
A circuit
ADM
A circuit
B circuit
A circuit in bakup
B circuit
SDH architecture
39/
63


protection services
service circuits
ADM
ADM
ADM
service circuits

protection services
SDH architecture
40/
63


circuito A
en back up
A circuit
ADM
ADM
ADM
ADM
AD
M
ADM
circuito A
circuito A
en back up
SDH architecture
41/
63

STM-1
AUG
VC-n
C-n
+ AU
+ HO POH
(pointer)
Mbit/s
140,
33 44 ,, 44 55
+ stuffing bits
+ overhead bits
TUG
TU-n
+ TU
VC-n
+LO POH
C-n
M
Mbbiitt//ss
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
Section

10 Gbit/s
STM-64
2,5 Gbit/s
STM-16
622 Mbit/s
STM-4
155 Mbit/s
x1
AUG16
x4
x1
AUG16
x4
x1
AUG4
x1
x1
x4
x1 AUG
STM-1
x1
AU416c
VC416c
AU44c
VC44c
AU-4
VC-4
x1
C416c
x1
C-44c
x1
C-4
ATM:149760 kbit/s
E4: 139264kbit/s
C-3
ATM:48384kbit/s
T3:44736kbit/s
E3: 34368 kbit/s
x3
SI)
( AN
51 Mbit/s
x1
STM-0
x1
TUG-3
x3
AU-3
TU-3
VC-3
(ANSI)
VC-3
x7
(AN
SI)
x7
x1
TUG-2
TU-2
VC-2
C-2
ATM:6874kbit/s
T2: 6312kbit/s
TU-12
VC-12
C-12
ATM:2144kbit/s
E1:2048kbit/s
TU-11
VC-11
C-11
ATM 1600 kbit/s

T1: 1544kbit/s
x3
Frame
Pointer processing
Aliingning
Multiplexing
POH addition
Tributary mapping
SI)
(AN
x4
Container
Group
43/
63
S T M -1
A U G
V C -n
C -n
+ AU
+ HO POH
(pointer)
M b i t /s
140,
34, 45
+ stuffing bits
+ overhead bits
TUG
T U -n
+ TU
(pointer)
V C -n
+L O P O H
C -n
Mbit/s
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
44/
63
Containers
autonomous
master clock
synchronized
master clock
synchronism
PDH frames
SDH container
mapping
stuffing
justification
bit oriented
2Mbit/s
MUX
8Mbit/s
mapping
stuffing
justification
byte oriented
MUX
155Mbit/s
2Mbit/s
45/
63
The container C-4

C-4
11
270
12
12
12
12
12
1 C-4 row
column 11
column 270
= CSSSSSOO
= I I I I I IJ S
: stuffing byte
I: Information bit
S: Stuffing bit
O: Overhead bit
46/
63

C -4 into a V C -4
10
1
11
270
J1
B3
C2
G1
F2
H4
F3
VC-4 Path
Overhead
(POH) is added
K3
9
N1
C4+POH=VC4
47/
63
1
STM-1
9 10
RSOH
10
270
VC-4
11
270
J1
B3
AUG
C2
G1
MSOH
F2
H4
F3
K3
POH
N1
48/
63

V=150 km/h
VC-4
155 km/h
STM-1
STM-1
VC-4
VC-4
VC-4
STM-1
49/
63

V<150 km/h
VC-4
VC-4
VC-4
VC-4
155 km/h
STM-1
STM-1
STM-1
between two frames
50/
63
The STM-1 frame
Regenerator
Section
Overhead
S T M -1
9 10
RSOH
10
270
VC-4
11
270
J1
Administrative
Unit Group
B3
C2
Multiplexer
Section
Overhead
G1
MSOH
F2
H4
F3
K3
POH
N1
51/
63

STM-1
1
270
9 10
RSOH
10
VC-4
11
270
J1
B3
C2
G1
MSOH
F2
H4
Z3
Z4
POH
Z5
Composition
2Mbit/s
34Mbit/s
140Mbit/s
1 VC4
3 VC3
21 VC12 + 2 VC3
21
42 VC12 + 1 VC3
42
63 VC12
63
52/
63
The STM-N frames

0
1
2
3
x4
0123
4
5
6
7
x4
4567
x4
8
9
A
B
x4
89AB
C
D
E
F
x4
CDEF
direct multiplexing
x16
0123456789ABCDEF
0123456789ABCDEF
Frame
Short Id.
STM-1
STM-4
155.520 x 4 = 622.080 kbit/s 622 Mbit/s
STM-16
622.080 x 4 = 2.488.320 kbit/s 2,5 Gbit/s
STM-64
2.488.320 x 4 = 9.953.280 kbit/s 10 Gbit/s
53/
63
J0 A2 A2 A2 A1 A1 A1
A1 A1
A1 A2
A2 A2 J0

125s

sinchronization
125s
54/
63
45Mbit/s
SDH
45 Mbit/s
Section

TUG-3
TU-3
VC-3
x3
34
+ TU
pointer
STM-1
+ SOH
AUG
+ AU
pointer
VC-n
C-3
+ LO POH
+ stuffing bits
+ overhead bits
+ HO POH

56/
63

1 1 1
25
1 1 1
25
Y I
1 1 1
Z I
25
I
Public Network
X = SSC I I I I I
Y = CCSSSSSS
I: Information bit
S: Stuffing bit
O: Overhead bit
Z = CCSSOOSJ
C-3
3
45Mbit/s
86
C-3
VC-3
57/
63
2Mbit/s
VC-3
2
1
(85 columnas)
86
J1
C-3
B3
C2
G1
F2
VC-3
H4
F3
K3
9
N1
C -3
TU-3

58/
63
VC-3
T U -3
2
H1
H2
H3
86
J1
x1
B3
C2
G1
TU-3
F2
H4
F3
Pointer bytes
K3
9
N1
V C -3
TUG-3
59/
63
TU-3
T U G -3
1
1
86
H1
H2
J1
H3
B3
x1
C2
TUG-3
G1
F2
R
H4
x3
F3
9
K3
N1
VC-4
60/
63
11
1
12
13
270
14
TUG-3
J1
B3
x3
C2
G1
F2 R
byte interleaving
3 TUG-3
VC-4
H4
F3
K3
9
( 3 x 86 = 258 columns )
N1
AU-4
stuffing bytes
61/
63
STM-1
9 10
RSOH
10
VC-4
11
VC-4
270
270
J1
B3
C2
G1
MSOH
AU-4
F2
H4
F3
K3
N1
POH
STM-1
62/
63
VC-4
9 10
STM-1
270
RSOH
AU-4
AUG
MSOH
STM-1
63/
63

PDH limitations

fourth hierarchy)


byte oriented

rest of the world


2Mbit/s with CRC4
2/
63

small companies.

definition

Advanced management

multimedia
3/
63
bytes vs. bits
frame 1
125 s
0
frame 2
125 s
1 byte
n 0
rate =
8 bits
12510-6seg.
= 64Kbit/s
4/
63
SDH objectives (i)
between equipments

speed tributaries

service

management

networks
fault tolerance
5/
63
6/
63
services
Internet
Frame Relay
RTB
ATM
GSM
transport network
SDH
transmission media
cable/fiber/radio
7/
63
SDH architecture
client
server
Section
inputs
Function of
outputs
connectivity
and overheads
SDH architecture
9/
63
SDH architecture
10/
63
network connection
Client layer
digitalization
codification
Server layer
add/drop
overheads
path

SDH architecture
11/
63
Reference points
Network connection
Layer Adaptation
Layer Adaptation
AP
AP
Layer Termination
Network connection
Layer Termination
Subnetwork
link
TCP
CP
CP
TCP
CP
CP
SDH architecture
12/
63
Connectivity
Client Path
Client layer
Server layer
AP
AP
Network Connection
Link Connection
Subnetwork
Connection
Subnetwork
Connection
TCP
TCP
CP
CP
CP
CP
Server Path
TCP
to multipoint
SDH architecture
13/
63
2 Mbit/s circuit
2 Mbit/s level
VC12 level
DXC
DXC
Subnetwork
Subnetwork
connection
VC12 level path
connection
VC4 level
Layer Adaptation
Layer Termination
VC4 level path

STM level
Layer Adaptation
Layer Termination
STM-1 section
transmission media
SDH architecture
14/
63

client connection
Layer Adaptation
Layer Adaptation
trail
AP
TCP
CP
CP
CP
TCP
CP
Maintenance)
SDH architecture
15/
63

NNI
NNI
NNI
NNI
Tributaries
Tributaries
Tributaries
MUX
sinc.
Media :
PDH
ATM
MUX
sinc.
CXC
DIGITAL CONNETION
fiber
wireless
MUX
sinc.
Media :
fiber
wireless
MUX
sinc.
ACCESS
PDH
ATM
MUX
sinc.
MUX
sinc.
Tributaries
SDH architecture
16/
63
Reference model
IP
Frame
RTB ISDN Relay
IP
ATM
ATM
Frame
Relay ISDN RTB
interchange unit
paths
sections
SDH frame
VC-12
low order VC-12
low order VC-12
high order VC-4
VC-4
high order VC-4
seccin
multiplexing
de multiplexin
section
MSOH
seccin
regeneration
de regeneracin
section
RSOH
physical interface
STM-1
physical interface
NNI
SDH architecture
17/
63
Section
Regenerators (REG)
STM-N
REG
STM-N
SDH architecture
19/
63
2M
8M
STM-1
L O -P T E
34M
H O -P T E
SDH
MUX
STM-N
45M
140M
Overhead management
SDH architecture
20/
63
STM-N
SDH
MUX
STM-M
M >N
STM-N

4 x STM-1 = STM4
4 x STM-4 = STM16
4 x STM-16 = STM64
SDH architecture
21/
63
West
East
STM-M
STM-M
STM-N, PDH
SDH architecture
22/
63
STM-N
STM-N
STM-N
STM-N
SDH architecture
23/
63
MUX
2M
34M
LPT
HPT
MUX
STM-1 SDH
MUX
REG
STM-N MUX
MUX STM-N
SDH STM-1
MUX
2M
HPT
LPT
34M
45M
45M
140M
140M
SDH architecture
24/
63
Ring topology
back up ring
ADM
ADM
ADM
tributary
active ring
tributary
ADM
SDH architecture
25/
63

E
A
B
C
Star PDH network
C
SDH Network
SDH architecture
26/
63
Transport design
National Backbone
STM-16
Primary Network
STM-4
Access Network
STM-1 or PDH
SDH architecture
27/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
28/
63

LTMUX
LO HO
MUX
REG
DXC
REG
ADM
REG
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
LTMUX
HO LO
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
29/
63

LTMUX
LO HO
MUX
REG
REG
SECT
DXC
REG
SECT
REG
REG
SECT
ADM
REG
SECT
LTMUX
HO LO
REG
REG
SECT
REG
SECT
MULTIPLEXING
MULTIPLEXING
MULTIPLEXING
SECTION
SECTION
SECTION
HIGH ORDER PATH

LOW ORDER PATH
SDH architecture
30/
63
Original signal
Regenerated signal
REG
REG
ADM
attenuation
Regenerator
Multiplexer
noise
distortion
Regenerator
SDH architecture
31/
63
Transport Services
2 Mbit/s PSTN
2 Mbit/s
34 Mbit/s
34 Mbit/s
ADM
ADM
ADM
ADM
ADM
A
DM
STM-16
STM-1
DXC
STM-1
ADM
ADM
STM-1,4
STM-1
ADM
ADM
2 Mbit/s
34 Mbit/s
140 Mbit/s
C
irc
ui
t
ADM
ADM
Internet
STM-4
LTMUX
140 Mbit/s
ADM
ADM
ADM
ADM
155 Mbit/s
ISDN
LTMUX
ATM
ATM
2 Mbit/s
GSM
SDH architecture
32/
63
Security
Section
Security services
strategies:
diversification
restoration
protection
SDH architecture
34/
63
Diversification
route 1 (50% C1-C2)
C1
C2
D
route 2 (50% C1-C2)
SDH architecture
35/
63
Restoration
A
(5,2)
(4,2)
(7,0)
(6,0)
(4,5)
(3,4)
(7,7)
(5,2)
(11,3)

alternative route
SDH architecture
36/
63
Protection (i)
SDH path protection

SDH architecture
37/
63
MUX
1+1
MUX
high priority
service (S)
protection (P)
MUX
MUX
low priority
1:1
1:N
MUX
MUX
SDH architecture
38/
63

A circuit in bakup
B circuit
protection ring
service ring
B circuit
ADM
ADM
ADM
ADM
ADM
A circuit
ADM
A circuit
B circuit
A circuit in bakup
B circuit
SDH architecture
39/
63


protection services
service circuits
ADM
ADM
ADM
service circuits

protection services
SDH architecture
40/
63


circuito A
en back up
A circuit
ADM
ADM
ADM
ADM
AD
M
ADM
circuito A
circuito A
en back up
SDH architecture
41/
63

STM-1
AUG
VC-n
C-n
+ AU
+ HO POH
(pointer)
Mbit/s
140,
33 44 ,, 44 55
+ stuffing bits
+ overhead bits
TUG
TU-n
+ TU
VC-n
+LO POH
C-n
M
Mbbiitt//ss
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
Section

10 Gbit/s
STM-64
2,5 Gbit/s
STM-16
622 Mbit/s
STM-4
155 Mbit/s
x1
AUG16
x4
x1
AUG16
x4
x1
AUG4
x1
x1
x4
x1 AUG
STM-1
x1
AU416c
VC416c
AU44c
VC44c
AU-4
VC-4
x1
C416c
x1
C-44c
x1
C-4
ATM:149760 kbit/s
E4: 139264kbit/s
C-3
ATM:48384kbit/s
T3:44736kbit/s
E3: 34368 kbit/s
x3
SI)
( AN
51 Mbit/s
x1
STM-0
x1
TUG-3
x3
AU-3
TU-3
VC-3
(ANSI)
VC-3
x7
(AN
SI)
x7
x1
TUG-2
TU-2
VC-2
C-2
ATM:6874kbit/s
T2: 6312kbit/s
TU-12
VC-12
C-12
ATM:2144kbit/s
E1:2048kbit/s
TU-11
VC-11
C-11
ATM 1600 kbit/s

T1: 1544kbit/s
x3
Frame
Pointer processing
Aliingning
Multiplexing
POH addition
Tributary mapping
SI)
(AN
x4
Container
Group
43/
63
S T M -1
A U G
V C -n
C -n
+ AU
+ HO POH
(pointer)
M b i t /s
140,
34, 45
+ stuffing bits
+ overhead bits
TUG
T U -n
+ TU
(pointer)
V C -n
+L O P O H
C -n
Mbit/s
1.5, 2,
6, 8,
34, 45
+ stuffing bits
+ overhead bits
44/
63
Containers
autonomous
master clock
synchronized
master clock
synchronism
PDH frames
SDH container
mapping
stuffing
justification
bit oriented
2Mbit/s
MUX
8Mbit/s
mapping
stuffing
justification
byte oriented
MUX
155Mbit/s
2Mbit/s
45/
63
The container C-4

C-4
11
270
12
12
12
12
12
1 C-4 row
column 11
column 270
= CSSSSSOO
= I I I I I IJ S
: stuffing byte
I: Information bit
S: Stuffing bit
O: Overhead bit
46/
63

C -4 into a V C -4
10
1
11
270
J1
B3
C2
G1
F2
H4
F3
VC-4 Path
Overhead
(POH) is added
K3
9
N1
C4+POH=VC4
47/
63
1
STM-1
9 10
RSOH
10
270
VC-4
11
270
J1
B3
AUG
C2
G1
MSOH
F2
H4
F3
K3
POH
N1
48/
63

V=150 km/h
VC-4
155 km/h
STM-1
STM-1
VC-4
VC-4
VC-4
STM-1
49/
63

V<150 km/h
VC-4
VC-4
VC-4
VC-4
155 km/h
STM-1
STM-1
STM-1
between two frames
50/
63
The STM-1 frame
Regenerator
Section
Overhead
S T M -1
9 10
RSOH
10
270
VC-4
11
270
J1
Administrative
Unit Group
B3
C2
Multiplexer
Section
Overhead
G1
MSOH
F2
H4
F3
K3
POH
N1
51/
63

STM-1
1
270
9 10
RSOH
10
VC-4
11
270
J1
B3
C2
G1
MSOH
F2
H4
Z3
Z4
POH
Z5
Composition
2Mbit/s
34Mbit/s
140Mbit/s
1 VC4
3 VC3
21 VC12 + 2 VC3
21
42 VC12 + 1 VC3
42
63 VC12
63
52/
63
The STM-N frames

0
1
2
3
x4
0123
4
5
6
7
x4
4567
x4
8
9
A
B
x4
89AB
C
D
E
F
x4
CDEF
direct multiplexing
x16
0123456789ABCDEF
0123456789ABCDEF
Frame
Short Id.
STM-1
STM-4
155.520 x 4 = 622.080 kbit/s 622 Mbit/s
STM-16
622.080 x 4 = 2.488.320 kbit/s 2,5 Gbit/s
STM-64
2.488.320 x 4 = 9.953.280 kbit/s 10 Gbit/s
53/
63
J0 A2 A2 A2 A1 A1 A1
A1 A1
A1 A2
A2 A2 J0

125s

sinchronization
125s
54/
63
45Mbit/s
SDH
45 Mbit/s
Section

TUG-3
TU-3
VC-3
x3
34
+ TU
pointer
STM-1
+ SOH
AUG
+ AU
pointer
VC-n
C-3
+ LO POH
+ stuffing bits
+ overhead bits
+ HO POH

56/
63

1 1 1
25
1 1 1
25
Y I
1 1 1
Z I
25
I
Public Network
X = SSC I I I I I
Y = CCSSSSSS
I: Information bit
S: Stuffing bit
O: Overhead bit
Z = CCSSOOSJ
C-3
3
45Mbit/s
86
C-3
VC-3
57/
63
2Mbit/s
VC-3
2
1
(85 columnas)
86
J1
C-3
B3
C2
G1
F2
VC-3
H4
F3
K3
9
N1
C -3
TU-3

58/
63
VC-3
T U -3
2
H1
H2
H3
86
J1
x1
B3
C2
G1
TU-3
F2
H4
F3
Pointer bytes
K3
9
N1
V C -3
TUG-3
59/
63
TU-3
T U G -3
1
1
86
H1
H2
J1
H3
B3
x1
C2
TUG-3
G1
F2
R
H4
x3
F3
9
K3
N1
VC-4
60/
63
11
1
12
13
270
14
TUG-3
J1
B3
x3
C2
G1
F2 R
byte interleaving
3 TUG-3
VC-4
H4
F3
K3
9
( 3 x 86 = 258 columns )
N1
AU-4
stuffing bytes
61/
63
STM-1
9 10
RSOH
10
VC-4
11
VC-4
270
270
J1
B3
C2
G1
MSOH
AU-4
F2
H4
F3
K3
N1
POH
STM-1
62/
63
VC-4
9 10
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The Synchronous Digital Hierarchy (SDH) : - I Part

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The Synchronous Digital Hierarchy (SDH) : - I Part

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The Synchronous Digital Hierarchy (SDH)

the multiplexing is bit oriented (second, third and

it is not possible to execute direct add&drop of

poor monitoring capacity

lack of management standards and short space to

lack of optic standards

no mechanisms to manage the quality, just for

Causes to define SDH

The Antitrust law at US followed by Bell break into

Was necessary to interconnect new PTTs: SONET

B-ISDN specification to integrate any traffic: SDH

Requirement for having

bytes vs. bits

An important consequence is that in SDH 1 byte represents a 64 Kbit/s channel

SDH objectives (i)

scalability in transmission speeds until 0 Gbit/s

direct add&drop for low

capabilities for new control channels supervision, maintenance &

support to fit any application: audio, video, voice

remote and centralized

easy migration from PDH

SDH is a flexible architecture

SDH has a reference model

It is an standard universally accepted

SDH is highly compatible with SONET

very efficient to manage circuits

fast circuit definition from a centralized point

advanced facilities for quality monitoring

multiplexing, transport, routing, management, reliability

SDH provides an efficient, reliable and flexible transport for circuits

The network is a function of the connectivity

The model considers the network as a connectivity function

it has a set of input/output interfaces

there are function to match requirement with capacities

nodes are the network elements: switches, multiplexers, and regenerators

Layer Adaptation: unifies the information format using

one to connect terminal points (paths)

one to connect routes (sections)

The connection monitors the client information integrity

VC12 level path

VC4 level path

Transference integrity: trails

The source delivers information which is adapted: digitalization, codification,...

Network Node Interface (NNI) location

NNI (Network Node Interface) are the connection between subnetworks:

low order VC-12

low order VC-12

high order VC-4

high order VC-4

Network elements and topologies

attenuation: reduction of strength of the signal per distance. Amplification

Line Termination Multiplexors (LTMUX)

Mux/Demux of plesiochronous circuits to/from STM-N frames

Mux/Demux of STM-N signals in/from STM-M

Does not modify the contents of transported information

Multiplexion of four SDH signals:

Add & Drop Multiplexer (ADM)

Put / get PDH circuits in/from STM-N frames

configures SDH rings topologies

can provide the network with fault tolerant capacities

Digital Cross-Connect (DXC)

Switchs STM signals as well as add&drop funcionalities.

implements all the network element capacities