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Sigma-delta (Σ-Δ) modulation techniques have moved into mainstream applications in signal processing and have found many
practical uses in areas such as high-resolution A/D, D/A conversions, voice communication, and software radio. Σ-Δ modulators
produce a single, or few bits output resulting in hardware saving and thus making them suitable for implementation in very
large scale integration (VLSI) circuits. To reduce quantization noise produced, higher-order modulators such as multiloop and
multistage architectures are commonly used. The quantization noise behavior of higher-order Σ-Δ modulators is well understood.
Based on these quantization noise characteristics, various demodulator architectures, such as sinc filter, optimal FIR filter, and
Laguerre filter are reported in literature. In this paper, theory and design of an efficient Kalman recursive demodulator filter is
shown. Hardware implementation of Kalman lowpass filter, using field programmable gate array (FPGA), is explained. The FPGA
synthesis results from Kalman filter design are compared with previous designs for sinc filter, optimum FIR filter, and Laguerre
filter.
Let x(n) be a slowly varying input signal to a Σ-Δ modu- second-order multiloop (DSM2) and third-order multistage
lator. For simplicity, consider the case where x(n) is a dc sig- (MASH3) architectures, coefficients of the N-tap optimum
nal given by x(n) = ρ. (This assumption is usually warranted FIR filter are given by
due to the oversampling of Σ-Δ modulator.) The power spec-
trum of the output, y(n), of a Σ-Δ modulator is given by [11]
30 n + 1 n+2 N −n
DSM2 : c(n) =
(2 sin π f )2m N N +1 N +2 N +3
Sy y ( f ) = + ρ2 δ( f ), (1)
3 N +1−n
× , (7)
N +4
where f denotes the frequency, normalized by the sampling
140 n 3 n 3
frequency, and m is the order of the modulator. The second MASH3 : c(n) = 1− ; 0 ≤ n < N.
term of the right-hand side of (1) is the signal term while the N N N
first term represents the quantization noise resulting from The number of filter taps, N, is usually selected to be the same
the modulator. The objective is to design a digital filter, H(z), as the oversampling ratio (OSR) of the Σ-Δ modulator.
such that the filtered quantization noise power at the output
of the demodulator is minimized, that is,
2.3. Optimal Laguerre IIR filter
0.5
j2π f 2
Γ = min H e (2 sin π f )2m df (2) To minimize quantization noise, it is described in [17, 18]
−0.5
that the filter transfer function, H(z), can be expressed using
subject to the following truncated Laguerre series:
M −1
H e j2π f | f =0 = 1. (3)
HL (z) = γk φk (z), (8)
k=0
The linear constraint on the minimization problem of (3)
is imposed to pass dc signal unattenuated through the filter. where γk is the Laguerre series coefficients and φk (z) is the
2 The effective bandwidth of the filter is given by frequency domain Laguerre function, given by
0.5 j2π f 2 √
H e df z 1 − a2 1 − az k
fB = 2 . (4) φk (z) = ,
−0.5 H e j2π f z−a z−a (9)
f =0
− 1 ≤ a < 1, k = 0, 1, . . . , M − 1.
At the demodulator, the high-frequency noise produced by
Using (8), the minimization of noise yields
the Σ-Δ modulator is removed by using the lowpass filter,
H(z), and the input signal is recovered.
m.s.e (dB)
−80
(a)
−100
νk −120
+ −140
xk Z −1 yk + qk pk −160
1 − Z −1
+ 1 − Z −1
−180
(b) −200
0 0.5 1 1.5 2 2.5 3 3.5 4
Iteration number (log)
Figure 1: (a) Single-loop Σ-Δ modulator and (b) its linear repre-
sentation. Simulation
From theoretical equation
Figure 1(a). Here νk denotes the quantization error of the Figure 2: Output mean squared error (m.s.e) versus iteration num-
thresholder, which can be approximately represented as a ber, m = 2. Theoretical result is shown for an optimum FIR filter
white Gaussian process with variance 1/12 [20]. The follow- [19].
ing state-space relationship can be obtained for the circuit in
Figure 1(b):
4 After updating (14)-(15) for N times (where N = OSR),
xk+1 = xk , the filtered output can be taken from the value of the first el-
yk+1 = xk+1 + yk , (11) ement of the state vector Gk , that is, Gk (1), and again the
filter is initialized using the conditions in (16). This pro-
q k = y k + νk ,
cedure essentially implements lowpass filtering and down-
where sampling operations. Extension of Kalman lowpass filter for
the second-order modulator is straightforward. This could
1 be obtained by modifying (13) and (16), respectively, as
qk = pk . (12)
1 − z−1 ⎡ ⎤
1 0 0
⎢ ⎥
Based on (11), let φ and H be defined as φ = ⎣1 1 0⎦ , H = [0 0 1]T ,
1 1 1 (17)
1 0 1
φ= , H = [0 1]T . (13) βk=0 = [I]3×3 , Gk=0 = [0 0 0]T .
1 1 12
Then, the Kalman gain equation (state update) and Extension to higher-order demodulators could be easily ob-
Kalman prediction equation can be obtained as follows [21]: tained via generalization of (17).
For each update (or iteration) the filer output is taken
φβk φT H from the value of Gk (1). Figure 2 shows the filtered error as 5
Kk = , a function of the number of iterations, k of a second-order
H T φβk φT H + σ 2 (14)
modulator (m = 2) when the forgetting factor is selected as
Gk+1 = φGk + Kk qk − H T φGk ,
γ = 1. Note that the filtered error is the same as that obtained
where Gk is the state vector, given by Gk = {xk , yk }T and σ 2 is using the N-length optimal FIR filter defined in (7).
the quantization noise variance. Furthermore, the covariance Note here that the recursion in (14)-(15) is complete at
of the state estimation error βk (i.e., the 2 × 2 state covariance every N samples (down-sampling), and the m.s.e of Kalman
matrix) satisfies filter will be the same as that of an optimum FIR filter.
βk+1 = γ I − Kk H T φβk φT (15) 4. FULL-RATE KALMAN FILTER
with I being the identity matrix and γ being a forgetting fac- The previous section discusses the implementation of a
tor, selected as γ = 1. Note that pk is the output of the mod- down-sampled Kalman filter. However in certain applica-
ulator in Figure 1(b), and qk is obtained by integrating pk . tions, a full-rate demodulator filter would be very advan-
Taking the quantization noise variance σ 2 = 1/12, and using tageous. This means that the Σ-Δ demodulator is used at a
the initial conditions shown in (16), it is possible to update sampling frequency given by the OSR. For example, in [5], a
(14)-(15) recursively: full-rate Laguerre filter has shown to improve the noise per-
formance by approximately 13 dB. In another example [6], a
1 bandpass Σ-Δ demodulator is used to retrieve the intermedi-
βk=0 = [I]2×2 , Gk=0 = [0 0]T . (16)
12 ate frequency (IF) in a software radio system. In this case, full
4 EURASIP Journal on Applied Signal Processing
−80
and thus increases hardware cost. Noting that qk = pk , the
−100
−120
Kalman filter equations for Figure 1(b) could now be written
−140
as
−160
Gk+1 = φGk + Kk pk − H T φGk . (19)
−180
−200
0 0.5 1 1.5 2 2.5 3 3.5 4 Assuming that the steady states have been achieved, the out-
Iteration number (log) put, ok , is obtained from integrating the state vector Gk as
shown in the following:
From equation N = 512
N = 32 N = 2048
N = 128
ok = Gk (1) + Gk−1 (1). (20)
0 0
−20 −20
−40 −40
−60
Power (dB)
−60
Power (dB)
−80
−80
−100
−100
−120
−120
−140
−140
−160
−180 −160
0 5 10 15 20 25 0 5 10 15 20 25
Frequency (kHz) Frequency (kHz)
−20
OSR = 128. Figure 9 shows the spectrum of the down-
sampled demodulated output signal. The window size of FFT
−40 was 1024, and with Hann window. The SNR achieved is ap-
proximately 100 dB. The FPGA result agrees with the MAT-
Power (dB)
In
1 Opain a
Go1 x0.01276
a+b 1
b
0.005 676 269 531 25 K1 Out
Go2
K2 a+b
Cast
0.084 091 186 523 44
a b
Go3
0.445 323 944 091 8 K3
q2
x(−0.8112)
x1.798
z−1 z−1
Figure 7: FPGA design of the second-order Kalman filter using System Generator under MATLAB Simulink.
b 20
q 1
k=0 rst
Go1 0
Accumulator
Magnitude (dB)
a −20
a+b b q
b 2
rst −40
a Go2
a+b b Accumulator 1
−60
Opain 1 a
a+b b −80
a b q 3
a+b rst
b Go3 −100
a b Accumulator 2
a−b −120
a 0 5 10 15 20
(ab)
2 b Frequency (kHz)
K1
a
(ab)
3 b
K2 Figure 9: FPGA simulation showing the spectrum of demodulated
a output from the second-order down-sampled Kalman filter.
(ab)
4 b
K3
20 20
0 0
−20
Magnitude (dB)
−20
Magnitude (dB)
−40
−40
−60
−60
−80
−80
−100
−100
−120
0 5 10 15 20 −120
0 10 20 30 40 50
Frequency (kHz)
Frequency (kHz)
Kalman-filtered error signal (down-sampled)
Input signal Input signal
(a) Kalman-filtered error signal
Kalman-filtered error signal (optimized FPGA)
20
0 Figure 11: Simplified FPGA versus original full-rate Kalman.
−20
Magnitude (dB)
20
−40
0
−60
Magnitude (dB)
−20
−80
−40
−100 −60
−120 −80
0 10 20 30 40 50
Frequency (kHz) −100
−120
Input signal 0 5 10 15 20
Kalman-filtered error signal (full rate) Frequency (kHz)
(b) Kalman-filtered error signal (full-rate down-sampled)
Input signal
Figure 10: FPGA simulation showing the spectra of input versus
the filtered output error-(a) down-sampled Kalman filter, and (b) Figure 12: FPGA simulation showing the filtered error signal from
full-rate Kalman filter. full-rate Kalman filter after down-sampling.
demodulated error signal from full-rate Kalman filter after down-sampled Kalman filter, and second order full-rate filter
down-sampling by OSR = 128. The figure shows the same (described in Section 6.2). All four filter designs were imple-
SNR of approximately 100 dB as shown in Figure 10(a). Note mented using Xilinx System Generator version 2.3, Simulink,
that if one needs to achieve the 10 dB noise gain noted in Fig- and MATLAB 6.5, and synthesized using Xilinx ISE 5.1 i. The
ure 10(b), then the signal could be further lowpass filtered target FPGA was Xilinx Virtex II XC2V250-6. All the filters
before the down-sampling, using a simple filter such as an were carefully designed to make sure that a sufficient number
accumulator and dump (sinc) filter [18]. of data bits was used in the datapath; that is, full bit-growth
for arithmetic operation, up to maximum of 32 bits.
6.4. Comparison of FPGA designs for sinc filter, opti- Table 1 shows the comparison of FPGA resource usage
mum FIR filter, Laguerre filter, and Kalman filters among the five Σ-Δ filters. From the table, the total number
of gates needed for 128-tap sinc filter, 128-tap optimum FIR
In [10, 12] we have carried out FPGA designs and provided filter, 7-stage Laguerre filter, down-sampled Kalman filter,
comparison among different Σ-Δ demodulators including and full-rate Kalman filter are 15 026, 3273, 20 213, 16 523,
optimum FIR filter, optimum Laguerre filter, sinc filter, and and 10 356 gates, respectively. seven-stage Laguerre filter con-
down-sampled Kalman filter. This section compares the full- tains the highest number of multipliers and thus the high-
rate Kalman architecture design explained in previous sub- est number of look up tables (LUTs). Optimum FIR filter
sections with earlier FPGA designs. requires minimum LUTs as well as total gate count. Down-
In the experiment, comparisons are made among FPGA sampled Kalman filter and sinc filter offer approximately the
designs for 128-tap sinc filter, 128-tap optimum FIR filter, same gate count. Second-order full-rate Kalman filter offers
7-stage Laguerre filter (a = 0.906 25, M = 7), second-order the second lowest gate count.
S. S. Abeysekera and C. Charoensak 9
Table 1: Comparison of FPGA resource used in sinc filter, optimum FIR filter, Laguerre filter, down-sampled and full-rate Kalman filters.
Table 2: Comparison of maximum operating frequency of sinc, Laguerre, and Kalman filters.
Optimum Kalman filters
sinc filter Laguerre filter
FIR filter Down-sample Full-rate
Maximum clock frequency (MHz) 24.5 98.3 8.4 22.3 28.2
Note that here the optimum FIR filter is the only filter filter, and full-rate Kalman filter are 24.5 MHz, 98.3 MHz,
implemented using multiply-accumulate technique (MAC) 8.4 MHz, and 22.3 MHz, and 28.2 MHz, respectively. Note
and as a result, there is a big saving in the number of mul- again that the high operating speed of optimum FIR filter
tipliers and adders. The design requires only one multiplier is achievable only because of the reduced circuit complexity
and one adder. In other applications where a full-rate opera- using MAC architecture.
tion is needed (i.e., the filtered output is not down-sampled), From the table, it is clear that Laguerre filter is slow com-
this MAC technique could not be applied and the optimum pared to other filters. This is due to the more complicated
FIR filter FPGA would require a lot more gates. structure and much longer critical path. Down-sampled
128-tap sinc, with long 128-tap delays, needs the maxi- Kalman filter, achieved approximately the same maximum
mum number of slice flip-flops, 253. Note also that a large operating frequency as sinc filter. Full-rate Kalman filter is the
number of LUTs, 150, are used for shift registers. Down- second fastest architecture, 28.2 MHz. Taking into account
sampled Kalman filter requires very little register resources, that it operates at full sampling frequency, full-rate Kalman
that is, 150 slice flip-flops and 0 LUTs. Its resource require- filter offers the highest output signal sampling rate. For op-
ment is low when compared with the Laguerre filter. timum FIR filter, the maximum output signal sampling rate
When compared to the down-sampled Kalman filter, the after down-sampling is only 98.3/128 = 0.77 MHz.
full-rate Kalman filter requires less registers still, that is, 84 Another figure that can be used to compare the per-
slice flip-flops and 0 LUTs. Its resource requirement is thus formance of hardware architectures is the processing power
very low and higher only than that of optimum FIR filter. per unit of supplied power (measured in sample per sec-
The figure of gate count for full-rate Kalman filter, 10 356, ond per watt, Msps/W). The following power consumptions
may look much higher than that of the optimum FIR filter, were taken from Xilinx utility called XPower which provides
3273, but in practice, the price of FPGA in this small gate a postrouted estimation of power consumption. The mea-
count range is about the same. surements of dynamic power consumption shown in Table 3
In conclusion, the advantages of Kalman filter over the were based on 20 MHz operating frequency. Note that the av-
other filters are (i) the filter implementation is independent erage static power consumption of all designs is in order of
of the oversampling ratio and thus suitable for full sampling hundreds of milliwatts. Again, it is shown that optimal FIR
rate applications, (ii) the filter algorithm is simple and well filter offers the lowest power consumption due to the low cir-
structured in that it could be easily extended to higher-order cuit complexity. However, due to the fact that Kalman filter
modulators, (iii) the requirement for register components produces full-rate output, the architecture offers many folds
is minimal. All these features make Kalman filter an attrac- increase in net Msps/W, that is, the value shown in the table
tive solution for hardware implementation with programma- multiplied by OSR. In this point of view, Kalman filter offers
bility. For full-rate Kalman filter, additional advantages are the highest Msps/W.
(iv) operation at full sampling frequency without having
to down-sample the output signal, (v) reduced hardware 7. CONCLUSION
resource requirements, (vi) the filter specification such as
bandwidth can be adjusted easily and can be designed to be Σ-Δ modulation offers high resolution and simplified hard-
programmable.
Table 2 compares the maximum operating frequency of ware implementation making it suitable for various signal
the Σ-Δ filters. The maximum operating speed of sinc filter, processing applications. In this paper, theory formulation of
optimum FIR filter, Laguerre filter, down-sampled Kalman an efficient full-rate Kalman filter, suitable for Σ-Δ demod-
10 EURASIP Journal on Applied Signal Processing
Table 3: Power consumption of sinc, optimal FIR, Laguerre, and Kalman filters (at 20 MHz operating frequency).
Sinc filter Optimum FIR filter Laguerre filter Kalman filters
Dynamic power consumption at 20 MHz (mW) 3.7 0.48 5.4 1.14
Million sample per second (Msps/W) 5405 41 667 3703 17 543
ulation, is given. FPGA implementation of the full-rate re- [2] S. P. Reichhart, B. Youmans, and R. Dygert, “The software
cursive Kalman lowpass filter is compared with previous re- radio development system,” IEEE Personal Communications,
ported work on optimum FIR filter, Laguerre filter, sinc filter, vol. 6, no. 4, pp. 20–24, 1999.
and down-sampled Kalman filter. Issues on hardware opti- [3] C. Dick and F. Harris, “FPGA signal processing using sigma-
mization of full-rate Kalman filter are discussed. Resource re- delta modulation,” IEEE Signal Processing Magazine, vol. 17,
no. 1, pp. 20–35, 2000.
quirement and speed performance of Kalman filter are given
[4] S. S. Abeysekera and K. P. Padhi, “Design of multiplier free
in comparison with other filters. FIR filters using a LADF sigma-delta (Σ − Δ) modulator,” in
It has been observed in our work that, when compared to Proceedings of IEEE International Symposium on Circuits and
sinc filter and Laguerre filter, Kalman filter offers a very inter- Systems (ISCAS ’00), vol. 2, pp. 65–68, Geneva, Switzerland,
esting choice for hardware implementation of Σ-Δ lowpass May 2000.
filter. Although optimum FIR filter implemented here ex- [5] R. Schreier and M. Snelgrove, “Bandpass sigma-delta modula-
hibits a very low gate count and high operating speed, this is tion,” Electronics Letters, vol. 25, no. 23, pp. 1560–1561, 1989.
due to the application of MAC architecture. In applications [6] B.-S. Song and I. S. Lee, “A digital FM demodulator for FM,
where full sampling rate is needed, MAC technique could not TV, and wireless,” IEEE Transactions on Circuits and Systems II:
be used and the design would require a lot more gates as well Analog and Digital Signal Processing, vol. 42, no. 12, pp. 821–
as be much slower. It is noted that the use of LUTs (look 825, 1995.
[7] S. S. Abeysekera, X. Yao, and Z. Zang, “A comparison of var-
up tables) instead of the MAC architecture for multiplication
ious low-pass filter architectures for sigma-delta demodula-
would need large LUTs as well as slow downs in the opera- tors,” in Proceedings of IEEE International Symposium on Cir-
tional speed. cuits and Systems (ISCAS ’99), vol. 2, pp. 380–383, Orlando,
The gate requirement and maximum operating fre- Fla, USA, May-June 1999.
quency of the down-sampled Kalman filter are approxi- [8] K. Lin, K. Zhao, E. Chui, A. Krone, and J. Nohrden, “Digital fil-
mately the same as those of the popular sinc filter. Kalman ters for high performance audio delta-sigma analog-to-digital
filter requires minimal flip-flops for memories. This charac- and digital-to-analog conversions,” in Proceedings of 3rd Inter-
teristic makes Kalman filter attractive in applications where national Conference on Signal Processing (ICSP ’96), vol. 1, pp.
the number of delays is limited such as the case of complex 59–63, Beijing, China, October 1996.
programmable logic devices (CPLDs), or low-power designs. [9] S. S. Abeysekera and C. Charoensak, “Optimum sigma-delta
(Σ −Δ) de-modulator filter implementation via FPGA,” in Pro-
Architecture of the Kalman filter is independent of oversam-
ceedings of 14th Annual IEEE International ASIC/SOC Confer-
pling ratio and well structured that it could be easily designed ence, pp. 281–285, Arlington, Va, USA, September 2001.
to be programmable for use with different order modulators, [10] S. S. Abeysekera and C. Charoensak, “FPGA implementation
as well as the full sampling rate applications. of a sigma-delta (Σ − Δ) architecture based digital I-F stage
The full-rate Kalman filter exhibits additional and very for software radio,” in Proceedings of 15th Annual IEEE Inter-
interesting advantages over the down-sampled version. This national ASIC/SOC Conference, pp. 341–345, Rochester, NY,
includes full sampling rate operation, higher maximum op- USA, September 2002.
erating frequency, adjustable bandwidth, and saving of hard- [11] S. S. Abeysekera, X. Yao, and C. Charoensak, “Design of opti-
ware cost. This makes full-rate Kalman filter a very attractive mal and narrow-band Laguerre filters for sigma-delta demod-
choice for applications in Σ-Δ demodulation. Using FPGA ulators,” IEEE Transactions on Circuits and Systems II: Analog
for implementation of Σ-Δ demodulation allows a quick and and Digital Signal Processing, vol. 50, no. 7, pp. 368–375, 2003.
[12] S. S. Abeysekera, “Bandpass sigma-delta (Σ − Δ) architecture
easy verification of new algorithms. Although the speed and
based efficient FM demodulator for software radio,” in Pro-
performance of the designs using FPGAs is limited and of- ceedings of IEEE International Symposium on Circuits and Sys-
ten inferior to ASICs, the development time is much shorter, tems (ISCAS ’04), vol. 4, pp. 381–384, Vancouver, BC, Canada,
making FPGA more suitable in applications where there is May 2004.
the need to verify practicality of a new concept, in this case [13] J. C. Candy, “A use of double integration in sigma delta mod-
the Kalman Σ-Δ demodulator. Moreover, the newer genera- ulation,” IEEE Transactions on Communications, vol. 33, no. 3,
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sampling A-to-D and D-to-A converters with multistage noise
shaping modulators,” IEEE Transactions on Acoustics, Speech,
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[15] W. Chou, P. W. Wong, and R. M. Gray, “Multistage sigma-
[1] J. P. Cummings, “Software radios for airborne platforms,”
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S. S. Abeysekera and C. Charoensak 11
[16] P. W. Wong and R. M. Gray, “FIR filters with sigma-delta mod- Composition Comments
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[17] S. S. Abeysekera and X. Yao, “Optimum Laguerre filter de-
sign technique for sigma-delta demodulators,” in Proceedings 1. We replaced “Low-Pass” with “Lowpass” in the title.
of IEEE International Symposium on Circuits and Systems (IS- Please check.
CAS ’00), vol. 5, pp. 405–408, Geneva, Switzerland, May 2000.
[18] S. S. Abeysekera and X. Yao, “A single stage decimator archi- 2. We changed the highlighted fraction from slashed to
tecture for sigma-delta demodulators using Laguerre filters,” stacked. Please check similar highlighted cases through-
in Proceedings of IEEE International Symposium on Circuits and out.
Systems (ISCAS ’01), vol. 2, pp. 789–792, Sydney, NSW, Aus-
tralia, May 2001. 3. We replaced “k small normal math” with the high-
[19] S. S. Abeysekera, “Stability analysis of sigma-delta modula-
lighted “K large normal math” for the sake of consistency.
tors using a non-linear technique,” in Proceedings of 4th Inter-
national Symposium on Signal Processing and Its Applications Please check.
(ISSPA ’96), vol. 1, pp. 242–245, Gold Coast, Australia, August
1996. 4. We redraw the frames of Figures 2, 3, 4, 5, 6, 7, 8, 9, 10,
[20] S. S. Abeysekera, “Kalman filter architectures for sigma-delta 11, and 12. Please check.
demodulators,” in Proceedings of IEEE International Sympo-
sium on Intelligent Signal Processing and Communication Sys- 5. We rephrased the highlighted part. Please check similar
tems (ISPACS ’02), Kaohsiung, Taiwan, November 2002. highlighted cases throughout.
[21] S. Haykin, Adaptive Filter Theory, Prentice-Hall, Englewood
Cliffs, NJ, USA, 1996.
6. Please note that Figures 3, 4, 5, 6, and 11 must be
[22] Xilinx Inc., System Generator v2.3 for the MathWorks
Simulink: Quick Start Guide, July 2002. printed in color. IF not, please send a grey-scale version for
the sake of clarity.
Saman S. Abeysekera received the B.S. En- 7. We changed “section II subsection C” to the high-
gineering (first class honors) degree from lighted “Section 2.3.” Please check similar highlighted
the University of Peradeniya, Sri Lanka, in cases throughout.
1978 and the Ph.D. degree in electrical en-
gineering from the University of Queens-
land, Brisbane, Australia, in 1989. From 8. Please specify to which section are you referring to.
1989 to 1997, he worked at the Centre
for Water Research, University of Western 9. Please specify to which section are you referring to.
Australia and Australian Telecommunica-
tion Research Institute, Curtin University of 10. Comment on ref. [1]: We added the author and added
Technology, Western Australia. He is presently an Associate Profes- “for airborne platforms” to the title. Please check.
sor in the School of Electrical and Electronic Engineering, Nanyang
Technological University, Singapore. He is also a Program Direc-
11. Comment on ref. [15]: We changed the 1st author.
tor in the Centre for Signal Processing. His research interests in-
clude time frequency domain analysis of audio and electrocardio-
Please check.
graphic signals, synchronization aspects of SONET/SDH systems,
blind signal processing, applications of sigma-delta modulators, 12. Regarding the photos of your paper, please note that
and wideband signal processing. Dr. C. Charoensak photo is low in resolution. I would appre-
ciate your sending another photo with 600 dpi at least as
Charayaphan Charoensak received the jpg/tiff with minimum compression/maximum quality.
M.A.Sc. and Ph.D. degrees in electrical en-
gineering from the Technical University of
Nova Scotia, Halifax, Nova Scotia, Canada,
in 1989 and 1993, respectively. He is cur-
12 rently a Senior Manager at Philips Electron-
ics Singapore, in the division of Flat Display
Technology. His main works include digital
signal processing for video picture improve-
ment and advanced system architecture for
flat panel television .