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INTRODUCTION TO ADVANCED
SEMICONDUCTOR MEMORIES
MEMORIES
40%
250,000
30%
200,00U
"o
Q
15
</>
150,000
20%
2
a.
100,000
2
10%
50,000
0
MOS Memory Market ($M)
Non-Memory IC Market ($M)
Memory % of Total IC Market
96
97
98
99
00
01*
02*
03*
04* 05*
36,019 29,335 22,994 32,288 49,112
51,646 56,541 70,958 94,541 132,007
78,923 90,198 86,078 97,930 126,551 135,969 148,512 172,396 207,430 262,172
31% . 25% 21% 25% 28%
28%
28% 29% 31% 33%
0%
Year
Figure 1.1
larger VLSI chips, and as stand-alone memory for specific system applications.
A major improvement in DRAM evolution has been the switch from
three-transistor (3T) designs to one-transistor (IT) cell design, enabling production of 4- to 16-Mb density chips that use advanced 3-D trench capacitor
and stacked capacitor cell structure. Currently, 64-Mb to 1-Gb DRAM chips
are in production, and multigigabit density chips are being developed. The
technical advances in multimegabit DRAMs have resulted in greater demand
for application-specific products such as the pseudostatic DRAM (PSRAM),
which uses dynamic storage cells but contains all refresh logic on-chip that
enables it to function similarly to an SRAM. Video DRAMs (VDRAMs) have
been produced for use as the multiport graphic buffers. Some other examples
of high-speed DRAM innovative architectures are synchronous DRAMs
(SDRAMs), cache DRAMs (CDRAMs), and Rambus DRAMs (RDRAMs).
Nonvolatile memories (NVMs) have also experienced tremendous growth
since the introduction in 1970 of a floating polysilicon gate-based erasable
program read-only memory (EPROM), in which hot electrons are injected into
the floating gate and removed either by ultraviolet internal photoemission
or by Fowler-Nordheim tunneling. The EPROMs (also referred to as the
UVEPROMs) are erased by removing them from the target system and
exposing them to ultraviolet light. An alternative to EPROM (or UVEPROM)
has been the development of electrically erasable PROMs (EEPROMs), which
offer in-circuit programming flexibility. Several variations of this technology
include metal-nitride-oxide-semiconductor (MNOS), silicon-oxide-nitrideoxide-semiconductor (SONOS), floating gate tunneling oxide (FLOTOX),
and textured polysilicon. The FLOTOX is most commonly used EEPROM
technology. An interesting NVM architecture is the nonvolatile SRAM, a
combination of EEPROM and SRAM in which each SRAM has a corresponding "shadow" EEPROM cell.
Flash memories based on EPROM or EEPROM technologies are devices
for which contents of all memory array cells can be erased simultaneously,
unlike the EEPROMs that have select transistors incorporated in each cell to
allow for the individual byte erasure. Therefore, the flash memories can be
made roughly two or three times smaller than the floating gate EEPROM cells.
Flash memories are available in 8- to 512-Mb densities as production devices,
and even higher densities in development.
DRAMs are currently (and predicted to be in the future) the largest memory
segment in terms of dollar sales. After DRAMs the SRAMs and flash markets
represent the next two largest memory segments. In year 2000, the flash
memory market surpassed the SRAM market and became the second-largest
memory market segment. Both DRAM and flash market shares are expected
to continue growing through 2005, although flash memory at a much faster
pace. The remaining memory segments are predicted to remain stable.
(a)
QTSRAM ($M)
E3 Flash ($M)
80,000
60,000
2
o
r
O
40,000 -
|
2
20,000 -
DRAM SM)
SRAM <$M)
Flash <SM>
Other Memory ($M)
96
97
98
25,132
4.745
2.611
3,531
19,796
3.842
2,702
2.993
14,011
3,895
2,493
2,595
00
20,715
4.662
4,561
2.350
29,176
6.291
10.446
or
27.300
7,075
14,400
2.871
02"
03*
04"
05"
29,935
7.676
16,235
2,695
38,615
8.9O4
20,760
2,659
53,290
10.6B5
27.845
2.721
77.270
ia356
38,600
2,701
Year
(b)
SRAM
HUM
2%
10%
All Other
2%
EPROM
1%
SRAM
13%
Flash
29%
DRAM
59%
DRAM
60%
Figure 1.2 (a) Comparison of different MOS memory technologies market share, (b) Percentages
for each MOS memory technology market for year 2000 and predicted values for year 2005 [2].
and BIST techniques have been developed such as the scan-path-based flagscan register (FLSR) and the random-pattern-based circular self-test path
(CSTP). Advanced BIST architectures have been implemented to allow parallel
testing with on-chip test circuits. The current generation megabit memory
chips include spare row and columns (redundancies) in the memory array to
compensate for the fault cells. In addtion, to improve the memory chip yield,
techniques such as built-in self-diagnosis (BISD) and built-in self-repair (BISR)
are used.
The errors in semiconductor memories can be broadly categorized as the
hard failures caused permanent physical damage to the device and soft errors
caused by alpha particles or the ionizing dose radiation environments. The
most commonly used error-correcting codes (ECC) that are used to correct
hard and soft errors are the single-error correction and double-error detection
(SEC-DED) codes, also referred to as the Hamming Codes. Multimegabit
DRAM chips have been developed that use redundant word and bit lines in
conjunction with ECC to produce optimized fault tolerance effect. To recover
from the soft errors (transient effects), memory scrubbing techniques are often
used, which are based upon the probabilistic or deterministic models. These
techniques can be used to calculate the reliability rate R(t) and mean time to
failure (MTTF) of the memory system.
Semiconductor Memories reviewed general reliability issues for semiconductor devices such as the memories, RAM failure modes and mechanisms,
nonvolatile memory reliability, reliability modeling and failure rate prediction,
design for reliability, and reliability test structures [1]. The general reliability
issues pertaining to semiconductor devices in bipolar and MOS technologies
are applicable to memories also. In addition, there are special reliability issues
and failure modes, which are of special concern for the RAMs. These issues
include gate oxide reliability defects, hot-carrier degradation, the DRAM
capacitor charge-storage and data-retention properties, and DRAM soft-error
failures. The memory gate dielectric integrity and reliability are affected by all
processes involved in the gate oxide growth.
The reduced MOS transistor geometries from scaling of the memory devices
has made them more susceptible to hot-carrier degradation effects. Nonvolatile
memories, just like volatile memories, are also susceptible to some specific
failure mechanisms. In the floating gate technologies such as the EPROM and
EEPROMs, data retention characteristics and number of write/erase cycles
without degradation (endurance) are the most critical reliability concerns.
Reliability failure modeling is the key to the failure rate prediction, and there
are many statistical distributions that are used to model various reliability
parameters. The method of accelerated stress aging for semiconductor devices
such as memories is commonly used to ensure long-term reliability. An
approach commonly used by the memory manufacturers in conjunction with
the end-of-line product testing has been the use of reliability test structures and
process (or yield) monitors incorporated at the wafer level and "drop-in" test
sites on the chip. The purpose of reliability testing is to quantify the expected
failure of a device at various points in its life cycle.
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RAM
Conventional
DRAM
DRAM
FPM
DRAM
High-spaed DRAM
Synchronous-type
DRAM
DDR SDRAM
DirectRDRAM
Next-generation
High-speed DRAM
SynchLink DRAM
Graphics
Memory
SRAM
Conventional
Dual Port
Graphics Buffer
Synchronous
type
SGRAM
DDR SGRAM
SSRAM
DDR SSRAM
Conventional
SRAM
Synchronous-type
SRAM
Figure 1.3
A flow chart of various types of some commonly used high speed RAMs.
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various NOR cell structures and NAND flash cells. An EEPROM technology
that was developed earlier is the metal-nitride-oxide-silicon (MNOS) and
(poly)silicon-oxide-nitride-oxide-semiconductor (SONOS), and floatinggate tunnel oxide (FLOTOX) cells that were briefly discussed in Semiconductor
Memories [1].
Chapter 5 in the present book reviews the latest developments in EEPROM/flash cells and array structures. Four major flash architectures are
reviewed: NOR, NAND, DINOR, and AND along with representative memory devices currently available from vendors, such as a 32-Mb simultaneous
read/write NOR-based flash memory from Advanced Microdevices, Inc.
(AMD), 32-Mb dual-plane flash memory from Intel Corp., 256-Mb UltraNAND flash memory from Samsung, Inc., and 16-Mb DINOR flash memory
from Mitsubishi, Inc. The new developments include a proposed 3.3-V, 16-Mb
nonvolatile memory using NAND flash architecture, which has operation
virtually identical to that of a DRAM.
The latest development in flash memory is the concept of multilevel (ML)
that refers to the storage of more than one bit per cell, in order to increase the
device density and reduce the cost per bit. In principle, the ML concept can be
coupled with various types of memory architectures, such as the NOR and
NAND to implement a 2-bit/cell scheme. However, there are several ML
programming, sensing, and reliability issues that need to be addressed in each
of these architectures. An example of this approach is Intel's multilevel
NOR-based architecture, which is currently capable of storing two bits per
memory cell but may be scalable to three bits per cell. An overview of Intel's
3-V StrataFlash NOR-based memory, a proposed multilevel 64-Mb NAND
flash memory design, a 512-Mb NAND flash memory from Toshiba Corp., and
a 256-Mb multilevel cell AND flash memory from Hitachi Corp. is provided.
Semiconductor Memories reviewed general reliability issues such as the gate
oxide breakdown, electromigration, hot-carrier degradation, metallization corrosion, and so on, which are generic among various semiconductor technologies [1]. However, there are a number of failure modes and mechanisms that
are specific to the EPROM/EEPROMs such as data-retention characteristics
and the number of write/erase cycles without degradation (endurance), which
are critical reliability concerns. The major issues concerning yield and reliability of flash memories are flash overerase, program/read disturbs, program/read
endurance, flash data retention failures, and flash hot carrier reliability effects.
In general, the reliability of MLMs is more critical than that of the
conventional two-level logic (1 bit/cell) because of the requirements for a larger
threshold (Vt) window (to keep adequate spacing among the stored levels)
and/or reduced spacing between the adjacent levels (to limit the increase in Vt
window). Chapter 5 in the present book reviews the major reliability and yield
issues for flash memories.
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FRAM is a RAM-based device that uses the ferroelectric (FE) effect as the
charge storage mechanism, based on the ability of material to store an
electrical polarization in the absence of an applied electric field; that is, a
ferroelectric memory stores data within a crystalline structure. In FRAM, the
memory readout is a destructive operation, and therefore each read access is
accompanied by a precharge operation that restores the memory state. A write
operation is very similar to a read operation and requires no system overhead.
Some of the most widely used FE materials are PZT (PbZr^Tii _A-O3) and SBT
(SrBi 2 Ta 2 O 9 ).
An example of the FRAM is 256-Kb device that uses a two-transistor,
two-capacitor (2T2C) memory cell design from Ramtron Corp. The new
developments include one-transistor, one-capacitor (1T1C) memory cell design
suitable for 1-Mb and higher-density designs. A proposed DRAM-like FeRAM
cell array, referred to as the depletion FeRAM (DeFeRAM), and a 4-Mb
FRAM with 1T1C cell design are discussed. A new chain FRAM (CFRAM)
architecture has been proposed, which can realize 4F 2 size memory cell and
random access; and when 16 cells are connected in series, the chip size can be
reduced to 63% to that of a conventional FRAM.
Metal-ferroelectric semiconductor (MFS) devices that are considered candidates for high-density NVM applications are based on the principle that
information can be stored as a polarization direction rather than as a charge
on a capacitor. Ferroelectric films used as memory storage elements have
significant reliability concerns, such as the aging/fatigue effects, thermal stability, effects of electric fields, and so on. These are briefly reviewed in Chapter 5.
As the processor performance has increased from several hundred megahertz to 1 GHz and beyond, idle wait time in relatively slower DRAMs
has increased, leading to a memory-processor performance gap. The fastest
growing trend in advanced semiconductor memory is the embedded memories designs and applications. Memory technology for embedded memory
has a wide variation, ranging from small blocks of ROMs, hundreds of
kilobytes for the cache RAMs, high density (several megabits) of DRAMs, and
small to medium density nonvolatile memory blocks of EEPROMs and flash
memories. Embedded SRAM is one of the most frequently used memory
embedded in logic chips. Chapter 6 discusses embedded memory designs and
applications.
Currently, the two major approaches for embedded memories development
are fabricating memory in a logic-based process versus fabricating logic in a
DRAM-based process technology. A recent trend driving the integration of
DRAM into logic chips is the need to reduce power by eliminating the need
for off-chip drivers and improving performance. Another advantage is noise
reduction. A key advantage of the embedded memory approach is the higher
packaging density and board space savings, which is a desirable feature for
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REFERENCES
1. Ashok K. Sharma, Semiconductor Memories: Technology, Testing and Reliability,
IEEE Press, New York, 1997.
2. B. McClean, B. Matas, and T. Yancey, The McClean Report: 2001 Edition, IC
Insights, 2001.