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Bridging faults:

1. Bridging faults are type of structural faults that occur in electronic


circuits , when there is exist a connection between two conducting line
where it should not have. These faults cause malfunction of the entire
circuit.
2. There may be single and multiple bridging faults in a circuit.
3. Bridging fault create either a feed back path between input and output or
non-feed back (input bridging) path

4. These faults generates a new wired AND logic or wired OR logic between
any two lines where fault occurs
5. Possible bridging faults in VLSI circuits are:
a. If there is a connection between
i. Output-output
. ex: between metals ,between outputs
lof different gates
ii. Input to output. Ex: between input and output gates
iii. Input to input. Ex: between inputs and outputs of different
gates
iv. Vdd and VSS. Ex: between power supply and ground
v. Input to VDD. Ex: between input and power supply
vi. Input to VSS. Ex: between input and ground
vii. Output to VDD. Ex: between output and power supply
viii. Output to VSS . ex: between output and ground
Detection of bridging faults:
1. Bridging faults can be detected by applying opposite logics to the
given two signals in the circuits.
Example:

In the above there is bridging fault between two input line A and B.
The fault free model for the above model will be:
A
0
0
1
1

B
0
1
0
1

A
1
1
0
0

B
1
0
1
0

Fault model:
A
0
0
0
1

B
0
0
0
1

A
1
1
1
0

B
1
1
1
0

From this we can clearly understand that circuit behaves differently when
is there is opposite logic functions at the input of the circuits. This similar
method can be applied to the OR logic model and all. It will ensure for
themultiple bridge faults but all the single faults can be easily detected.
2. IDDQ testing is also another method used to find out the bridging
faults in the circuit. This test used when there is VDD,VSS vs input
and output faults.

Delay faults:
In vlsi circuit every conducting material will have certain resistance and in
turn capacitance. By considering time constant of those combination we
assume a particular amount of delay will be provided by every component
in the chip design. This delay may cause to generate faults in the circuits
which are called as delay faults. They are divided into following models.
1. Transistor delay
2. Gate delay
3. Path delay
4. Segment delay
5. Path delay
Detection:
1. Transistor faults are due to slow to fast rise of inputs in
the CMOC circuit. They are detected by applying two
input vectors, one Is used to as input and other is a
test vector which is used to find out the faults in the
circuit. These are done by using fault detection models
for every stuck at zero and one faults using proper
tools
2. To detect gate delay faults, one must know the size of
gate and delay provided by that in the circuit.
Otherwise we will consider the delay and apply tools to
detect the faults in the circuit. One advantage of this
gate delay is that the delay is linear in the entire
circuit.
3. In the path delay finding out the critical path delay in
the entire circuit and calculating the delays provided
by other components y using superposition principles
will give us detection
4. Segmentation model is between transistor and path
delay model.

Here we consider the size of the segment which


produces maximum delay and that will be considered
as the faulty segment. It is precise since the number of
segments existed in design is less than number of
transistors and path
5. In line delay model the largest fault sensitizing path
will be detected and it is used to detected fault on the
small size by using longest line which is similar to
transistor and gate delay model. It can detect only
single fault occur between any two line

References:
1.

VLSI Testing: Digital and Mixed Analogue/digital Techniques


By Stanley Leonard Hurst

2. A Designers Guide to Built-In Self-Test


By Charles E. Stroud
3. Built in self test by V.D.Agarwal
4. Wikipedia
5. Frequency enhancement of digital VLSI test systems,L.ackner and M.R.Barber
6. Essesntialo of electronic testing for digital,memory and mixed signal Vlsi
processing by M.L.Bushnell

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