Modeling and Digital Control Implementation of the Bidirectional

Zeta-Sepic DC-DC Converter

Adriano, Ruseler, INEP, Brazil, ruseler@inep.ufsc.br
Ivo, Barbi, INEP, Brazil, ivobarbi@inep.ufsc.br

Abstract
This paper deals with the current control of the bidirectional Zeta-Sepic DC-DC converter. By
means of the state average method, the transfer function representing the ratio of the input
inductor current to the duty-cycle is deducted and validated by simulation. A digital controller
is proposed, analyzed, designed and simulated. The proposed digital controller is tested on a
50 V input, 50 V / 500 W output and 50 kHz switching frequency, using a Texas Instruments
DSP TMS 320F2812. The experimental results obtained in the laboratory agree well with the
results predicted by theoretical analysis.

1.

Introduction

In meaning of power flow, the DC-DC converters can be classified as unidirectional or bidirectional, which can be subdivided as isolated and non-isolated. Bidirectional converter topologies mainly derive from the basics ones. For a buck and boost non-isolated derived topology, sources may have different voltage levels, since in a power flow direction the converter operates as a step-down and in other direction as a step-up. This paper presents a
non-isolated converter that operates in step-up and step-down mode no matter in what direction the power is flowing. The basic employed topologies are the Zeta and SEPIC converters. The junction of these two converters forms the Zeta-Sepic bidirectional converter, which
in addiction is a natural isolated topology [1], [2], [3].
A complete analysis for the Zeta-Sepic converter operating in the continuous conduction
mode (CCM) is accomplished, beginning from converter circuit explanation to a practical validation of the theoretical study. The state-space averaging technique was used to model the
converter resulting in a compact form to represent its dynamics, being suitable for use in
software designed to handle matrices as MATLAB. Since the output voltage is a voltage
source, the bidirectional fourth-order of SEPIC or Zeta converter, are in this case reduced to
a third order dynamics system.

2.

The Zeta-Sepic Bidirectional Converter Topology

The Zeta-Sepic Bidirectional converter is obtained by the composition of two classical converters: Zeta and SEPIC. Note that the active converter, depends on what direction the power flows. For example, if power flows from source Va to Vb, the Zeta converter is active.
ILb
Cab

ZetaMode

RVa

RCab Cab
RLa

Lb

RLb

SEPICMode

Sa

Va

Sa

La

Sb

Vb

Va

La

Sb

Fig. 1. Operation Modes (left) and the converter conductions losses considered (right).

Vb

On other hand, power flowing from source Vb to Va the SEPIC converter is active. For convenience this two situations are called Zeta Mode and SEPIC Mode respectively, as show in
Fig.1.

2.1.

Operation principle and circuit states

The converter operates in continuous conduction mode (CCM). Using complementary commands there are two equivalent circuits within one switching period. Fig. 2 shows the two
circuit states. Circuit state A occurs when MOSFET Sa is conducting and circuit state B
when MOSFET Sb is conducting.
Cab

Sa
Va

La

Cab

Lb
Sa

Vb

Sb

Va

La

Lb

Vb

Sb

Fig. 2. Circuit state A (left) and circuit state B (right).

2.2.

Main waveforms of the bidirectional Zeta-Sepic converter

The Zeta-Sepic converter waveforms are similar to the ones for the Zeta when in Zeta mode
and to the SEPIC converter, when in SEPIC mode, as shown in Fig. 3.
ZetaMode
SEPICMode
v La|Lb
VLa|Lb,max
VLa|Lb,min
ILa|Lb,max
ILa|Lb,min
ILb,min
ILb,max
ILa,max
ILa,min
ILab,max
ILab,min
ILab,min
ILab,max

i La|Lb
iCab

iSa

iSb
v Sa

Va + Vb

v Sb

Va + Vb

Sa
Sb

1 D

1 D

1 D

1 D

Fig. 3. Main waveforms of the Zeta-Sepic bidirectional converter operating in Zeta Mode (left) and in
SEPIC Mode (right).

3.

State Space Averaged Model

In order to find the converter dynamics as well as the quiescent operation point, the ZetaSepic converter was modeled using the state space averaging technique. The converter operates in continuous conduction mode having two equivalent circuits defined by the switch
Sa position. The initial step in the state space modeling is writing the differential equations
that describes the converter in each circuit state. The system (2.1) represents the differential
equations for the State A, including the conduction losses.

 diLa

0 dt (RVa + RLa )
RVa
0 iLa 1 0
La 0
v
diLb
0 Lb

0
=
RVa
(RVa + RCab + RLb ) 1 iLb + 1 1 a

v
dt

0 0 Cab
0
1
0 vCab 0 0 b
u
dvCab
K
Aa
x
Ba
dt

(2.1)

Similary, the differential equations are represented in matrix form (2.2) for the State B.
diLa

0 dt (RCab + RLa )
0
1 iLa 0 0
La 0
v
diLb

0 Lb

(2.2)
0
0
=
RLb 0 iLb + 0 1 a

vb
dt

0 0 Cab
1
0
0 vCab 0 0
u
dvCab
K
Ab
x
Bb
dt
Let the x vector be the state variables, which is the inductor currents and capacitor voltage.
The input u vector contains the independent inputs of the system such as the sources Va
and Vb.
The next step is to average each state equation matrix by the duty of the corresponding circuit state, for example A = Aad + Ab(1 d ) being d the duty cycle. The system equation (2.3)
represents the steps for linearization and ac perturb about a quiescent point.
d
K

d x

Ts

=A x

dt
y Ts = C x

Ts

+ Bu u

Ts

+E u

Ts

x
u

Ts

Ts

= D + d

Ts

= X + x

Ts

= U + u

Ts

= Y + y

d ( X + x )
= A( X + x ) + Bu(U + u )
dt
Y + y = C( X + x ) + E(U + u )

(2.3)

Defining the output vector y equal to the state vector x, the C matrix is known. For the case
in study, the E matrix is zero, so the working system for modeling the converter is shown in
(2.4).

d ( X + x )
K
= Aa(D + d ) + Ab 1 (D + d )
dt

3.1.

X + x + Ba(D + d ) + Bb 1 (D + d )

Bu

}(

U +u

}(

(2.4)

Steady state analysis, the DC model

A steady state analysis is required in order to specify the converter components and implement a prototype. Developing equation (2.4) and collecting the DC terms, the system (2.5) is
archived. Note that to obtain the steady state for the converter including or not the nonidealities the only change is achived in matrix Aa and Ab. This characteristic justifies the use
of state averaging technique to model the converter.
ILa
V
0 = [ Aa D + Ab(1 D )] ILb + [Ba D + Bb(1 D )] a
Vb
VCab

(2.5)

The system unknown variables for the converter operating in Zeta mode are D, ILa and VCab,
and, for the converter operating in SEPIC mode are D, ILb and VCab.
As an example, the static gain can be obtained solving (2.5) for the ideal converter resulting
in equation (2.6) which is identical to the static gain of the Zeta and to the SEPIC converters.

Vb
D
=
=G
Va 1 D

3.2.

(2.6)

Modeling the converter dynamics

The converter dynamics model is obtained by manipulating equation (2.4) and selecting the
first-order terms. Applying the Laplace transform and manipulating the system to relate the
state variables against the converter duty cycle drives to equation (2.7).

x( s )
H(s) =
= K s [ Aa D + Ab(1 D) ]

d ( s )

( Aa Ab) X + (Ba Bb)U

Bd

(2.7)

The matrixes A and Bd are:

(D 1) RCab D RVa RLa
A =
D RVa

1 D

D RVa
D ( RVa + RCab ) RLb
D

1 + D
D , Bd =
0

( RCab RVa ) ILa RVa ILb + VCab + Va

RVa ILa ( RVa + RLa ) ILb + VCab + Va

ILa ILb

(2.8)

3.3.

Converter non-idealities

As an attempt to simplify the controller design, the converter conduction losses are considered. The MOSFET is considered to be ideal because it operates as a diode or as a switch
depending on the current direction, avoiding unnecessary complexity modeling. Therefore,
the system (2.7) remains the same in Zeta and SEPIC modes. Table 3.1 lists the prototype
parameters values and Table 3.2 lists the steady state values necessaries to obtain the converter model.
Table 3.1 Converter parameters and conTable 3.2 Steady state operation points of
the Zeta-Sepic bidirectional converter with
duction resistances.
components resistances.
Parameter
Value
Resistance
La
Lb
Cab
Va
Vb

0,17
0,197
0,003
0,2
0,2

347 H
233 H
58 F
48 V
48 V

Parameter
ILa
ILb
VCab
D

Zeta Mode
12,6537 A
10,4167 A
47,9010 V
0,5485

SEPIC Mode
-10,4167 A
-12,4356 A
47,3210 V
0,4558

Applying the parameters listed in Table 3.1 and Table 3.2, for the converter operating in
Zeta mode, in equations (2.7) and (2.8), the transfer function (2.9) is obtained, relating the
inductor Lb current with the duty cycle.
GiLb,zeta (s ) =

3.917e005s 2 7.43e008s + 7.788e012

(2.9)
s 3 + 2133s 2 + 3.331e007s + 4.302e010
For the converter operating in SEPIC mode, the transfer function relates the inductor Lb current with the duty cycle as in (2.10).
GiLb,sepic (s ) =

4.289e005s 2 + 9.83e008s + 1.242e013

(2.10)
s 3 + 2000s 2 + 3.093e007s + 3.957e010
The system modeling validation is accomplished by the ac sweep analysis in PSIM software.
The start frequency is 12.5 Hz and end frequency of 12.5 kHz, with 51 data points and excitation source amplitude of 0.005. The PSIM generate data are imported into MATLAB and

Frequency:

Gate A

RVa

La

vtri

RLb
Vb

Gate A
GateB

iLb ( s) / d ( s )

Step: 1e-007
TotalTime : 0.02

iLb ( s) / d ( s)

SEPIC Mode

vsin
D

Sb

GateB

Va

Phase (Deg)

Lb

Phase (Deg)

RLa

RCab

Magnitude (dB)

Cab

iLb ( s) / d ( s )

Zeta Mode

Amplitude: 0.005
No. Points: 51
ac iLb

12.5Hz -12.5kHz
Sa

Magnitude (dB)

displayed together with bode diagrams of the modeled system. As shown in Fig. 4 the perfect data fit validate the converter ac small signal model.

iLb ( s) / d ( s )

Fig. 4. Setup used to validate the dynamics model with losses and the comparison with simulated
point against the equated model.

iLb ( s ) / d ( s)

iLb ( s ) / d ( s)

iLb ( s) / d ( s)

Imaginary Axis

Magnitude (dB)
PPhase (deg)

iLb ( s ) / d ( s )

Imagunary Axis

Phase (deg)

Magnitude (dB)

A Bode diagram plot and pole-zero map comparison is made in Fig. 5. When the nonidealities are considered, the pole-zero map is shifted to the left, turning the current response more damped as confirmed in the Bode Diagram.

Fig. 5. Comparisons between ideal converter model and non-ideal converter model operating in Zeta
mode (left) and in SEPIC Mode (right).

4.

Current Controller implementation

A closed loop control is needed to drive power from one source to another. The diagram in
Fig. 6 show the block diagram for the current control loop and delimits the analog and digital
signals. The proportional integral controller is chosen to obtain a zero error to step in reference.

S1

du
u

iLb,ref (z)
G

Ci Lb ( z )

GADC

d (s )

d (z)

e( z )

DigitalControler

GPWM

fa

GiLb (s )

iLb (s )

CondI (s )

Fig. 6. Classic controller topology (left) and detailed structure (right).

To interface the analog signal from the current sensor with the ADC module, an auxiliary circuit is required. This circuit consists of an MSB low pass filter [4] at 5 kHz, following by an
inverter with offset of 1.5 V and a limiter voltage CI (0-3V). For a proper controlling design,
the dynamic of the conditioner circuit also must be regarded, as is described by (3.1).
2.408e007
CondI (s ) = 2
(3.1)
s + 1.692e004s + 1.605e008

4.1.

Fixed point considerations (DSP TMS320F2812)

A fixed point DSP was used to implement the digital controller. In order to optimize its numeric performance, fixed point arithmetic and C28x IQMath Library were studied [5]. As
the ADC module has 12 bits [6], the Q format for the ADC variables was chosen to be Q12.
A symmetric PWM waveform is obtained by configuring timer 1 to count in a continuous
up/down mode. The timer period register (TxPR) determines the switching frequency and the
maximum value of the compare register, limiting the resolution of the PWM module by
log2(TxPR) bits [7]. The compare register value represents the duty cycle, value in a Q format chosen as the ceiled value of the PWM resolution (Q11). The DSP clock frequency is
150 MHz and the switching frequency is 50 kHz. The ADC module gain for control loop and
the PWM module gain can be evaluated as be the equations shown in (3.2).
QnPWM
QnPWM
11
(212 1) 1
4095
1
2
2
2
GADC =
=

,
PWMGAIN =
=
=
= 1.365
3
TxPR
fDSPclock 1500
212 3 4096 3
round

2fSwitching
(3.2)

4.2.

Proportional integral current controller design

The PI controller was designed in MATLABs toolbox for the converter operating in Zeta
Mode with the set point in 10A, by locating the zero at 1.8 kHz and adjusting the gain to obtain a first order response. For digital implementation, the controller is discretized with Tustin
method and sampling frequency of two times the switching frequency. The obtained PI controller is written in (3.3).
0,002693 z - 0,002403
CiLb,zeta ( z ) =
(3.3)
z-1
The step response for the converter operating in both modes is shown in Fig. 7. Using the
same controller in SEPIC mode results in a similar behavior and proves that the same controller can be used to control the converter in both power flows directions.

iLb,ref iLb
Amplitude

Amplitude

iLb,ref iLb

Fig. 7. Reference step response for the converter operating in Zeta mode (left) and in SEPIC Mode
(right) for the current controller designed in Zeta mode.

5.

Numeric Simulation Results

A simulation of the circuit with including parameters cited above has been carried out in the
software PSIM. The simulated result shown in Fig. 8 is in accordance with the expected step
response illustrated in Fig. 7.
Gadc

RLb

RLa

RVa

Gate A La

GateB

Lb

Vb

Ci Lb ( z )

iLb,ref

iLb,ref iLb

RVb
Sb

Va

iLb,dsp

ZOH

Cab RCab

Gate A

Vtri

iLb,ref

GateB

Digital Value

Sa

Ampres (A)

CondI (s )

iLb,dsp
Fig. 8. Full featured simulation structure of the implemented converter (left) and simulation result for
the converter switching between operation modes (right).

6.

Experimental Results

A prototype was implemented in order to validate all theoretical study. The converter was
designed to handle 500 W of nominal power. Batteries where used as voltage sources bidirectional in current. For validating the converter operation modes, the current reference was
set to put the converter in Zeta and in SEPIC Modes. The current in inductance Lb is measured and the results are showed in Fig. 9. The waveforms obtained in the laboratory agree
with the results predicted by the theoretical analysis presented in Fig. 8.
The converter exhibits a nonlinear behavior near zero. This phenomenon is caused by the
drivers dead time. For minimizing this effect, the dead time was set to a minimal value adjusted experimentally in the laboratory.

iLb

iLb

Fig. 9. Experimental results for the converter switching from Zeta mode to SEPIC mode (left) and
switching from SEPIC mode to Zeta mode (right).

7.

Conclusion

This paper has presented a completed analysis of the bidirectional Zeta-Sepic DC-DC converter. A brief analysis shows that this converter behaves as a classic Zeta converter when
power flows from source Va to source Vb and as a SEPIC converter when power flow
changes. The state-space averaging technique was used to model the converter dynamics
and to find the steady state operation point, without increase of modeling complexity when
the conduction losses were considered.
Modeling the converter with non-idealities brings advantages for the controller design mainly
because the dumping effect introduced by the consideration of the converter resistances.
The obtained experimental results validate the theoretical study previous achieved. The outline shown in this paper can be used to model, control, simulate and implement almost all
DC-DC converters operating in continuous conduction mode.
This converter is a possible candidate to substitute the conventional bidirectional buck-boost
converter in some practical applications, such as renewable power supply systems and electric vehicles.

8.
[1]
[2]
[3]
[4]
[5]
[6]
[7]

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