In the recent nanotechnology, the variation in the gate propagation delay is the big concern. This paper proposes the new model for gate delay propagation using the Statistical Static Timing Analysis and the results of it are compared with another modelling called as Monte-Carlo analysis. The proposed model uses Statistical analysis to find accurate propagation delay of the logic gates with reduced simulation time for 16nm technology.

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In the recent nanotechnology, the variation in the gate propagation delay is the big concern. This paper proposes the new model for gate delay propagation using the Statistical Static Timing Analysis and the results of it are compared with another modelling called as Monte-Carlo analysis. The proposed model uses Statistical analysis to find accurate propagation delay of the logic gates with reduced simulation time for 16nm technology.

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Volume: 3 Issue: 5

ISSN: 2321-8169

2862 - 2865

_______________________________________________________________________________________________

Bhushan Malkapurkar

Anil Wanare

Dr. DYPSOET, Lohgaon acronyms acceptable

Pune, India

e-mail: bhushan.malkapurkar@dypic.in

Dr. DYPSOE, Lohgaon acronyms acceptable

Pune, India

e-mail: anil.wanare@dypic.in

AbstractIn the recent nanotechnology, the variation in the gate propagation delay is the big concern. This paper proposes the

new model for gate delay propagation using the Statistical Static Timing Analysis and the results of it are compared with another

modelling called as Monte-Carlo analysis. The proposed model uses Statistical analysis to find accurate propagation delay of the

logic gates with reduced simulation time for 16nm technology.

Keywords-SSTA;Variations;Technology

__________________________________________________*****_________________________________________________

I.

INTRODUCTION

As CMOS technology scaling down to nanometre, process

variations have been increased. The process variations change

the transistor dimensions like length, width, thickness of oxide

and threshold voltage. This results in variations in timing

parameters which makes difficulty in performance count of

digital circuits.

So it is necessary to characterize and control the parameter

fluctuations to improve the performance. To calculate more

accurate timing parameters and performance of the circuits,

statistical static timing analysis (SSTA) is an important

technique [1]. SSTA analyses circuit propagation delays

statistically by considering process variations.[1][3]

performance of the system.

another chip shown in Fig 1. The variations within chip called

intra die variation and the variations from chip to chip, wafer

to wafer and one lot of wafers to another lot of wafers are

called inter die variations. Intra die variations are caused by

process gradients over the wafer during manufacturing. Global

or random parameter variations are divided into two types

such as extrinsic variations and intrinsic variations.

Fluctuations of effective channel length, doping concentrations

and oxide thickness caused by extrinsic equipment are

considered to be extrinsic variations. The intrinsic variations

are due to random fluctuations in channel dopant number,

oxide charge, interface charge, etc.

In the conventional methods static timing analysis (STA) is

used, which uses corner based analysis shown in Figure 2.[1]

The corner values show best case and worst case delay of the

possible process variations are not considered. This method

does not consider the process variations. With a case based

STA analysis, it is therefore difficult to calculate actual timing

distribution of a circuit. To overcome this difficulty SSTA is

one of the new concepts. SSTA models process parameters

such as gate length, width, oxide thickness and doping

concentration as random variables and propagates these

random variables through the circuit in topological fashion to

calculate the performance of the system similar to the

propagation in its deterministic counterpart.

As mention earlier conventional method is not

accurate method. To overcome this, various methods are

available to give accurate timing analysis. One of the most

usable method that is Monte Carlo analysis, but this is very

time consuming method. To overcome this researcher finds

various algorithms, but some of them consider only one or few

process parameter variation to decide operating speed. In this

study, we propose a new algorithm that will consider all

process variations and gives accurate operating speed of the

circuit.

A. VLSI Circuit design specifications

To design high speed VLSI circuit, the major three

specifications are important first the operating speed of the

circuit, second the power dissipation of the circuit and third

area required to fabricate a chip. Out of these three the first

one i.e. operating speed of the circuit is most important and

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Volume: 3 Issue: 5

ISSN: 2321-8169

2862 - 2865

_______________________________________________________________________________________________

challenging one. To decide the operating speed of the circuit

the designer must know all timing constraint of the circuit like

propagation delay of each logic gate, clock to Q time, setup

and hold time of the flip flop and interconnect delay. By using

these timing constraints designer finds longest path delay.

According to that the speed of the system will decide. If the

circuit is small then this may not be a tough task. But for

millions transistor integration this will be very tough and

challenging task.[8]

II.

We will consider the two NOT gates connected in series

i.e. first NOT gate is driving second NOT gate.

by default it is 0V.

TOXE is oxide thickness and the value is 2nm.

EV is exponent for mobility degradation and the value is

1.67m2/V for N channel and 1.0 m2/V for P channel.

Vgsteff is a smoothing function to ensure continuity between

subthreshold region and linear region.

Vgsteff =max { Voff [(n Vt ln(1+ exp (Vgs Vth))/ (n

Vt)]/[1+n exp(-(Vgs Vth))/ (n Vt)]} - -Eq. 9[4]

N= 1+N Factor

N Factor is nearly close to 1. So N is close to 2.

S is a surface potential.

S = 0.4 + Vt ln(NDEP/ni)

Eq. (10)

NDEP is a Channel doping concentration for zero body

bias.

Ni is an intrinsic carrier concentration for silicon.

From the above equations we can say that the propagation

delay varies with the length (L), width (W), oxide thickness

(TOXE) and dopants (ni) in the MOSFET. Now in statistical

static timing analysis, we will consider the varying values of

these variables and calculate the propagation delay. Whereas

the value of oxide thickness and dopants are having very less

variation so we can neglect those variations and can consider

them as constant. In this we will vary length from minimum

value to maximum value keeping other variables constant. We

will generate matrix of these values and solve it.

to calculate the proportional delay (tp) of the NOT gate.

In second invertor, capacitance is generated at the PMOS

& NMOS transistors, we will call them as CP & CN

respectively. Now, the first Invertor will be either charge or

discharge the load capacitor CL.

Where CL = CP + CN. CL will be charged through PMOS

of first invertor and CL will discharge through NMOS of first

invertor.

Propagation delay for NOT gate is given by:

TP = (TPLH + TPHL) /2

Eq. (1)

For charging the load capacitor CL,

TPLH =RP CL

Eq. (2)

RP = VDD / IDSP

Eq.(3)

For discharging the load capacitor CL,

TPHL =RN CL

Eq. (4)

RN = VDD / IDSP

Eq. (5)

IDSP = IDS0 [1+(Vds Vdseff) / Vascbe] [1+(1/ Cclm) ln (VASAT +

VAclm) / VASAT]

Eq. (6)[4]

IDS0 = ( Weff / Leff ) eff (0 r / TOXE) Vgseff [1- (Abulk Vdseff)

(Vgsteff +4Vt)] [(Vdseff / (1+ Vdseff / sat Leff)] Eq. (7)[4]

eff = 0/[1+(VA+ VCVBS){Vgsteff +[2(VTH0 - Vfb - S)/TOXE ] EV}

Eq.(8)[4]

0 is low field mobility which is 0.06 m2/V for N channel

& 0.025 m2/V for P channel

VA is first order mobility degradation coefficient (10-15

m/v2).

VC is second order mobility degradation coefficient

(0.045 10-15 m/v2)

VFB is flat band voltage and the value is (-1.0Volt)

The load capacitor (CL) will charge through PMOS N1

and N2 and load capacitor (CL) discharge through either N3 or

N4. SO we need to design the PMOS and NMOS as per the

requirement. Rp1 and Rp2 will come in series through load

capacitor CL charges. So we need to take the value of Rp1 and

Rp2 as

Rp = Rp1 + Rp2

Eq. (11)

So to reduce the resistance Rp1 and Rp2 by half, we need to

increase the width (W) by twice. So the charging time of load

capacitor will be same. And for discharging the load capacitor

through NMOS transistors the RN1 and RN2 are in parallel but it

is not fix through which path it will discharge. So considering

the worst condition we keep the width (W) as it is for NMOS

transistors.

2863

IJRITCC | May 2015, Available @ http://www.ijritcc.org

_______________________________________________________________________________________

Volume: 3 Issue: 5

ISSN: 2321-8169

2862 - 2865

_______________________________________________________________________________________________

Propagation delay for NOR gate is given by:

TP = (TPLH + TPHL) /2

Eq. (12)

For charging the load capacitor CL,

TPLH = (RP1 + RP2) CL

Eq. (13)

RP1 = RP2 = VDD / IDSP

Eq. (14)

IDSP = IDS0 [1+(Vds Vdseff) / Vascbe] [1+(1/ Cclm) ln (VASAT +

VAclm) / VASAT]

Eq. (15)[4]

IDS0 = ( 2 Weff / Leff ) eff (0 r / TOXE) Vgseff [1- (Abulk

Vdseff) (Vgsteff +4Vt)] [(Vdseff / (1+ Vdseff / sat Leff)]

Eq. (16)[4]

And for discharging the load capacitor CL,

TNHL = RN3 CL or RN4 CL Eq. (17)

IDSP = IDS0 [1+(Vds Vdseff) / Vascbe] [1+(1/ Cclm) ln (VASAT +

VAclm) / VASAT]

Eq. (18)[4]

IDS0 = ( Weff / Leff ) eff (0 r / TOXE) Vgseff [1- (Abulk Vdseff)

(Vgsteff +4Vt)] [(Vdseff / (1+ Vdseff / sat Leff)] Eq. (19)[4]

C.

The Load capacitor (CL) will charge through the PMOS

Resistor Rp1 and Rp2 but the two resistors are in parallel in

NOT gate. So the resistance Rp1 and Rp2 needs to be double so

that it will charge the CL till its limit. So we need to decrease

the width (W) by half. And while discharging the load

capacitor discharges through RN3 and RN4 of the NMOS

transistors, here these RN3 and RN4 are in series. So again we

need to lower these resistances by half so we need to increase

the width (W) by twice.

Wherever Times is specified, Times Roman or Times New

Roman may be used. If neither is available on your word

processor, please use the font closest in appearance to Times.

Avoid using bit-mapped fonts if possible. True-Type 1 or Open

Type fonts are preferred. Please embed symbol fonts, as well,

for math, etc.

Eq. (20)

And for discharging the load capacitor CL,

TNHL = (RN3 + RN4) CL

Eq. (21)

RN3 = RN4 = VDD / IDSP

Eq. (22)

IDSP = IDS0 [1+(Vds Vdseff) / Vascbe] [1+(1/ Cclm) ln (VASAT +

VAclm) / VASAT]

Eq. (23)[4]

IDS0 = (2 Weff / Leff ) eff (0 r / TOXE) Vgseff [1- (Abulk

Vdseff) (Vgsteff +4Vt)] [(Vdseff / (1+ Vdseff / sat Leff)]

Eq. (24)

III. EXPERIMENTAL RESULT

Our method has been tested for the various cases and the

results are compared with the Monte- Carlo analysis for 16nm

technology are found to be as follows, percentage error in

mean for NOT gate is 0.018%, for NAND gate is 4.049% and

for NOR gate is 4.834%. Whereas the percentage error in

standard deviation for NOT gate is 11.083%, for NAND gate

is 0.206% and for NOR gate is 7.008%, and the percentage

error in propagation delay time for NOT gate is 0.205%, for

NAND gate is 4.854% and for NOR gate is 0.327%. In all

cases the result are considered for variation up to 0 to 10%.

From these result we can say that our result is closely matched

with the Monte-Carlo analysis to the satisfactorily conditions.

TABLE I.

Table

Head

RESULT TABLE

FOR MEAN

Mean

Statistical Analysis

Monte-Carlo

Analysis

% Error

Not

Gate

1.6354e-007

1.6351e-007

0.018%

Nor

Gate

2.3919e-007

2.2816e-007

4.834%

Nand

Gate

1.4904e-007

1.5533e-007

4.049%

TABLE II.

Table

Head

RESULT TABLE

Mean

Statistical Analysis

Monte-Carlo

Analysis

% Error

Not

Gate

8.9908e-009

8.0937e-009

11.083%

Nor

Gate

1.0854e-008

1.1672e-008

7.008%

Nand

Gate

8.1950e-009

8.1781e-009

0.206%

TABLE III.

Table

Head

RESULT TABLE

Mean

Statistical Analysis

Monte-Carlo

Analysis

% Error

Not

Gate

1.7954e-007

1.7991e-007

0.205%

Nor

Gate

2.3919e-007

2.3841e-007

0.327%

Nand

Gate

1.6364e-007

1.7199e-007

4.854%

TP = (TPLH + TPHL) /2

For charging the load capacitor CL,

2864

IJRITCC | May 2015, Available @ http://www.ijritcc.org

_______________________________________________________________________________________

Volume: 3 Issue: 5

ISSN: 2321-8169

2862 - 2865

_______________________________________________________________________________________________

7

x 10

4.5

4.5

3.5

3.5

2.5

2.5

1.5

1.5

0.5

1.5

1.55

1.6

1.65

1.7

1.75

1.8

x 10

0.5

1.35

1.85

1.4

1.45

1.5

1.55

1.6

-7

1.7

1.75

1.8

-7

x 10

x 10

1.65

x 10

REFERENCES

Satish Kumar Y, un Li, Claudio Talarico, Janet Wang et. Al. The

probabilistic collocation method based statistical gate delay model

considering process variations and multiple input switching, IEEE

2005.

[2] Bhagath P. J. and Ramesh S. R. A survey of SSTA technique with focus

of accuracy and speed, International Journal of Computer Applications

(0975 8887) Volume 89 No.7, March 2014.

[3] A . Agrawal, Static Timing Analysis for Intra Die Process Variation

with Spatical Correlations, ICCAD 2003.

[4] Tanveer Hasan Morshed, et. Al. BSIM4v4.7MOSFET mode-User

Reference Manual, 2012UC Berkeley.

[5] Chang, Hongliang, and Sachin S. Sapatnekar. "Statistical timing

analysis considering spatial

correlations using a single PERT-like

traversal." In Proceedings of the 2003 IEEE/ACM international c

onference on Computer-aided design, p. 621. IEEE Computer Society,

2003.

[6] Devgan, Anirudh, and Chandramouli Kashyap. "Block- based static

timing analysis with uncertainty." In Proceedings of the 2003

IEEE/ACM international conference on computer-aided design, p. 607.

IEEE Computer Society, 2003.

[7] Zhang, Lizheng, Weijen Chen, Yuhen Hu, and CC-P. Chen. "Statistical

timing analysis with extended pseudo- canonical timing model." In

Design, Automation and Test in Europe, 2005. Proceedings, pp. 952957. IEEE, 2005.

[8] Blaauw, David, Kaviraj Chopra, Ashish Srivastava, and Louis Scheffer.

"Statistical timing analysis: From basic principles to state of the art."

Computer-Aided Design of Integrated Circuits and Systems, IEEE

Transactions on 27, no. 4 (2008): 589-607.

[9] Chung, Jaeyong, and Jacob A. Abraham. "Refactoring of Timing Graphs

and Its Use in Capturing Topological Correlation in SSTA." ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on

31, no. 4 (2012): 485-496.

[10] Chung, Jaeyong, Jinjun Xiong, Vladimir Zolotov, and Jacob A.

Abraham. "Path criticality computation in parameterized statistical

timing analysis using a novel operator." Computer-Aided Design of

Integrated Circuits and Systems, IEEE Transactions on 31, no. 4 (2012):

497-508.

[1]

3.5

2.5

1.5

0.5

2.05

2.1

2.15

2.2

2.25

2.3

2.35

2.4

-7

x 10

2865

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