Escolar Documentos
Profissional Documentos
Cultura Documentos
Xiaoying Li1
Fuming Sun2
Enhua Wu1, 3
1
University of Macau, Macao, China
2
University of Science and Technology Beijing, Beijing, China
3
Institute of Software, Chinese Academy of Sciences, Beijing, China
ABSTRACT
In this paper, a hierarchical pipeline FIR filter structure is
proposed and implemented using FPGA hardware. It is a
flexible multi-rate structure. By adopting the clock of
computation several times faster than the sampling rate,
multiplications and additions can be finished using the
shared component to reduce the logic area. Only a few
more delay units are needed to separate the basic FIR
filter structure into two levels: in-group and betweengroup. As the number of taps of filter increases, the
structure can be easily extended without increasing the
delay of critical path. A Simulink-to-FPGA flow is
applied to the multi-rate structure of FIR filter with mixed
HDL and Simulink blockset design entry.
KEY WORDS
1. INTRODUCTION
Finite Impulse Response (FIR) filters are one of the
primary types of digital filters used in various Digital
Signal Processing (DSP) applications such as audio signal
processing, video convolution functions and telecommunications by virtue of stability and easy
implementation. The standard FIR filters design contains
a great number of multiplications which require large
silicon area, increase the power consumption, and state
the upper limit of the maximum sampling rate. Early
works have been done on replacing multiplications by
decomposing them into simple operations such as addition,
subtraction, shift and sharing common sub-expressions [1],
on minimizing the delay and the number of adders [2],
and on the tradeoffs between truncated multipliers and the
accuracy of computation [3]. Various application specific
FIR filters are frequently implemented using FPGA [4].
In this paper, a new structure of FIR filter is proposed and
implemented with FPGA hardware. It is a flexible twolevel architecture with two clock rates. By adopting a
clock several times faster than the sampling rate, the
multiplying and adding component can be highly shared
for computation, which can greatly reduce the number of
multipliers and realize high throughput while it does not
augment the delay in the critical path. According to the
relation of N (taps) and M (ratio of two clock rates),
N / M 1 additional delay units should be added
(1)
(a)
(b)
Figure1. Two Basic Forms of FIR Filter (N=5)
(a) Direct
(b) Transposed
The symmetry property of a linear-phase FIR filter can be
exploited to reduce the number of multipliers into almost
half in the direct form implementations. Both odd and
even order symmetric FIR structures are illustrated in
Fig.2. Other forms such as cascade, lattice and poly-phase
structures can also be used as complex FIR filter
structures.
5. DISCUSSION
From the development of FPGA technology, the
methodology challenges the update of various EDA tools.
Based on the standard development flow (Fig. 6), initial
efforts have been transferred to high-level design and
synthesis. There are many conversion tools such as C-toFPGA, Stateflow diagram to VHDL (SF2VHD), Matlabto-FPGA (MATCH). The features of Simulink-to-FPGA
flow can be discussed as follows.
Friendly graphics interface. Although the
schematic entry is also a GUI interface, the
Simulink is easier to organize input data and
much convenient to observe output in many ways.
Easy to number format conversion. Double to
fixed point number conversion is parameterized to
functional blocks. But the consistence of data type
must be noticed during the data flow.
ACKNOWLEDGMENT
The research is supported by the Research Grant of
University of Macau.
REFERENCES
[1] Y. C. Lim, J. B. Evans, and B. Liu, Decomposition of
binary integers into signed power-of-two terms, IEEE
Trans. Circuits System., vol. 38, 1991, 667-672.
[2] Hyeone-Ju Kang and In-Cheol Park, FIR filter
synthesis algorithms for minimizing the delay and the
number of adders, IEEE Trans. Circuits System, vol.42,
2001, 770-777.
[3] E. G. Walters III, Design tradeoffs using truncated
multipliers in FIR filter implementations, Masters Thesis,
Lehigh University, May 2002
[4] L. Mintzer, FIR Filters with FPGA, Journal of VLSI
Signal Processing, 6, 1993, 119-127.
[5] Samueli, H., An improved search algorithm for the
design of multiplierless FIR filters with powers-of-two
coefficients, Circuits and Systems, IEEE Transactions on,
Volume: 36 Issue: 7, 1989, 1044 -1047.
[6] Xilinx, Xilinx System Generator, Version 6.2, Xilinx
Inc., USA.
[7] Altera,. Altera DSP Builder, Version 5.1, Altera Inc,
USA.
[8] AccelChip, Integrating MATLAB Algorithms into
FPGA Designs, in Xcell Journal, 2005, 73-75.