ECE 553: Testing and Testable Design of Digital Systems

Department of Electrical and Computer Engineering

University of WisconsinMadison
ECE 553: Testing and Testable Design of Digital Systems
Fall 2013-2014

Midterm Examination
CLOSED BOOK
Kewal K. Saluja
Date:
November 12, 2013
Place:
Room 2535 Engineering Hall
Time:
7:15 - 8:30 PM
Duration: 75 minutes

PROBLEM

TOPIC

POINTS

General Questions

10

Test Economics

16

Modeling

11

Fault Simulation

14

SCOAP Computation

10

Test Generation - Comb

14

Test Generation - Seq

10

Checking Sequence

15

TOTAL

SCORE

100

Show your work carefully for both full and partial credit.
You will be given credit only for what appears on your exam.
Last Name (Please print): SOLUTION
First Name:
ID Number:

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ECE 553: Testing and Testable Design of Digital Systems

1. (10 points) General Questions
Answer the following in brief and to the point. You must not use more than two to
three lines of explanation where an an explanation is needed.
(a) (1 point) Memory usage by a concurrent fault simulator is smaller than the
memory usage by a deductive fault simulator.
Answer False.
(b) (1 point) Memory usage by a serial fault simulator is smaller that the memory
usage by a deductive fault simulator.
Answer True
(c) (2 point) A gate level fanout-free realization of a circuit has 20 inputs and 2
outputs. What is the maximum number of tests we will need to test this circuit.
Hint: think checkpoints.
In a fanout free circuit there are no branches. Therefore only checkpoints in the
circuit are primary inputs. Hence the total number of faults for which we need to
find tests is 2x20 = 40. Thus the max number of tests is 40.
(d) (2 points) If a fault f1 dominates fault f2 , and the fault f2 dominates a fault f3 .
which of these faults can be deleted to reduce the fault list for fault detection.
Give reason.
We delete the fault that dominates. Hence delete faults f1 and f2 .
(e) (1 point) Method of Boolean Difference can be used to determine if a fault in a
combinational circuit is redundant.
Answer True
(f) (1 points) Easy/Hard heuristic can only be used in PODEM during backtrace
and it can not be used during D-drive.
Answer False.
(g) (1 points) If SCOAP CC0 value of a line in a circuit is 25 then it means that
this line can always be set to 0 by assigning appropriate values to the inputs to
the circuit.
Answer False.
(h) (1 points) If SCOAP CC1 value of a line in a circuit is inf then it means that
this line can never be set to 1 no matter what values are assigned to the inputs
to the circuit.
Answer True
2

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ECE 553: Testing and Testable Design of Digital Systems

2. (16 points) Test Economics
A chip manufacturer is to produce ICs in a very large quantity and it has worked out
its cost as follows:
.
Cost of design (amortized on each IC) = $ 5.00
.
Production cost of each IC = $ 1.00
.
Test cost for each IC = $ 2.00
Test as filter has the following properties based on the quality of test:
.
95% of the truly good devices will pass the test.
.
96% of the bad devices will fail the test.
Based on the technology used, it is known that the true yield of ICs being fabricated
is 80%.
Now answer the following questions:
(a) (1 point) What percentage of good devices will fail the test?
5%
(b) (1 point) What percentage of bad devices will pass the test?
4%
(c) (3 point) Determine the Yield of the above devices. You must show your work.
0.95x0.8 + 0.04x0.2 = 0.768 Which is 76.8%
(d) (3 point) Determine the Defect Level (DL) of the above devices. You must show
your work and write the value of defect level in parts per million?
(0.04x0.2)/0.768 = 0.010417 which is 10417 ppm

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ECE 553: Testing and Testable Design of Digital Systems

(e) (3 point) Determine the Yield loss due to above testing. You must show your
work.
0.05x0.8 = 0.04 which is 4%
Note this is corrct answer - but some students felt that yield loss is a ratio of good
devices faild to the good devices or devices tested good - I gave points for that if
it was explained by the student.
(f) (5 points) Assuming that the manufacturer will have to pay $50.00 for every bad
device sold to a customer (because customer will return a bad IC), at what price
should an IC be sold so that the manufacture breaks even.
Let y be the break even cost. Then:
y(0.8x0.95 + 0.2x0.04) - 50x0.2x0.04 = 5 + 1 + 2
Solving for y we obtain the break even cost to be $ 10.94

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ECE 553: Testing and Testable Design of Digital Systems

3. (11 points) Modeling-sol
A library cell of a design library realizes a function f (A, B, C) = A . B . C. A
designer, makes a mistake, while building this cell and makes incorrect connections
and realizes the function A . C . B. Answer the following and you must show your
work for full credit.
(a) (3 points) Write all primitive cubes of f .
All primitive cubes are (I used the order of variable to be A B C /outpur, same
as in f):
xx0/1

11x/1

0x1/0

x01/0

(b) (4 points) Write two propagation D-cubes of f :

i. a propagation D cube with at least one of the inputs to be logic 1:
D 1 1 / D ; Another propagation D cube with this property is 1 D 1 / D
Clearly complementing D will also obtain additional valid cubes.
ii. a propagation D cube with at least one of the inputs to be logic 0:
X 0 D / D; Another propagation D cube with this property is 0 x D / D
Clearly complementing D and D will also obtain additional valid cubes.
(c) (4 points) Write two primitive cubes of failure for the mistake specified in the
problem description.
Primitive cubes of the faulty function are
1 x 1 / 1;
x 0 x / 1;
0 1 x / 0;
x 1 0 / 0;
These in conjunction with the primitive cubes of f generate the following primitive cubes of fault:
1 1 0 / D;
0 0 1 / D;

0 1 0 / D;
101/D

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ECE 553: Testing and Testable Design of Digital Systems

4. (14 points) Fault Simulation - Deductive
The circuit of Fig 1 is to be simulated using the pattern given below:
pattern

A B C D E F

= 0 1 1 1 1 0

0
1

0
1
1

B
C

l
1
1

j
D

1
1

1
h
1

1 0

1
0

1
s

o
1

1
1

n
1
0

0
F

r
1

Figure 1: Circuit for deductive fault simulation - Solution

The fault list that needs to be simulated for this pattern is given below:
A/1

B/1

C/0

D/0

E/0

F/1

h/0

i/0

k/0

n/0

s/0

Note: During fault simulation, list associated with any line or gate must not contain a
fault that is not in the above list.
(a) (2 points) Indicate the true signal values in every gate of the circuit. For your
convenience, I have already provided values in one of the gates.
True values are shown in the gates.

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ECE 553: Testing and Testable Design of Digital Systems

(b) (10 points) In the table below, provide the deductive fault lists associated with
every line in the circuit. Again to get you started, I have already completed the
entries associated with all primary input lines.

Line Name

fault list

Line Name

fault list

A/1

C/1

--

D/0; h/0

C/0

D/0; h/0; n/0

D/0

D/0; h/0

E/0

C/0; D/0; k/0

F/1

D/0; h/0; n/0

D/0; h/0

C/0; D/0; h/0; k/0;

s/0

E/0

C/0; D/0; h/0;

k/0;/ n/0; s/0

D/0

A/1

C/0; k/0

(c) (2 points) Now, indicate which of the faults will be detected and at which output.
Faults detected at output u:
A/1
Faults detected at output t:
C/0; D/0; h/0; k/0;/ n/0; s/0

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ECE 553: Testing and Testable Design of Digital Systems

5. (10 points) SCOAP Computation
Consider the circuits shown in Figure 2 for SCOAP computations. This circuit is a
part of a larger combinational circuit.

(40,31)30

(30,15)55

G1

(45,24) 46

(40,31) 171

B1

(45,24) 46
B

G12

(45,24) 85
B2

G2

Z1

(105,20)97
G3

(70,13)96

(40,31) 30

(67,39) 50

(19,73)129

Z2

(38,46)71

Figure 2: Combinational Circuit for SCOAP Computations - solution

In this circuit some of the SCOAP values, i.e the CC0, CC1 and CO values, are already
computed and shown in the circuit. The notation used is (CC0,CC1) CO. While many
other values need to be computed. You are to compute all the remaining values, i.e.
CC0, CC1 and CO values which are not shown in the figure. Enter these values in
the table below. I have already entered the values shown in the figure in this table,
therefore you need only to complete the blank entries.
Line

Controllability

Observability

CC0

CC1

CO

30

15

55

45

24

B1

45

B2

Line

Controllability

Observability

CC0

CC1

CO

G1

40

31

30

46

G12

40

31

171

24

46

G2

38

46

71

45

24

85

Z1

40

31

30

70

13

96

G3

105

20

97

19

73

129

Z2

67

39

50

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ECE 553: Testing and Testable Design of Digital Systems

6. (14 points) Combinational Test Generation
A PODEM like test generator is used to generate a test of for the line 20 s-a-1 in the
circuit of Figure 3.
1
3
7
A
B

4
5

9
11

6
10

12

13
14

20

19
21
25
26

8
22
24

15
16

C
D

2
27
28

29

23
30
31

E
F

17
18

Figure 3: Circuit for test generation

It is still in the process of test generation and has made the assignments at some of
the primary inputs as follows and in the order shown:
B
C
C
A
A

=
=
=
=
=

1
0
1
1
0

(a) (3 points) Construct the decision tree for the completed work this far.
1
0
B --> C --> no test (backtrack) change decision
|
|
1
1 --> A --> no test (backtrack)
|
|
0 --> we are here

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ECE 553: Testing and Testable Design of Digital Systems

(b) (7 points) In the table below indicate all the implications of the above assignments and the D frontier. I have already filled in a few implications for some
signal lines.
Assignments
Implications
D frontier
B=1, C=1, Lines 2, 5, 8 are 1; Lines 1, 3,
A=0
4, 6 are 0;
Line 7, 9, 10 are 0; Line 11, 12, Gates 27, 26 and
13, 14, 15, 19 are 1; Lines 20 is 28
0 hence Lines 21, 22, 23 are D;
Line 25 is D;

Comments

D=1

backtrack

Line 24, 28 are 1; Line 26 is D null

and 27 is 1; lIne 29 is 1

(c) (4 points) If the next assignment is D = 1, will that cause a back track or lead
to a next new assignment? Show your work in the table above.
D frontier will disappear and it will lead to backtrack.

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ECE 553: Testing and Testable Design of Digital Systems

7. (10 points) Sequential Test Generation
Consider the sequential circuit given in Figure 4 containing two D-type flip-flops and
a logic gate.
A

B
FF1

FF2

D Q

D Q

Figure 4: Figure for a sequential circuit

(a) (2 points) In the Figure 5 I have provided two FFs and a box for the combinational part of the circuit. Redraw the combinational part of circuit in the box
and make all the connections. Note the FF labels: FF2 is drawn above FF1.
B

Q D
FF2

Q D
FF1

Figure 5: Figure for combinational part of the sequential circuit

The circuit within the block is in Figure 6

(b) (4 points) Draw the time frame expansion of this circuit for three time frames.
Clearly draw the timeframe boundaries and label them. Mark the inputs, outputs,
pseudo primary inputs and pseudo primary outputs appropriately in the model
you
The draw.
timeframe expansion model is shown in Figure 7
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ECE 553: Testing and Testable Design of Digital Systems

Q D
FF2

Q D
FF1

Figure 6: Figure for combinational part of the sequential circuit

X
X
D

Figure 7: Time frame expansion of the sequential circuit

(c) (4 points) Derive a test sequence that will detect a stuck-at 1 fault at the output
of OR gate. You can use any method you like. Use the time frame expansion
drawn by you to show clearly the values of the inputs and the time the values are
applied. You must also indicate the time the fault is detected and what will be
the expected output and the output of the faulty circuit for the input sequence
obtained by you.
The input sequence will be AB(t=1) 0X, AB(t=2) X0, AB(t=3) XX
The fault will be detected after application of second clock, i.e. in the third
timeframe. The output will be D, i.e. expected output is 0 and faulty circuit will
produce a 1.

12

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ECE 553: Testing and Testable Design of Digital Systems

8. (15 points) Checking Experiment
State table of a finite state machine with four states, A, B, C, and D; and a binary
input alphabet consisting of 0, and 1; is given in Table 1.
Table 1: State Machine for Problem 8
Input
0

A/0

C/0

A/1 D/1

B/0

D/0

B/1

D/1

Now consider applying the sequence 0 1 1 1 to this machine. Note when this sequence
is applied the initial state of the machine is not known.
(a) (2 points) What will be the output sequence. When the output is not known
write an X for that.
The output sequence will be x x x 1.
(b) (2 points) What will be the state sequence. When the state is not known just
indicate the state ambiguity. Assume before the sequence is applied the state
ambiguity is (ABCD).
The state ambiguities will be: (ABCD) (AB) (CD) D D
(c) (1 points) Does this machine initialize to some state during the application of
the above sequence.
Clearly machine initializes to state D after the input 0 1 1.
(d) (2 points) Find a shortest synchronizing sequence for this machine. You must
show your work otherwise no points will be awarded.
This machine has three shortest synchronizing sequences which are 0 0 - initializes
to state B; and 1 0 - initializes to state B; 1 1 initializes to state D.

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ECE 553: Testing and Testable Design of Digital Systems

(e) (4 points) Now consider a fault which causes the above machine to change to
the state table shown in Table 2. Note that there is only one change due the fault
and that is next state of B with input 0 is C instead of A.
Table 2: State Machine of the Faulty Machine for Problem 8
Input
0

A/0

C/0

C/1

D/1

B/0

D/0

B/1

D/1

Will the above sequence detect this fault? You must show your work otherwise
no credit will be given.
The faulty machine will produce the following output sequence:
xxx1
This is same as the fault free machine. Hence, this sequence will not detect the
fault.
(f) (4 points) Append a shortest possible sequence to the above sequence to detect
the fault described above. Again, you must show your work otherwise no credit
will be given.
First we notice that the faulty machine has exactly the same state (D) at the
end of sequence 0 1 1 1 as the fault free machine. We apply a 0 and transfer
the machine to state B. Now we apply the input 0 which will transfer the fault
free machine to state A while the faulty machine will transfer to state C. Now
we use Distinguishing sequence to differentiate between the states A and C. This
machine has two DS, 0 0 and 0 1. Either of these will work.
Thus we must append 0 0 0 0 or 0 0 0 1 to detect the fault.

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