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Understandingthebasicsofsetupandholdtime|EDN

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Home > Analog Design Center > How To Article

Understanding the basics of setup and hold time

DeepakBehera,KarthikRaoC.G.andDeepakMahajan,FreescaleSemiconductorApril19,
2012
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Tounderstandwhysetupandholdtimearisesinaflipfloponeneedstobeginbylookingatits
basicfunction.Theseflipflopbuildingblocksincludeinvertersandtransmissiongates.Inverters
areusedtoinverttheinput.Itisimportantheretonoteitscharacteristicvoltagetransfercurve
(SeeFigure1).

Figure1.Abasicbuildingblockofaflipflop,aninverterfeaturesacharacteristicvoltage
transfercurve.
Atransmissiongate,denotedbyTxthroughoutthearticle,isaparallelconnectionofnMOSand
pMOSwithcomplementaryinputstobothMOSFETs(seeFigure2).Bidirectional,itcarries
currentineitherdirection.Dependingonthevoltageonthegate,theconnectionbetweenthe
inputandoutputiseitherlowresistanceorhighresistance,sothatRon=100orlessandRoff
>5M.Thiseffectivelyisolatestheoutputfromtheinput.

Figure2.Atransmissiongate,shownherewithatruthtable,isaparallelconnectionof
nMOSandpMOSwithcomplementaryinputstobothMOSFETs.
WheneverbothnMOSandpMOSareturnedon,anysignal'1'or'0'passesequallywellwithout
degradation.Theuseoftransmissiongateseliminatesundesirablethresholdvoltageeffectswhich
giverisetolossoflogiclevels.
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ThetransistorlevelstructureofaDflipflopcontainstwo'backtoback'invertersknownasa
'latchingcircuit,'sinceitretainsalogicvalue.ImmediatelyaftertheDinput,aninvertermayor
maynotbepresent(SeeFigure3).

Figure3.ThetransistorlevelstructureofDflipflopcontainstwobacktobackinverters
knownasa'latchingcircuit.
Normaloperationofaflipflop
Inordertovisualizenormaloperationsofaflipflop(SeeFigure4),in4a,initiallyD=0andCLK
isLOW.InputfollowsthepathDWXYZandfinallyZ=0.Weareneglectingthe'latchingcircuit'
onRHSforthetimebeing.

Figure4.TheworkingsofaDflipflopwherebythedarkenedlineshowstheconducting
path.
WhentheCLKisHIGH(See4b),latchingcircuitonLHSisenabled.Itlatches1,whichresultsin
Q=0(whichiswhatitshouldbeforD=0).Notethattheoutputarrivesatthepositiveedgeof
CLK.Henceitisapositiveedgetriggeredflipflop.
WhentheCLKisLOW,theRHSlatchingcircuitisenabled(See4c)andthereisnochangein
output.AnychangeininputisreflectedatnodeZwhichisreflectedintheoutputatthenext
positiveedgeofCLK.
Insummary,ifDchanges,thechangewouldreflectonlyatnodeZwhenCLKisLOWandit
wouldappearattheoutputonlywhentheCLKisHIGH.
ItisherethatweintroduceSETUPandHOLDtime.Setuptimeisdefinedastheminimum
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amountoftimebeforetheclock'sactiveedgethatthedatamustbestableforittobelatched
correctly.Anyviolationmaycauseincorrectdatatobecaptured,whichisknownassetup
violation.
Holdtimeisdefinedastheminimumamountoftimeaftertheclock'sactiveedgeduringwhich
datamustbestable.Violationinthiscasemaycauseincorrectdatatobelatched,whichisknown
asaholdviolation.Notethatsetupandholdtimeismeasuredwithrespecttotheactiveclock
edgeonly.
ReasonforSETUPTime:

Figure:5.ThetimeittakesdataDtoreachnodeZiscalledthesetuptime.
InFigure5,whenD=0andCLKisLOW,inputDisreflectedatnodeZsothatW=1,Y=0,
andZ=1anditwilltakesometimetotraversethepathDWXYZ.ThetimethatittakesdataD
toreachnodeZiscalledtheSETUPtime.WhentheCLKisHIGH,T1isswitchedOFFandT2is
switchedON.Therefore,theLHS'latchingcircuit'kicksintoactionlatchingthevaluepresentat
nodeZ,andproducingitintheoutput(Q=0andQ'=1).
ItisindispensablefornodeZtohaveastablevaluebythen.Anydatasentbeforethesetuptime,
asdefinedabove,willproduceastablevalueatnodeZ.Thisdefinesthereasonforthesetup
timewithinaflop.
ReasonforHOLDTime:

Figure6.Thedarkenedlineshowstheconductingpathforholdtime.
Aspreviouslyindicated,HOLDtimeismeasuredwithrespecttotheactiveCLKedgeonly.In
Figure6,inputdataDisgiventotheinverter,oranyotherlogicsittingbeforetransmissiongate
T1,andisapartoftheflipflop.TheCLKandCLKBARinFigure6thatcontrolstheswitchingof
thetransmissiongates,comeaftertherampingupoftheCLKsignal,i.e.afterpassingthrough
buffersandinverters.
ThereisafinitedelaybetweentheCLKandCLKBARsothatthetransmissiongatetakessome
timetoswitchonoroff.Inthemeantimeitisnecessarytomaintainastablevalueattheinputto
ensureastablevalueatnodeW,whichinturntranslatestotheoutput,definingthereasonfor
holdtimewithinaflop.
Afinitepositivesetuptimealwaysoccurs,howeverholdtimecanbepositive,zero,oreven
negative.Let'slookatwhyandhowthiscanbetrue.Asdiscussedearlier,theremaybe
combinationallogicsittingbeforethefirsttransmissiongatetomaketheflopsetresetenableor
scanenable,possiblyforyetanotherreason.Thisintroducesacertaindelayinthepathofinput
dataDtoreachthetransmissiongate.Thisdelayestablisheswhethertheholdtimeispositive,
negative,orzero.
InFigure7,Tinitialisthetimedelayintroducedbythecombinationallogicsittingbeforethefirst
transmissiongateandTTXisthetimetakenforthetransmissiongatetoswitchONorOFFafter
theCLKandCLKBARisgiven.TherelationshipbetweenTinitialandTTXgivesrisetothe
varioustypesofholdtimethatexist.
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Figure7.TherelationshipbetweenTinitialandTTXestablishesvarioustypesofholdtime
TherelationshipbetweenTinitialandTTXinFigure8furtherclarifiespositive,zero,andnegative
holdtime.

Figure:8.Relationshipsthatestablishpositive,zero,andnegativeholdtime.Adjustingthe
TTXchangestheholdmargin.
InFigure8,CLKrepresentstheclockwithanactiverisingedge,D1,D2andD3represent
variousdatasignals,Srepresentsthesetupmargin,andH1,H2,andH3denotestherespective
holdmargins.TTXindicatesthetimetakenforthetransmissiongatetoswitchONorOFFafter
theCLKandCLKBARarrive,andTinitialisthetimedelayintroducedbythecombinationallogic
sittingbeforethefirsttransmissiongate.SinceHOLDmarginisalwaysdecidedwithrespectto
theactiveclockedge,playingwiththeTTXwillchangetheholdmargin.
Abouttheauthors:
DeepakBeheraisadesignengineerwithexperienceinsignalintegrityandpackagedesigning
andanalysis.KarthikRaoC.G.isadesignengineerwithexperienceindigitalIPdesign.Deepak
MahajanisadesignEngineerwithexperienceinSoCverification.
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12Comments
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KarthikR856
HiDurgeshK461,
Holdtimeisnotjustaformality.Ifthereisnosetup
violation,stabledatahasindeedreachedpointZ(not
justpointX).Butaftertheclockedge,thereisa
certaintimebeforethetransmissiongateitselfcloses
completely.Ifanynewdatachangenowpasses
throughthisgatebeforeitscompletelycloses,the
originaldataisnowcorruptedandhencecorrectdata
cannotcomeoutoftheRHSlatch.
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KarthikRaoC.G.
Sept25,20153:31PMEDT
0| 0

Reply
DurgeshK461
Ithinktheholdrequirementisjustaformality.because
Itismeasuredfromtheedge.Thatmeansifwethink
thatthereisnosetupviolation,thestabledatahas
alreadyreachedthepointX.Soaftertheedge,evenif
wechangetheinputItwillnotgetlatchedinthefirst
latch.Thatmeansthecorrectdatawillcomeouteven
ifwehaveaholdviolation.Onemorethingworth
mentioningthatacombilogicsittingbeforetheDinput
willalsoaffecttehsetuptimeasitwilltakemoretime
fortheinputtoreachtheoutputoflatch1.
Apr29,20142:54AMEDT

0| 0

Reply
jasonkee111
hi
iftheclockisnot50%dutycycle,e.g.80%high20%
low,doesitmeanthatitismoreeasierpronetosetup
failure?Thanks
Mar10,201410:44PMEST

0| 0

Reply
pekon_
Thankyouforsuchinformativearticlewithindepth
explanation.
[pekon]
Feb27,201412:16PMEST

0| 0

Reply
deependsailor
Superbarticle..Igotitclearnowthatwhatexactly
setupandholdtimeis.
Regards
Deepen
Sept11,20137:36AMEDT

0| 0

Reply
kiran5509
HelloDeepak,
Ithinkiunderstandtheholdtimenow.Theminimum
amountoftimethedatarequiredtobestableonactive
clockedgewhileT1andT2turnoffandon

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respectively.Thisarticleisreallytopnotchamuch
neededon.
Thankyou,
Manju
Apr2,20134:08PMEDT
0| 0

Reply
kiran5509
TheconductingpathduringriseedgeisfromZtoQ
right.Butduringexplanationofholdtheconduction
pathisshowfromDtoW.shouldtheholdtimebeZ
holdingstudywhiletheT2getsturnedon?.Kindly
pleaseclarify.
Thankyou,
Manju
Apr2,20134:47PMEDT

0| 0

Reply
SaiGovindaRao
AwesomeArticle.Thewholeofmyengineeringand
evenmy1yearjobdidnothelpmeingivingsucha
goodreasonedunderstanding.
ThankYouveryMuch
Aug2,20122:42AMEDT

0| 0

Reply
ddr71m
HiSaurabh,Verywellwrittenarticle...
Jun26,20125:30AMEDT

0| 0

Reply
KarthikRao
HiSaurabh,

Thatfigureessentiallyconsistsoftwolatches
connectedinseries,withthetransmissiongates
presenttoprovidetherightclockedgestothelatches
resultinginaFlipFlopoperation.Asmentionedinthe
article,theinitialinverterstagemayormaynotbe
presentintheactualcircuit.Thisinverter,ifpresentis
usuallyusedforaddingscanchainingcapabilitiesto
theflipfloptohelpcheckDesignForTestability.
Apr27,20125:42AMEDT
0| 0

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anonymoususer
Ithinkitsmoreimportanttounderstandwhathappens
whenyoucannotcontrolsetupandholdtimes.Istheir
agoodarticle,withoutMarketingFluff,givingconcrete
waystominimizemetastabilityusingMSIlogicfor
thoseofuswhodontuseprogrammablelogic
devices?
Apr26,20121:22AMEDT
0| 0

Reply
anonymoususer
ButsirwhydoweneedsuchacomplexcircuitforD
flipflop?Thiscanbemadesimplybyfeedingthe
outputoffirstdlatchtotheseconddlatch(i.e.only2
dlatchesinseries)withfirstonedrivenbyclkand
secondonebyclk'.Inmycircuit,canyoutellmethe
causeforsetupandholdtime?
Apr22,20122:07AMEDT

0| 0

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