DFT ASSIGNMENT -1

J.SWAPNA
201532548
VERILOG CODE FOR ALU
// design of ALU using mux
module alumux( input [3:0]a,
input [3:0]b,
input [2:0]si,
output reg[7:0]z );
always @(a or b or si)
begin
case(si)
3'b000: z<=a&b;
3'b001: z<=a|b;
3'b010: z<=~a;
3'b011: z<=~b;
3'b100: z<=a<<b;
3'b101: z<=a>>b;
3'b110: z<=a+b;
3'b111: z<=a-b;
endcase
end

endmodule

SIMULATION OUTPUT

ALU TEST BENCH

//ALU test bench

module alutestbech;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg [2:0] si;
// Outputs
wire [7:0] z;
// Instantiate the Unit Under Test (UUT)
alumux uut (.a(a),
.b(b),
.si(si),
.z(z));
initial begin
// Initialize Inputs
a = 4'b1010;
b = 4'b1100;
si = 3'b000;#30
si = 3'b001;#30
si = 3'b010;#30
si = 3'b011;#30
si = 3'b100;#30
si = 3'b101;#30
si = 3'b110;#30
si = 3'b111;#30

// Wait 100 ns for global reset to finish

#100;
// Add stimulus here
end
endmodule

RTL SCHEMATIC

SYNTHESIS REPORT

Release 13.3 - xst O.76xd (nt)

Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.59 secs
--> Reading design: alumux.prj
Synthesis Options Summary

==============================================
===========================
---- Source Parameters
Input File Name

: "alumux.prj"

Ignore Synthesis Constraint File : NO

---- Target Parameters
Output File Name
Output Format
Target Device

: "alumux"
: NGC
: xc7a8-3-csg324

---- Source Options

Top Module Name

: alumux

Automatic FSM Extraction

: YES

FSM Encoding Algorithm

: Auto

Safe Implementation
FSM Style
RAM Extraction
RAM Style
ROM Extraction

: No
: LUT
: Yes
: Auto
: Yes

Shift Register Extraction

ROM Style

: YES
: Auto

Resource Sharing

: YES

Asynchronous To Synchronous

: NO

Shift Register Minimum Size

Use DSP Block

:2
: Auto

Automatic Register Balancing

: No

---- Target Options

LUT Combining

: Auto

Reduce Control Sets

Add IO Buffers

: Auto
: YES

Global Maximum Fanout

: 100000

Add Generic Clock Buffer(BUFG)

Register Duplication

: 32

: YES

Optimize Instantiated Primitives : NO

Use Clock Enable
Use Synchronous Set

: Auto
: Auto

Use Synchronous Reset

: Auto

Pack IO Registers into IOBs

: Auto

Equivalent register Removal

: YES

---- General Options

Optimization Goal

: Speed

Optimization Effort

:1

Power Reduction

: NO

Keep Hierarchy

: No

Netlist Hierarchy

: As_Optimized

RTL Output

: Yes

Global Optimization
Read Cores

: AllClockNets
: YES

Write Timing Constraints

: NO

Cross Clock Analysis

: NO

Hierarchy Separator

:/

Bus Delimiter

: <>

Case Specifier

: Maintain

Slice Utilization Ratio

: 100

BRAM Utilization Ratio

: 100

DSP48 Utilization Ratio

: 100

Auto BRAM Packing

: NO

Slice Utilization Ratio Delta

:5

HDL Synthesis

==============================================
===========================
Synthesizing Unit <alumux>.
Related source file is "c:/xilinx/alu/alumux.v".
Found 5-bit subtractor for signal <GND_1_o_GND_1_o_sub_8_OUT>
created at line 39.
Found 5-bit adder for signal <n0035[4:0]> created at line 38.
Found 8-bit shifter logical left for signal <GND_1_o_b[3]_shift_left_4_OUT>
created at line 36

Found 8-bit shifter logical right for signal

<GND_1_o_b[3]_shift_right_5_OUT> created at line 37
Found 8-bit 8-to-1 multiplexer for signal <z> created at line 31.
Summary:
inferred 2 Adder/Subtractor(s).
inferred 3 Multiplexer(s).
inferred 2 Combinational logic shifter(s).
Unit <alumux> synthesized.
==============================================
===========================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
5-bit adder

:2
:1

5-bit subtractor

:1

# Multiplexers

:3

8-bit 2-to-1 multiplexer

:2

8-bit 8-to-1 multiplexer

:1

# Logic shifters

:2

8-bit shifter logical left

8-bit shifter logical right

:1
:1

==============================================
===========================

Design Summary

==============================================
===========================

Top Level Output File Name

: alumux.ngc

Primitive and Black Box Usage:

-----------------------------# BELS

: 48

LUT2

:4

LUT3

:3

LUT4

:7

LUT5

:6

LUT6

: 23

MUXF7

:5

# IO Buffers

: 19

IBUF

: 11

OBUF

:8

Device utilization summary:

Selected Device : 7a8csg324-3
Slice Logic Utilization:
Number of Slice LUTs:

43 out of 5000

Number used as Logic:

0%

43 out of 5000

0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used:
Number with an unused Flip Flop:

43
43 out of

43 100%

Number with an unused LUT:

0 out of

43

0%

Number of fully used LUT-FF pairs:

0 out of

43

0%

Number of unique control sets:

IO Utilization:
Number of IOs:

19

Number of bonded IOBs:

19 out of

200

9%

==============================================
===========================
Timing Report
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------No clock signals found in this design
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 2.949ns
Timing Details:All values displayed in nanoseconds (ns)

==============================================
===========================
Timing constraint: Default path analysis
Total number of paths / destination ports: 276 / 8
------------------------------------------------------------------------Delay:
Source:
Destination:

2.949ns (Levels of Logic = 6)

b<1> (PAD)
z<0> (PAD)

Data Path: b<1> to z<0>

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

20 0.001 0.781 b_1_IBUF (b_1_IBUF)

LUT6:I0->O

1 0.097 0.693 Mmux_z25 (Mmux_z24)

LUT6:I0->O

1 0.097 0.511 Mmux_z26_SW0 (N2)

LUT3:I0->O

1 0.097 0.295 Mmux_z26_SW1 (N4)

LUT6:I5->O

1 0.097 0.279 Mmux_z26 (z_0_OBUF)

OBUF:I->O

0.000

z_0_OBUF (z<0>)

---------------------------------------Total

2.949ns (0.389ns logic, 2.560ns route)

(13.2% logic, 86.8% route)

Total REAL time to Xst completion: 30.00 secs

Total CPU time to Xst completion: 30.54 secs
Total memory usage is 343936 kilobytes