DIGITAL SYSTEMS DESIGN LABORATORY

Laboratory Activity 3
VHDL Modeling of Arithmetic Circuits

Cesar A. Llorente

DIGITAL SYSTEMS DESIGN LABORATORY

De La Salle University
2401Taft Avenue, Manila
Philippines 1004

DIGITAL SYSTEMS DESIGN LABORATORY

Lab Activity 3. VHDL Modeling of Arithmetic Circuits

You have seen in Laboratory Activity 2 the modeling of combinational circuits particularly
the decoder and multiplexer. Writing the test bench to verify the functionality of the circuit was
emphasized. An octal 8-1 multiplexer and a 3x8 decoder was synthesized as part of the data routing
components of the SAP datapath.
In this laboratory activity, you will model arithmetic circuits both using structural method
and data flow method. For the structural model, you will start by creating the inverter, and gate,
and or gate. Then you will use these components to create the full adder circuit. You will then
combine these components to create the 4-bit parallel adder circuit. You will then synthesize the
subtractor circuit by first creating an exclusive or gate, which are then used to create an 8-bit or gate
array. This or gate array will be used to take the complement of the B operand to implement an 8-bit
adder- subtractor circuit. You will then model an 8-bit Arithmetic Logic Unit (ALU). Finally, you
will write the test bench that will test the functionality of the 8-bit ALU.

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DIGITAL SYSTEMS DESIGN LABORATORY

I. OBJECTIVES
A. Synthesize a Full Adder circuit using structural VHDL model.
B. Synthesize a 4-bit parallel adder circuit using structural VHDL model.
C. Write a VHDL test bench to simulate the Full Adder circuit and the 4-bit parallel adder
circuit.
D. Synthesize and simulate an 8 bit subtractor circuit using dataflow modeling.
E. Synthesize and simulate an 8-bit Arithmetic Logic Unit (ALU).

II. Equipment and Materials

PC with Xilinx ISE softwares installed
Spartan3E FPGA starter Kit

III. Conceptual Framework

A full adder circuit has a Boolean equation for its sum output as S = (A B Ci) + (AB Ci)
+ (AB Ci) + ( ABCi), and for the carry output, Co = (B Ci) + ( A Ci ) + ( A B). Structural
modeling is implemented by first synthesizing the 3- input AND gate and the 4-input OR gate, in
addition to the 2-input AND gate and inverter previously synthesized in lab 2 (see Table 1 (a)
through (e). Using these components, the Full Adder circuit can be synthesized. The complete
VHDL code for the Full Adder using structural modeling is shown in Table 1(f).
Simulation of the function of the circuit can be done using a test bench coded in VHDL.
While the test bench in previous laboratory activities were created graphically, the input stimulus
that will exercise the circuit under test can be specified in VHDL. Table 1(g) lists the VHDL
testbench for the full adder circuit. The resulting simulation timing waveform is shown in Table
1(h).
In contrast, the Full Adder circuit can be modeled as a simple VHDL assignment statement
(data flow modeling) as in Listing 1 below.
Listing 1. Full Adder
--FA.vhd
library ieee;
use ieee.std_logic_1164.all;
entity FA is
port ( A, B, Cin : in std_logic;
S, Co
: out std_logic);
end FA;
architecture a of FA is
begin
S <= (A and not B and not Cin) or ( not A and B and not Cin) or ( not A and not B and Cin)
and B and Cin);
Co <= ( B and Cin) or ( A and Cin ) or ( A and B );
end a;

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or (A

DIGITAL SYSTEMS DESIGN LABORATORY

Logic symbol for Full Adder

Full adder timing diagram

The full adder circuit can be utilized to create a 4-bit parallel adder circuit. Parallel adder
circuits of any width having a multiple of 4 bits, can be implemented using the 4-bit parallel adder
circuit. Implementation of parallel adder circuits can be one wherein the carry output of the
previous stage propagates of ripples through the succeeding stages. This imposes performance
penalty in speed. The dataflow model for a 4-bit adder circuit is listed below;
Listing 2
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity add4_1 is
port ( A, B
Cin
S
Co
end add4_1;

: in std_logic_vector(3 downto 0);

: in std_logic;
: out std_logic_vector(3 downto 0);
: out std_logic);

architecture a of add4_1 is
signal opr1, opr2, sum
: std_logic_vector(4 downto 0);
begin
opr1 <= "0000" & Cin + A;
opr2 <= '0' & B;
process(opr1, opr2)
begin
sum <= opr1 + opr2;
end process;
S <= sum(3 downto 0);
Co <= sum(4);
end a;

A subtractor circuit is defined by the Boolean equations D = X xor Y xor Bi for the
Difference, and Bout = X Y + X Bin + Y Bin. The subtractor circuit is also implemented by
complementing the B input of the full adder circuit. Making the carry input of the full adder to 1
makes subtraction in 2s complement form.
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DIGITAL SYSTEMS DESIGN LABORATORY

The VHDL structural model of an 8-bit parallel adder-subtractor circuit is listed in Table 3 .
The implementation of the 8-bit adder and 8-bit xor circuits are done using dataflow. These
components are interconnected together in the top-level entity (add_sub.vhd) using structural
modeling.

IV. Procedure
1. Launch the Xilinx ISE software.
2. Open the lab project created during the first lab activity.
3. Remove all the source files.
3.1. Select a filename from the Sources pane.
3.2. Select Remove from the Source Menu.
3.3. Repeat the process until all source files were removed from the Sources pane except for the
andgate and the invert.
4. Synthesize the full adder circuit using structural modeling.
4.1. Synthesize the 3-input and gate.
4.1.1.
Open a text editing window by selecting New in the File menu.
4.1.2.
Double-click on the text file button or click on the text file button and click OK.
4.1.3.
Copy and paste or type in the code listed in Table 1(c).
4.1.4.
Save the file using the entity name as the file name.
4.1.5.
Add this file to the project files by clicking on Add Source from the Project menu.
4.1.6.
Select the file by double-clicking on the file name, andgate3.vhd.
4.1.7.
Click OK in the Adding Sources pop up window.
4.1.8.
Make the file as the top entity in the hierarchy by clicking Set as Top Module in the
Source menu.
4.1.9.
Compile the file by double-clicking on the Synthesize - XST in the Processes pane.
Make sure that the Synthesize/Implementation is selected in the Sources pane.
4.1.10.
Repeat steps 4.1.1 through 4.1.8 for all logic gates listed in Table 1 (e) through (g).
Listing Table 1(g) is the full adder circuit.
5. Simulate the Full Adder circuit using the test bench in VHDL listed in Table 1(h).
5.1. Create the VHDL test bench.
5.1.1. Select the New Source from the Project menu.
5.1.2. Select VHDL Test bench from the New Source Wizard.
5.1.3. Type in the file name, fullAdder_tbw, in the File name text box. Make sure that the
Add to Project check box is selected. Click Next.
5.1.4. Highlight the filename of the design file in this case, fullAdder.vhd and click Next.
5.1.5. Click Finish in the next pop up window. A VHDL test bench template will be
automatically generated by the EDA tool. You may copy the code listing in Table 1 (g)
and paste it to the test bench edit window.
5.2. Run the simulation.
5.2.1. Select the Behavioral Simulation form the Sources pane.
5.2.2. Click on the Processes tab in the Processes pane to display the ISE Simulator in the
Processes pane. Expand the menu by clicking on the + sign that precedes the ISE
Simulator menu.

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DIGITAL SYSTEMS DESIGN LABORATORY

5.2.3. Double-click on the

to start the simulation process.

Record the simulation waveform. Relate the input stimulus specified in the VHDL test
bench and the waveform generated. Also note the output generated and verify whether
the output waveform response is correct for the operation of a full adder circuit.
Modify the test bench by creating your own set of input stimulus.
6. Synthesize and simulate the 4-bit Parallel Adder circuit modeled in Table 2. Repeat the process
followed in the synthesis and simulation of the full adder circuit. Take note that the VHDL test
bench is listed in Table 2 (b) and (c).
7.

Synthesize and simulate the 8-bit adder - subtractor circuit listed in Table 3. Create the VHDL
test bench to simulate the operation. The test bench should shown both the addition and
subtraction operations in a single simulation run.

V Machine Problem 2
a. Synthesize and simulate an 8-bit adder circuit using structural modeling using the 4-bit
parallel adder as illustrated in this laboratory manual.
b. Discuss the performance of the circuit in (a) if it will be used to implement a 32-bit adder.
Will it presents performance penalties to the system where the circuit is to be used? In
what way? Support your answer with simulation results and propagation delays
determined by the synthesis tool.
c. Synthesize and simulate the Arithmetic Logic Unit specified in chapter 4 of the book
Computer Organization and Design, 2nd edition by Patterson and Hennessy.

Cesar A. Llorente

DIGITAL SYSTEMS DESIGN LABORATORY

Table 1. Structural modeling of a Full Adder
(a)
--invert.vhd
library ieee;
use ieee.std_logic_1164.all;
entity invert is
port ( A : in std_logic;
Y
: out std_logic);
end invert;
architecture a of invert is
begin
Y <= not A;
end a;
(b)
--andgate.vhd
library ieee;
use ieee.std_logic_1164.all;
entity andgate is
port ( A, B
Y
end andgate;

: in std_logic;
: out std_logic);

architecture a of andgate is
begin
Y <= A and B;
end a;
(c)
--andgate3.vhd
library ieee;
use ieee.std_logic_1164.all;
entity andgate3 is
port ( A,B,C
Y
end andgate3;

: in std_logic;
: out std_logic);

architecture a of andgate3 is
begin
Y <= A and B and C;
end a;
(d)
--3-input OR gate
library ieee;
use ieee.std_logic_1164.all;
entity orgate3 is
port ( A,B,C

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: in std_logic;

DIGITAL SYSTEMS DESIGN LABORATORY

Y

: out std_logic);

end orgate3;
architecture a of orgate3 is
begin
Y <= A or B or C;
end a;
(e)
--4-input OR gate
library ieee;
use ieee.std_logic_1164.all;
entity orgate4 is
port ( A,B,C,D
Y
end orgate4;

: in std_logic;
: out std_logic);

architecture a of orgate4 is
begin
Y <= A or B or C or D;
end a;
(f)
-- Full Adder
library ieee;
use ieee.std_logic_1164.all;
entity fullAdder is
port ( A, B, Ci
S, Co
end fullAdder;

: in std_logic;
: out std_logic);

architecture a of fullAdder is
component invert is
port ( A : in std_logic;
Y
: out std_logic);
end component;
component andgate is
port ( A, B
: in std_logic;
Y
: out std_logic);
end component;
component andgate3 is
port ( A,B,C
Y
end component;

: in std_logic;
: out std_logic);

component orgate3 is
port ( A,B,C
Y
end component;

: in std_logic;
: out std_logic);

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DIGITAL SYSTEMS DESIGN LABORATORY

component orgate4 is
port ( A,B,C,D
Y
end component;

: in std_logic;
: out std_logic);

-- S = (A B? Ci?) + (A?B Ci?) + (A?B? Ci) + ( ABCi)

-- Co = (B Ci) + ( A Ci ) + ( A B)
signal An, Bn, Cin, or4A,or4B,or4C,or4D,or3A,or3B,or3C

: std_logic;

begin
u1: invert port map (A=>A, Y=>An);
u2: invert port map (A=>B, Y=>Bn);
u3: invert port map (A=>Ci, Y=>Cin);
u4: andgate3 port map (A=>A, B=>Bn, C=>Cin, Y=>or4A);
u5: andgate3 port map (A=>An, B=>B, C=>Cin, Y=>or4B);
u6: andgate3 port map (A=>An, B=>Bn, C=>Ci, Y=>or4C);
u7: andgate3 port map (A=>A, B=>B, C=>Ci, Y=>or4D);
u8: orgate4 port map (A=>or4A, B=>or4B, C=>or4C, D=>or4D, Y=>S);
u9: andgate port map (A=>B, B=>Ci, Y=>or3A);
u10:andgate port map(A=>A, B=>Ci, Y=>or3B);
u11:andgate port map (A=>A, B=>B, Y=>or3C);
u12:orgate3 port map (A=>or3A, B=>or3B, C=>or3C, Y=>Co);
end a;
(g) VHDL Test bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY fullAdder_tbw_vhd IS
END fullAdder_tbw_vhd;
ARCHITECTURE behavior OF fullAdder_tbw_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fullAdder
PORT(
A : IN std_logic;
B : IN std_logic;
Ci : IN std_logic;
S : OUT std_logic;
Co : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL Ci : std_logic := '0';
--Outputs
SIGNAL S : std_logic;

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DIGITAL SYSTEMS DESIGN LABORATORY

SIGNAL Co : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fullAdder PORT MAP(
A => A,
B => B,
Ci => Ci,
S => S,
Co => Co
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
-- Place stimulus here
A <= '0';
B <= '0';
Ci <= '0';
wait for 50 ns;
A <= '1';
B <= '0';
Ci <= '0';
wait for 50 ns;
A <= '0';
B <= '1';
Ci <= '0';
wait for 50 ns;
A <= '1';
B <= '1';
Ci <= '0';
wait for 50 ns;
A <= '0';
B <= '0';
Ci <= '1';
wait for 50 ns;
A <= '1';
B <= '0';
Ci <= '1';
wait for 50 ns;
A <= '0';
B <= '1';
Ci <= '1';
wait for 50 ns;

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DIGITAL SYSTEMS DESIGN LABORATORY

A <= '1';
B <= '1';
Ci <= '1';
END PROCESS;
END;
(h) Simulation Timing waveform of full adder using the VHDL test bench in (g)

Table 2. Model for a 4-bit parallel adder using the full adder circuit model in Table 1.
(a) VHDL model for a 4-bit ripple parallel adder
-- 4-bit Parallel Adder
library ieee;
use ieee.std_logic_1164.all;
entity parallelAdder4bit is
port ( A, B
Ci
S
Cy
end parallelAdder4bit;

: in std_logic_vector(3 downto 0);

: in std_logic;
: out std_logic_vector(3 downto 0);
: out std_logic);

architecture a of parallelAdder4bit is
component invert is
port ( A
Y
end component;

: in std_logic;
: out std_logic);

component andgate is
port ( A, B
: in std_logic;
Y
: out std_logic);
end component;
component andgate3 is

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DIGITAL SYSTEMS DESIGN LABORATORY

port ( A,B,C
Y
end component;

: in std_logic;
: out std_logic);

component orgate3 is
port ( A,B,C
Y
end component;

: in std_logic;
: out std_logic);

component orgate4 is
port ( A,B,C,D
Y
end component;

: in std_logic;
: out std_logic);

component fullAdder is
port ( A,B,Ci
S, Co
end component;

: in std_logic;
: out std_logic);

signal C1, C2, C3

: std_logic;

begin
u1: fullAdder port map (A=>A(0),B=>B(0),Ci=>Ci, S=>S(0), Co=>C1);
u2: fullAdder port map (A=>A(1),B=>B(1),Ci=>C1, S=>S(1), Co=>C2);
u3: fullAdder port map (A=>A(2),B=>B(2),Ci=>C2, S=>S(2), Co=>C3);
u4: fullAdder port map (A=>A(3),B=>B(3),Ci=>C3, S=>S(3), Co=>Cy);
end a;
(b). Test bench template for the 4-bit parallel adder.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY parallelAdder_tbw_vhd IS
END parallelAdder_tbw_vhd;
ARCHITECTURE behavior OF parallelAdder_tbw_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT parallelAdder4bit
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Ci : IN std_logic;
S : OUT std_logic_vector(3 downto 0);
Cy : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL Ci : std_logic := '0';
SIGNAL A : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL B : std_logic_vector(3 downto 0) := (others=>'0');

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DIGITAL SYSTEMS DESIGN LABORATORY

--Outputs
SIGNAL S : std_logic_vector(3 downto 0);
SIGNAL Cy : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: parallelAdder4bit PORT MAP(
A => A,
B => B,
Ci => Ci,
S => S,
Cy => Cy
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END;

(c). Input stimulus for the test bench template.

A <= "0000";
B <= "0000";
Ci <= '0';
wait for 50 ns;
A <= "0001";
B <= "0000";
Ci <= '0';
wait for 50 ns;
A <= "0010";
B <= "0011";
Ci <= '0';
wait for 50 ns;
A <= "0101";
B <= "1000";
Ci <= '0';
wait for 50 ns;
A <= "0111";
B <= "1100";
Ci <= '0';
wait for 50 ns;

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DIGITAL SYSTEMS DESIGN LABORATORY

A <= "1001";
B <= "0111";
Ci <= '0';
wait for 50 ns;
A <= "0001";
B <= "0000";
Ci <= '1';
wait for 50 ns;
A <= "0010";
B <= "0011";
Ci <= '1';
wait for 50 ns;
A <= "0101";
B <= "1000";
Ci <= '1';
wait for 50 ns;
A <= "0111";
B <= "1100";
Ci <= '1';
wait for 50 ns;
A <= "1001";
B <= "0111";
Ci <= '1';
wait; -- will wait forever

(d). Simulation timing waveform generated by the testbench using the input stimulus in
(c).

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DIGITAL SYSTEMS DESIGN LABORATORY

Table 3. VHDL model of an 8-bit parallel adder-subtractor circuit used in the Simple As
Possible computer.
(a) 8-bit adder circuit
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity add8 is
port ( A, B
Cin
S
Co
end add8;
architecture a of add8 is
signal opr1, opr2, sum

: in std_logic_vector(7 downto 0);

: in std_logic;
: out std_logic_vector(7 downto 0);
: out std_logic);

: std_logic_vector(8 downto 0);

begin
opr1 <= "00000000" & Cin + A;
opr2 <= '0' & B;
process(opr1, opr2)
begin
sum <= opr1 + opr2;
end process;
S <= sum(7 downto 0);
Co <= sum(8);
end a;
(b). 8-bit XOR gate array used to complement input B.
library ieee;
use ieee.std_logic_1164.all;
entity xor8 is
port(a, b : in std_logic_vector(7 downto 0);
Y
: out std_logic_vector(7 downto 0));
end xor8;
architecture a of xor8 is
begin
Y <= a xor b;
end a;
(c). 8-bit adder-subtractor circuit.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity add_sub8 is

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port ( A, B
su
S
Co
end add_sub8;

: in std_logic_vector(7 downto 0);

: in std_logic;
: out std_logic_vector(7 downto 0);
: out std_logic);

architecture a of add_sub8 is
component add8 is
port ( A, B
cin
S
Co
end component;

: in std_logic_vector(7 downto 0);

: in std_logic;
: out std_logic_vector(7 downto 0);
: out std_logic);

component xor8 is
port(a, b : in std_logic_vector(7 downto 0);
Y
: out std_logic_vector(7 downto 0));
end component;
signal xortmp, sutmp

: std_logic_vector(7 downto 0);

begin
sutmp <= su & su & su & su & su & su & su & su;
g1: xor8 port map (b, sutmp, xortmp);
g2: add8 port map (a, xortmp, su, S, Co);
end a;

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DIGITAL SYSTEMS DESIGN LABORATORY

Preliminary Report

Laboratory Activity 3. VHDL Modeling of Arithmetic Circuits

Date Performed: _________________________
Date Submitted: __________________________

Group Number: ___________

Team
Task

Name and Signature

Design:
Test/Verification:
Documentation:
Procurement:
Setup

_________________________________
_________________________________
_________________________________
_________________________________
_________________________________

Instructor: ______________________________________

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DIGITAL SYSTEMS DESIGN LABORATORY

Data and Results
4.

Propagation Delay = ______________________

5. Timing waveform

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6. Propagation Delay

Timing

7. Propagation Delay

Timing

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DIGITAL SYSTEMS DESIGN LABORATORY

Summary of the Activity Performed (Individual report from team members detailing individual
activities done during the Laboratory Activity)
Group Number: _____________
Name and Signature of Member: __________________________________
Role: _____________________________________________
Summary

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DIGITAL SYSTEMS DESIGN LABORATORY

GROUP EVALUATION FORM

Laboratory 3: VHDL Modeling of Arithmetic Circuits
Group No:

Section:

LAB SCHEDULE:

Group Members:
1.

DATE PERFORMED:

2.
3.
4.
5

Exercises
Problems
Teamwork (+pts)
EVALUATION GRADE:

DATE SUBMITTED:

EVALUATION: (for lab instructor use only)

Exercises (45%):

Problems (45%):

Lab Performance (5%):

[
[
[
[
[

]
]
]
]
]

members are in proper/designated places

members performed assigned role.
exhibit correct work habits ( adherence to safety , proper use of tools/equipment/instruments)
maintain cleanliness and orderliness in the lab (no liters, clean workbench arranged chairs before leaving)
submit preliminary report at the end of the laboratory session

Attendance (5%):
[
[

] all members present on time or before the 5-minute grace period

] come to class prepared ( photocopy of the lab manual, Preliminary Report, and Group Evaluation Form,
source codes needed, datasheets, etc.)

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