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Why Power Management Chips???

Chips???

Design of High-efficiency DCDC Power Converter Circuits

Prof. Amit Patra, Department of EE &


Advanced VLSI Design Laboratory,
Indian Institute of Technology, Kharagpur

Power management chips are the interface between batteries


and different chips (RF, Base-band and Digital)
Different elements need special supply voltage and have also
different requirements in terms of noise, power supply
rejection ratio (PSRR) and quiescent current

Mobile
phone

PC

Private mobile
radio

Camera

PDA

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Power Distribution

Power Management Circuits

Linear Voltage Regulator (LDOs)


Step-Down Regulator
Switching Voltage Regulator
Buck (Step-Down) Converter
Boost (Step-Up) Converter
Buck-Boost Converter (Inverting / Non-inverting)
Switched Capacitor Converters (Charge-Pumps)
Step-Up Regulator
Step-Down Regulator
Inverting Amplifier

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Linear Voltage Regulator

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Linear Regulator Power Model

Simple and low noise


Output Voltage is lower than the input voltage
High efficiency only if Vo is close to Vg

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Linear regulator efficiency cannot be greater than the ratio of


the output and the input voltage

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Buck Switching Voltage Regulator

Switching Voltage Regulators


fs = Switching frequency
D = Duty Ratio
D = 1 - D

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Switching Voltage Regulator

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Device/Converter Specifications

Static voltage regulation

DC output voltage precision, i.e., % variation with


respect to the nominal value over:

DC-DC Buck Converter

DC-DC Boost Converter

input voltage range (line regulation)


output load range (load regulation)
temperature

Dynamic voltage regulation

DC-DC Buck-Boost Converter

Load transient response, including peak output


voltage variation and settling time for a step load
transient
Line transient response, including output voltage
variation and settling time for a step input voltage
transient

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Other Features/Requirements

Overvoltage protection

Frequency synchronization

Soft start

Shut-down and operating-mode control

Adjustment of the output voltage using

turns the device off if the input (battery) voltage drops


below a specified threshold

Current limiting (overload protection)

Other Features/Requirements

prevents the output voltage from rising above a specified


limit

Undervoltage shutdown

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limits the load current

Thermal shutdown

turns the device off if the temperature exceeds a specified


threshold
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allows synchronization of the switching frequency to


an external system clock
controlled output voltage increase during startup
enables a system controller to shut-down the device,
or to select an operating mode(PWM,PFM,LDO)
a resistive voltage divider,
external analog control voltage, or
digital (pin-select) control

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Buck converter analysis

Switch 1 is ON

Switch in position 1

Switch 2 is ON
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Switch in position 2

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Average Voltage across the Inductor

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Inductor Voltage and Current Waveforms

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Average Current across the Inductor

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Inductor Current Conduction Mode

Implementing ZeroZero-cross Detect

With the zero-crossing comparator the switch S2 operates


as a diode, resulting in DCM and improved efficiency at light
loads

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CCM vs. DCM

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Selection of the Inductor

In DCM, the inductor current is always positive


At light loads, in DCM, the duty cycle is significantly lower
than in CCM
CCM operation at light loads is undesirable because the
reversal of the inductor current polarity contributes to
conduction losses, while it does not contribute to the output
load current
With a diode rectifier, DCM operation occurs automatically
because of the diode characteristic
With a synchronous rectifier, DCM operation at light loads
can be accomplished by turning off the NMOS switch at the
zero-crossing of the inductor current

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Selection of the Capacitor

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Switch Realization
NMOS switch
PMOS
Switch

Switch
control
signals

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Advanced VLSI Design Laboratory

Conduction Losses

Switching Losses
Average and RMS values

Switching losses are proportional to the


switching frequency
Switching loss mechanisms:

Charging/discharging of capacitance at
MOSFET gates and switch node
Body-diode reverse recovery
Inductor eddy-current and core losses

Switch on-resistance and forward voltage drops result in switch conduction


losses
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Switching Frequency in PFM

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Discussion of Operating Modes

In PFM, the switching frequency is directly proportional to the load current


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Different Control approaches

The switch duty cycle is controlled based on


output voltage compensation

Current-mode control

Asynchronous Buck Converter (in PSM)

Hysteretic voltage control


Voltage-mode control

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The switch duty cycle is controlled based on


output voltage and switch current sensing

Energy based Control

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Typical Waveform
Mode-I

Inductor Current In PSM


During charging:

Mode-II

Gate
Pulses

di
Vo- E =- L
iL
IP

Inductor
Current

( i-

Inductor Current

Vo
R

) =C

dt
dVo

Ton =

dt
IP L
E- Vo

During discharging:

Output
Voltage

Vo=- L

IP L is constant. => constant Volt-sec.

( i-

Hysteresis
Band

Vo
R

) =C

Toff =

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di

dt
dVo
dt
IP L
Vo

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Time

Hysteretic Control of PSM Converter

Possible Improvements
The efficiency will be lower
for lower output voltage due
to large forward diode drop in
the rectifier

The efficiency can be


improved if the diode is
replaced by a synchronous
switch

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Advanced VLSI Design Laboratory

Typical Waveforms
Ip

Ton

Advantages and Disadvantage of HMC

Toff

IL

E-IL*rds(on)
Vout
Vg

Vz

Suitable for low load applications


Predetermination of inductor value and peak
inductor current
Variable frequency operation

Vcomp

Vmono

Diode-On

PMOS-On

NMOS-On

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VoltageVoltage-Mode Control Architecture

Different Blocks for VMC

Band gap reference circuit


Error Amplifier
Ramp Oscillator
PWM Comparator
Dead Time
Drivers

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Error Amplifier

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Ramp Oscillator
Vdd

High DC gain > 60db


Unity gain Bandwidth ~= 10 times crossover
Slew Rate > 10times Vdd*Fs
Pole zero compensation of LC filter
Desired loop bandwidth =~ Fs/5 to Fs/10

I
R1

I = C * Fsw * v1

comparator
v1

clock

R2

10/2

RS

vc
Latch

Ramp Signal

200/2

Vref
comparator

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CurrentCurrent-Mode Control Architecture

Supply Voltage

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Switching Regulators : Design Steps


1.

Define requirements
Range of input voltages

Required output voltage(s)

Required output current


Find a suitable controller IC

Web sites; parametric searches

From a list of suitable ICs, optimize for


efficiency and ease of procurement
Read datasheet closely!
Find the inductor, capacitor, diode
Build prototype

2.

3.
4.
5.

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Advanced VLSI Design Laboratory

Switching Regulators: Passives

Switching Regulator ICs


Finding Parts

Some manufacturers
www.national.com

www.maxim-ic.com

www.linear.com

www.analog.com

www.ti.com

www.intersil.com

www.fairchild.com

www.st.com

Capacitors
Low-ESR tantalums: medium ESR,
Sanyos POSCAPno explosions!

Aluminum electrolytics: high ESR,

Cornell Dubiliers Organic semiconductor


OSCONlow ESR, high cost
Solid polymer aluminum: low ESR,

Diodes
Schottky diodes: low voltage drop

SMT are best


Inductors

High current-handling, low resistance


required

SMT toroids work very well

Many more or design yourself .

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Motivations
Switch Capacitor Circuits

or
Charge Pumps

Inductor-less
On-chip integration
Low cost
High switching frequency
Easy to implement (open-loop system)
Fast transient but large ripple
High efficiency but limited output power

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Ideal Dicksons Charge Pump(Phase 1)

Ideal Dicksons Charge Pump(Phase 2)


3VDD-2Vt

2VDD-Vt

VDD

2VDD-Vt

VDD

VDD-Vt

VDD-Vt
VDD-Vt

VDD

VDD-Vt

0
VDD

2VDD-2Vt

C1

Vo
C2

clk

clk_bar

Clk=0, Clk_bar=VDD
Finite diode voltage drops, Vt

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VDD

Vo

VDD-Vt

C3

VDD

clk

clk_bar

C1

C2

C3

Clk=VDD, Clk_bar=0
Maximum voltage stress on diodes 2VDD-Vt => reliability issue
Maximum voltage stress on capacitors VCn =n(VDD-Vt) => reliability issue
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Switching Regulators : Switched Capacitor

Produce output voltage


equal to Vin or 2 x Vin

Applications

Flash ROM
Substrate Biasing Circuits

Output noisy and poorly


regulated, but OK for
certain applications

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Advanced VLSI Design Laboratory

Power Supply Design : Helpful Hints

Efficiency not an issue? Linear regulators may be best.


Battery powered? Consider switcher for efficiency.
Vout > Vin? Use a switcher (Boost).
With switchers, stick to simple topologies like Boost and
Buck. Advanced topologies not for the faint of heart!
Use a combination of switchers and linear regulators to get
multiple output voltages.
Electrical noise an issue (e.g., with A/D converters)?
Strongly consider post-regulation using a linear regulator.
Need to double (2 x Vin) or invert (-Vin)? Consider a
capacitive charge pump .
Put batteries in series, not parallel. Parallel batteries can
rapidly self-discharge, wasting battery life.

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Voltage Regulator Modules

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Next Generation Power Supplies

Higher current load together with


increased slew rate

Decreasing trend of supply voltages

Smaller inductor can be used improves dynamics

Intel road map of CPU load voltage


and current
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Ripple cancellation @ Vo

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Interleaving Technique

Why Multiphase?
Current division
Higher current carrying capability

Better thermal performance


Low current in each phase reduces the loss and heat
generated

Use of ceramic capacitors for decoupling


Inductors are in parallel during load transient fast
settling small multi-layer ceramic capacitors

Two synchronous Buck Phase Shifted by 180 degree


Current ripple is cancelled for duty ratio of 50%

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Voltage Mode Control Scheme


400nH

Rds =2m

Waveforms for VMC

2m

SW1
G1

1.

Phase shifted ( switching


period divided by number
of phases) ramps are
compared with error
amplifier output

2.

D = Vea/Vramp

S1
Vin

Rds =2m

DRIVERS

Vout

12V

ESR

Q D
Q

load

1m

S2

20m

2000uF

S1
Ramp1

400nH

Ramp1

Vea

2m

Rds =2m
SW2
G2

DRIVERS

Rds =2m

Ve

VID

PID

Ramp2

Vea

Voltage
Compensator

Vref
+

D
A

G1

Q D

S2

Ramp2

G2
0

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Layout Issues

Power MOSFET Design

Current Carrying Capability

Maximum current limit of Metals used


Maximum current in an array

t1

Ts/2

t2

Ts

3/2Ts

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Layout of the Power MOSFET


Determine size of the single cell for
fixed current carrying capability
which is fraction of total rated
current of POWER MOSFET

Optimization of Losses

Conduction Loss is inversely proportional to size


Switching loss is directly proportional to size
Conduction Loss = Switching Loss

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Connect the devices in parallel


Source

Array of MOSFETs
Gate

D
R
A
I
N

S
O
U
R
C
E

Drain

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A POWER MOSFET
Thank You

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Advanced VLSI Design Laboratory

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