Building a Battery Operated Auto Ranging DVM

with the ICL7106

Application Note

AN046
Larry Goff

Introduction

Input Divider Network

In the field of DVM design, three areas are being addressed

with vigor: size, power dissipation, and novelty. The
handheld portable multimeter has gained in popularity since
low power dissipation devices enabled battery operation, LSI
A/D converters reduced IC count, and novelties such as
conductance, automatic range scaling, and calculating were
included to entice the user.

A simplified drawing of the divider network is shown in

Figure 2. This configuration was chosen for simplicity and
implementation using analog switches. The low leakage
ID101s are used for input protection, and the second set of
switches to IN LO reduces the net error due to switch
resistance. This can be seen calculating IN HI and IN LO
voltages for the two equivalent circuits.

This application note describes a technique for auto-ranging

a battery operated DVM suitable for panel meter
applications. Also, circuit ideas will be presented for
conductance and resistance measurement, 9V battery and
5V supply operations, and current measurement.

For equivalent circuit A,

Auto Ranging Circuitry

The control signals necessary for auto-ranging are overrange, under-range, and clock. The over-range and underrange inputs control the direction of a scale shift, becoming
active at the completion of an invalid conversion and
remaining active until a valid conversion occurs. The clock
input controls the timing of a scale shift. This signal should
occur only once per conversion cycle, during a time window
which will not upset an ongoing conversion and must be
disabled after valid conversions.
In the circuit of Figure 1, inverted over-range (O/R) and
under-range (U/R) are generated by detecting the display
reading. The ICL7106 turns the most significant digit on and
blanks the rest to indicate an over-range. An under-range
occurs if the display reads less than 0100. R1C1 and R2C2
are required to deglitch O/R and U/R.
The next step in the logic disables O/R and U/R prior to
shifting into nonexistent ranges. O/R is disabled when in the
200V range, while U/R is disabled when in the 200mV range.
The next level of gating disables the clock if the conditions
are as described above and a valid conversion state exists.
Clock is enabled only when a range shift is called for and
there exists a valid range to shift into.
The CD4029 is a four bit up/down counter, used as a register
to hold the present state and as a counter to shift the scale
as directed by the control inputs. The CD4028 is a BCD to
decimal decoder interfacing the CD4029 and ladder
switches. An additional exclusive OR gate package is added
to drive the appropriate decimal point.

RS + R K
V MEAS = V IN HI = ------------------------------------- V IN
R S + R + R K

(EQ. 1)

where RS = switch resistance, R = input resistance (1M),

and 1 + K is the desired divider ratio.
Ideally VINHI should be
RK
1
V IDEAL = ----------------------- V IN = ------------- V IN
R K + R
1 + K

(EQ. 2)

Therefore the percent error is:

Ideal Actual
--------------------------------------- 100,
Ideal

(EQ. 3)

R S + R/K

or 1 ( 1 + K ) ----------------------------------- 100
R

S + R/K + R

(EQ. 4)

The worst case error occurs at (1+K) = 1000. For this

example, the error due to a 1kW switch resistance is 99.7%.
IN HI for equivalent circuit B is the same as Equation 1.
However, IN LO for circuit B is:
RS

------------------------------------- V IN ,
R S + R + R K

(EQ. 5)

and combining Equations (1) and (5)

RK
V MEAS = V INHI V INLO = ------------------------------------- V IN
R + R + R K
S

(EQ. 6)

The percent error is equal to:

R/K
1 ( 1 + K ) ---------------------------------- 100

R + R + R/K

(EQ. 7)

Using the same values for RS, (1+K), and R, the worst case
error is 0.1%. This error can be further improved if lower
rDS(ON) switches are used. From the results calculated
above, the worst case conversion error due to switch
resistance will be one count of the least significant digit for a
full scale input, and a slight adjustment to R itself will correct
the remaining error on all scales.

1-888-INTERSIL or 321-724-7143 | Copyright

Intersil Corporation 1999

V+

V+

V+

OSC 1

40

D1

OSC 2

39

C1

OSC 3

38

B1

TEST

A1

REF HI

36

F1

REF LO

35

G1

CREF

34

E1

CREF

33

D2

COMMON

32

10 C2

IN HI

31

CREF
100k
100pF
CLOCK

37 DIG GND

A/Z

1k
1F

ICL7106 PIN26
V-

1
8
9 74C32

10
4011

4011
3
13

1
2

4
A

12

O/RANGE
3

10k 6
R1

C1

4023 5 10
0.005F
TEST
O/RANGE
1
10k
2

R2 9
4023
C2 0.005F

1
4023

11 4
12

5
6

13

8
9

10

IN LO

30

12 A2

A-Z

29

13 F2

BUFF

28

14 E2

INT

27

15 D3

V-

26

16 B3

G2

25

17 F3

C3

24

18 E3

A3

23

19 AB4

G3

22

20 POL

BP

21

Q2
D

R8

22k

Q1

0.47F

100k

47k

3N169
N CH.

1M

D2

0.22F
V-

TEST

11

13

VIN

4011

11

2N3702
Q3

12

TEST

4011

3
4

11 B2

0.01F

D1

47M

C3
0.1F

20k

5.1k

C
ID101
TEST

V+
1

PE

V+ 16
CLK 15

14

3
4

V+

2
3

13

4
B
A

CD402T

C1

12

C 12

Q1

Q7 11

D 11

UP/DOWN 10

A 10

BINARY
9
DECODE

6, 12

TEST

A
7
8

8 CD4016

B 13

CD4029BC

6 8

9 12

13

5, 13
12

CD4016

TEST
UP/DOWN
COUNTER

BACK
PLANE
DECODER

ARROW

FIGURE 1. AUTO RANGING CIRCUITRY

R4

10.1k
10
11
R5
3
4

A OR D

1M

VIN

1 14

1.001k
3

13, 5

3 15

R6

V+ 16

R1 R2 R3

8
6

111.1k

10
11
9

OPEN
OPEN

Application Note 046

D
3

24k

Application Note 046

R
IN HI

+
ID101
VIN

R/999

R/99.01

R/9

IN LO

SWITCH CONTROL
LINES
200V

20V

200mV

2V

FIGURE 2A.

+
R

TO IN HI

TO IN HI
VIN

VIN

R/K

R/K

VMEAS
TO IN LO

VMEAS
R SWITCH

R SWITCH
TO IN LO

FIGURE 2B. EQUIVALENT CIRCUIT A

(SWITCHES TO IN LO REMOVED)

FIGURE 2C. EQUIVALENT CIRCUIT B

(SWITCHES TO IN LO INCLUDED)
FIGURE 2. INPUT DIVIDER NETWORK

Ranging Clock Circuit

Two N-Channel MOSFETs, a PNP transistor and a handful
of passive components combine to generate the clock signal
used to gate the auto-ranging logic. A closer look at the inner
workings of the ICL7106 will help clarify the discussion of
this circuit. The analog section of the ICL7106 is shown in
Figure 3.
It can be shown that CREF low (pin 33 of ICL7106) will sit at
-VREF for DE+ and at common for DE-, with DE+
designating the deintegrate phase for a positive input signal
and DE- referring to a negative input signal. During the autozero phase, CREF low is tied to an external reference
through pin 35, which in Figure 1 is VREF below the positive
supply. The net result is that CREF low is above COMMON
during auto-zero, is left to float during signal integrate, and is
at or below COMMON during deintegrate. R8 and D1 are
added externally to pull CREF to COMMON during integrate,
with Q2 and R1 included to speed this action. The signal at
CREF low is now a square wave that is high during auto-zero
and low at all other times. Q1 and Q3 amplify and level shift
this waveform for logic level compatibility. This clock signal is

gated through D2 and controls the timing of the auto-ranging

circuitry. C3 is added to delay the clock, eliminating disparity
with O/R and U/R (see Figure 4 for timing diagram).

Application Note 046

CREF
RINT
CREF+

REF HI

34

36

V+

A-Z

REF LO

CREF -

BUFFER

35

33

28

A-Z

CAZ
V+
1

CINT

A-Z

INT

29

27
INTEGRATOR

10A

TO
DIGITAL
SECTION

2.8V

31
IN HI
DE-

INT

DE+

6.2V

INPUT
HIGH

A-Z

A-Z

DE+

32

COMPARATOR

DE-

COMMON
INT

INPUT
LOW

A-Z AND DE()

30
IN LO

26
V-

FIGURE 3. ANALOG SECTION OF ICL7106

INTEGRATOR
A/Z

OVER-RANGE
CONVERSION

A/Z

VALID
CONVERSION

A/Z

CREF LOW
(PIN 33)

CLOCK

O/R, U/R

FIGURE 4. TIMING DIAGRAM

Supply Requirements
The circuit of Figure 1 operates on a standard 9V transistor
battery. CMOS logic and a CMOS A/D converter (ICL7106)
are used to extend battery life; the approximate power drain
for this circuit is 8mW. The circuit in Figure 5 can also be
added to detect low supply voltage.
The circuit of Figure 6 can be used to generate 5V from a
single 5V supply. The ICL7660 is a voltage converter which
takes a 5V input and produces a -5V output. With respect to
common mode signals, the circuit of Figure 1 will have
infinite common mode handling capability if operated from a
floating 9V battery. However, if powered by a fixed supply
such as in Figure 6, the common mode capability of the

converter will be limited to approximately 2V, if COMMON is

disconnected from -VIN.

Application Note 046

For transconductance measurement, merely switch RSTD
and RX. This scheme makes the measurement of large
resistors, in conductance form, convenient and easy. This is
also convenient for leakage measurements.

1M
1

8
ICL8211

4 FIG 7

1M

180K
TO DISPLAY
INDICATOR

A simple current meter can be built using the circuit of

Figure 8. The low leakage of the ICL7106 (10pA/max)
makes possible the measurement of currents in the mid
pico-Amp range. However, the switch leakage current will
limit the accuracy of the resistor network and may degrade
converter resolution.

BACKPLANE
TEST

FIGURE 5. LOW VOLTAGE DETECTOR

900R

+5V
NC 1

AUTO-RANGING
DVM CIRCUIT

ICL7660

+
10F

IN HI
90R

7 NC
6 NC

IIN

ICL7106
9R

IN LO
10F

-5V
R

FIGURE 6. GENERATING 5V FROM +5V

Resistance, Transconductance and

Current Circuits

FIGURE 8. CURRENT METER

The purpose of this section is to show the simplicity of

measuring transconductance (1/R) and resistance with the
ICL7106. The circuit of Figure 7 requires only one precision
resistor per decade range of interest. The conversion output
is described by the formula:
RX
--------------- 1000
R STD

(EQ. 8)

V+

REF HI
RSTD
REF LO
IN914 or
IN4148

X4

ICL7106
IN HI

RX
IN LO

COMMON

FIGURE 7. TRANSCONDUCTANCE AND RESISTANCE

MEASUREMENT

Using the ICL7126 and ICL7107

With a few modifications, the circuit of Figure 1 can easily be
adapted for use with either the low power ICL7126 or the
ICL7107. Using the ICL7126 simply requires a change in the
values of the integrating and auto-zero components. Refer to
the ICL7126 data sheet for details.
The ICL7107 is an LED version of the ICL7106, and is a bit
trickier to use in this application. First the over-range/underrange logic must be changed slightly. Simply replace the
quad exclusive-NOR with an LM339; connect the outputs, as
before, to the CD4023 triple 3-input NAND. Second, the
ICL7107 requires +5V and -5V rather than the +9V battery
used in Figure 1. If battery operation is desired, the negative
supply can be derived from 4 Ni-Cad cells in series and an
ICL7660 (see Figure 9). Note that both supplies float with
respect to the input terminals. (Logic supplies are V+ and
DIG. GND.)

Application Note 046

ICL7107
+5V
ICL7660
1

2
+
10F

-5V
+

10F

12k

+
-

O /RANGE

+
+

U /RANGE

CD4023 OR
74C10

1 V3

OSC 1 40

2 D1

OSC 2 39

3 C1

OSC 3 38

4 B1

TEST 37

5 A1

REF HI 36

6 F1

REF LO 35

7 G1

CREF 34

8 E1

CREF 33

9 D2

COMMON 32

10 C2

IN HI 31

11 B2

IN LO 30

12 A2

A-Z 29

13 F2

BUFF 28

14 E2

INT 27

15 D3

V- 26

16 B3

G2 25

17 F3

C3 24

18 E3

A3 23

19 AB4

G3 22

20 POL

GND 21

+
LM339

-5V

NEGATIVE (0V)
LOGIC SUPPLY

33k

FIGURE 9. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNALS FROM ICL7107 OUTPUTS. THE LM339 IS
REQUIRED TO ENSURE LOGIC COMPATIBILITY WITH HEAVY DISPLAY LOADING

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