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A B C
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
D F
0 0
1 0
0 1
1 1
0 0
1 1
0 0
1 1
0 0
1 0
0 1
1 1
0 0
1 0
0 0
1 1
MUX 16:1
D
C
B
A
0
1
0
G15
2
3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ECE 241
Logic Circuit Lab
although only one Mux input is selected, we need to realize two potentially different values of F. If they
are different, they will be functions of D (either D or D). To see this, we partition the truth table into
sections where A, B and C have the same value. This is shown in Figure 2.
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B C D F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Vcc
C
B
A
D
D
0
1
0
MUX 8:1
0
1 G0
7
2
0
1
2
3
4
5
6
7
ECE 241
Logic Circuit Lab
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B C D
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
B
A
C
D
C
D
C
MUX 4:1
0 0
G
1 3
0
1
2
3
ECE 241
Logic Circuit Lab
A B C
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
D F
0 0
1 0
0 1 BC + BD
1 1
0 0
1 1
0 0
1 1
0 0
1 0
0 1 BC +CD
1 1
0 0
1 0
0 0
1 1
B
D
B
C
C
D
MUX 2:1
0
1
0}G
0
of n variables simply by connecting the outputs of the Decoder that correspond to the minterms of a
function to a multi-input OR gate. Consider the Decoder circuit shown in Figure 6 which implements
two separate functions of three variables. Notice that we have used a 74138 3-to-8 Decoder. As in most
Decoders, the outputs are asserted low. This allows us to use NAND gates to implement the minterm
sums.
We can see that, unlike Multiplexers, Decoders can be used to implement more than one Boolean
function at a time. On the other hand, a Multiplexer implementation may not require any external circuitry, while a Decoder circuit always needs external gates.
Also, in order to select the particular 7 segment group, the common Anodes A1 - A4 must be driven
by Vcc, meaning you will have to connect the A1 - A4 pins to the FPGA and pull them up internally
through an IO Buffer in your schematic entry.
3 Seven-Segment Displays
A Seven-Segment display consists of seven LEDs arranged in a figure 8, as shown in Figure 7. Lighting
combinations of the LEDs allows one to display various symbols. To display the symbol 0, we light
segments A, B, C, D, E and F. Lighting segments B and C produces the symbol 1. Because it is a
common anode display, to select a Seven-Segment display a high voltage is applied to the corresponding
anode (A1-A4 on the Digilab Board). Individual LED segments are lit by taking the inputs (the cathodes
CA-CG, DP) associated with the segment low.
Important Note - The seven segment LEDs are active low, meaning you will have to drive the segment low on the CA - CG, DP pins low in order to light up the LED segments. Example - if CA = 0, then
segment A will light up.
5 Experiment (10)
1. Implement the code converter you designed. Feel free to use components from the Xilinx library.
2. Perform a pre- or post-synthesis simulation of your design.
3. Assign pins to connect your design to switches and displays as needed, by creating a UCF file.
Download your design into the FPGA and demonstrate the functionality to the instructor or TA.
Obtain a signature for your report cover page or the design summary page.
ECE 241
Logic Circuit Lab
B C
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A F
0 0
1 0
0 0
C
1 0
0 1
1 1
0 1
1 1
0 0
1 0
0 1 D(A +C)
1 0
0 0
1 0
0 1
1 1
MUX 2:1
0
1
0}G
C
A
D
ECE 241
Logic Circuit Lab
A1
B
6 Report (5)
Turn in a brief, professional report summarizing your experience. Include your design schematics, any
simulations that you performed, and the design summary page.
C
D
CA CB CC CD CE CF
DP
C
B
A
BIN/OCT
0
1
1
2
2
3
4
4
5
6
7
F2
F1
CG DP