Escolar Documentos
Profissional Documentos
Cultura Documentos
LED LCD TV
SERVICE MANUAL
CHASSIS : LD23E
CONTENTS . ............................................................................................. 2
SERVICING PRECAUTIONS..................................................................... 4
SPECIFICATION........................................................................................ 6
ADJUSTMENT INSTRUCTION............................................................... 12
Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
Copyright © LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only
Only for training and service purposes
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES
manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as
SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo-
NOTE: If unforeseen circumstances create conflict between the sure of the assembly.
following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder ES
on page 3 of this publication, always follow the safety precautions. devices.
Remember: Safety First. 4. Use only an anti-static type solder removal device. Some solder
removal devices not classified as “anti-static” can generate
General Servicing Precautions electrical charges sufficient to damage ES devices.
1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate
source before; electrical charges sufficient to damage ES devices.
a. Removing or reinstalling any component, circuit board mod- 6. Do not remove a replacement ES device from its protective
ule or any other receiver assembly. package until immediately before you are ready to install it.
b. Disconnecting or reconnecting any receiver electrical plug or (Most replacement ES devices are packaged with leads electri-
other electrical connection. cally shorted together by conductive foam, aluminum foil or
c. Connecting a test substitute in parallel with an electrolytic comparable conductive material).
capacitor in the receiver. 7. Immediately before removing the protective material from the
CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective material
installation of electrolytic capacitors may result in an explo- to the chassis or circuit assembly into which the device will be
sion hazard. installed.
2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or circuit,
high voltage meter or other voltage measuring device (DVM, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace-
Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the
3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity suf-
4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropriate
(by volume) isopropyl alcohol (90 % - 99 % strength) tip size and shape that will maintain tip temperature within the
CAUTION: This is a flammable mixture. range or 500 °F to 600 °F.
Unless specified otherwise in this service manual, lubrication of 2. Use an appropriate gauge of RMA resin-core solder composed
contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks are Do not use freon-propelled spray-on cleaners.
correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500 °F to 600 °F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500 °F to 600 °F)
Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand against
ily by static electricity. Such components commonly are called the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there
and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo-
should be used to help reduce the incidence of component dam- nent lead and the foil.
age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush.
natively, obtain and wear a commercially available discharging
wrist strap device, which should be removed to prevent poten-
tial shock reasons prior to applying power to the unit under test.
Copyright © LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only
Only for training and service purposes
IC Remove/Replacement 3. Solder the connections.
Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced
which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to
cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures.
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique Circuit Board Foil Repair
as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
Removal board causing the foil to separate from or "lift-off" the board. The
1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed whenever
gently prying up on the lead with the soldering iron tip as the this condition is encountered.
solder melts.
2. Draw away the melted solder with an anti-static suction-type At IC Connections
solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the
the IC. following procedure to install a jumper wire on the copper pattern
Replacement side of the circuit board. (Use this technique only on IC connec-
1. Carefully insert the replacement IC in the circuit board. tions).
2. Carefully bend each IC lead against the circuit foil pad and
solder it. 1. Carefully remove the damaged copper pattern with a sharp
3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary).
(It is not necessary to reapply acrylic coating to the areas). 2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
"Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and
Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection.
1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper
as possible to the component body. pattern and let it overlap the previously scraped end of the
2. Bend into a "U" shape the end of each of three leads remaining good copper pattern. Solder the overlapped area and clip off
on the circuit board. any excess jumper wire.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding At Other Connections
leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern
long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the
each connection. installation of a jumper wire on the component side of the circuit
board.
Power Output, Transistor Device
Removal/Replacement 1. Remove the defective copper pattern with a sharp knife.
1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous
2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens.
3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern
board. break and locate the nearest component that is directly con-
4. Insert new transistor in the circuit board. nected to the affected copper pattern.
5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the
6. Replace heat sink. nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Diode Removal/Replacement Carefully crimp and solder the connections.
1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the
sible to diode body. it does not touch components or sharp edges.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.
Copyright © LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only
Only for training and service purposes
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
Copyright © LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only
Only for training and service purposes
No. Item Specification Remarks
3 Receiving system Analog : Upper Heterodyne ► DVB-T
Digital : COFDM, QAM - Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
► DVB-T2
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,
- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
► DVB-C
- Symbolrate :
4.0Msymbols/s to 7.2Msymbols/s
- Modulation :
16QAM, 64-QAM, 128-QAM and 256-QAM
► DVB-S/S2
- symbolrate
DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s
DVB-S (QPSK) : 2 ~ 45Msymbol/s
- viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10
4 Input Voltage AC 100 ~ 240V 50/60Hz
5 Screen Size 46.96 inches 1046.68(H) x 594.02(V) x 1.5(D)mm (Typ.)
FHD+240Hz
6 Aspect Ratio 16:9
7 Tuning System
8 Operating Environment 1) Temp : 0 ~ 40 deg
2) Humidity : ~ 80 %
9 Storage Environment 1) Temp : -20 ~ 60 deg
2) Humidity : ~ 85 %
Copyright © LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only
Only for training and service purposes
5. Component Video Input (Y, Cb/Pb, Cr/Pr)
No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock Porposed
1 720*480 15.73 60 13.5135 SDTV ,DVD 480I
2 720*480 15.73 59.94 13.5 SDTV ,DVD 480I
3 720*480 31.50 60 27.027 SDTV 480P
4 720*480 31.47 59.94 27.0 SDTV 480P
5 1280*720 45.00 60.00 74.25 HDTV 720P
6 1280*720 44.96 59.94 74.176 HDTV 720P
7 1920*1080 33.75 60.00 74.25 HDTV 1080I
8 1920*1080 33.72 59.94 74.176 HDTV 1080I
9 1920*1080 67.500 60 148.50 HDTV 1080P
10 1920*1080 67.432 59.94 148.352 HDTV 1080P
11 1920*1080 27.000 24.000 74.25 HDTV 1080P
12 1920*1080 26.97 23.976 74.176 HDTV 1080P
13 1920*1080 33.75 30.000 74.25 HDTV 1080P
14 1920*1080 33.71 29.97 74.176 HDTV 1080P
Copyright © LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only
Only for training and service purposes
7. HDMI Input
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC Proposed
HDMI-PC DDC
1 720*400 31.468 70.08 28.321 Х
2 640*480 31.469 59.94 25.17 VESA O
3 800*600 37.879 60.31 40.00 VESA O
4 1024*768 48.363 60.00 65.00 VESA(XGA) O
5 1360*768 47.72 59.8 84.75 WXGA O
6 1280*1024 63.595 60.0 108.875 SXGA O
7 1920*1080 67.5 60.00 148.5 WUXGA O
HDMI-DTV
1 640*480 31.469 / 31.5 59.94/ 60 25.125 1 SDTV 480P
2 720*480 31.469 / 31.5 59.94 / 60 27.00/27.03 2,3 SDTV 480P
3 720*576 31.25 50 27 17,18 SDTV 576P
4 720*576 15.625 50 27 21 SDTV 576I
5 1280*720 37.500 50 74.25 19 HDTV 720P
6 1280*720 44.96 / 45 59.94 / 60 74.17/74.25 4 HDTV 720P
7 1920*1080 33.72 / 33.75 59.94 / 60 74.17/74.25 5 HDTV 1080I
8 1920*1080 28.125 50.00 74.25 20 HDTV 1080I
9 1920*1080 26.97 / 27 23.97 / 24 74.17/74.25 32 HDTV 1080P
10 1920*1080 25 33 HDTV 1080P
11 1920*1080 33.716 / 33.75 29.976 / 30.00 74.25 34 HDTV 1080P
12 1920*1080 56.250 50 148.5 31 HDTV 1080P
13 1920*1080 67.43 / 67.5 59.94 / 60 148.35/148.50 16 HDTV 1080P
8. 3D Mode
8.1. RF Input
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom
2 1920*1080 28.125 50 74.25 HDTV 1080I Side by Side, Top & Bottom
Copyright © LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only
Only for training and service purposes
8.2.2. HDMI 1.4b
3D input proposed
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC Proposed
mode
Frame packing Secondary(SDTV 480P)
Line alternative (SDTV 480P)
1 640*480 31.469 / 31.5 59.94/ 60 25.125 1 Side-by-side(Full) (SDTV 480P)
Top-and-Bottom Secondary(SDTV 480P)
Side-by-side(half) Secondary(SDTV 480P
Frame packing Secondary(SDTV 480P)
Line alternative (SDTV 480P)
2 720*480 31.469 / 31.5 59.94 / 60 27.00/27.03 2,3 Side-by-side(Full) (SDTV 480P)
Top-and-Bottom Secondary(SDTV 480P)
Side-by-side(half) Secondary(SDTV 480P)
Frame packing Secondary(SDTV 576P)
Line alternative (SDTV 576P)
3 720*576 31.25 50 27 17,18 Side-by-side(Full) (SDTV 576P)
Top-and-Bottom Secondary(SDTV 576P)
Side-by-side(half) Secondary(SDTV 576P)
Frame packing Secondary(SDTV 576I)
Field alternative (SDTV 576I
4 720*576 15.625 50 27 21 Side-by-side(Full) (SDTV 576I
Top-and-Bottom Secondary(SDTV 576I)
Side-by-side(half) Secondary(SDTV 576I)
Frame packing Primary(HDTV 720P)
Line alternative (HDTV 720P)
5 1280*720 37.500 50 74.25 19 Side-by-side(Full) (HDTV 720P)
Top-and-Bottom Primary(HDTV 720P)
Side-by-side(half) Primary(HDTV 720P)
Frame packing Primary(HDTV 720P)
Line alternative (HDTV 720P)
6 1280*720 44.96 / 45 59.94 / 60 74.17/74.25 4 Side-by-side(Full) (HDTV 720P)
Top-and-Bottom Primary(HDTV 720P)
Side-by-side(half) Primary(HDTV 720P)
Frame packing Primary(HDTV 1080I)
Field alternative (HDTV 1080I)
7 1920*1080 33.72 / 33.75 59.94 / 60 74.17/74.25 5 Side-by-side(Full) (HDTV 1080I)
Top-and-Bottom Secondary(HDTV 1080I)
Side-by-side(half) Primary(HDTV 1080I)
Frame packing Primary(HDTV 1080I)
Field alternative (HDTV 1080I)
8 1920*1080 28.125 50.00 74.25 20 Side-by-side(Full) (HDTV 1080I)
Top-and-Bottom Secondary(HDTV 1080I)
Side-by-side(half) Primary(HDTV 1080I)
Frame packing Primary(HDTV 1080P)
Line alternative (HDTV 1080P)
9 1920*1080 26.97 / 27 23.97 / 24 74.17/74.25 32 Side-by-side(Full) (HDTV 1080P)
Top-and-Bottom Primary(HDTV 1080P)
Side-by-side(half) Primary(HDTV 1080P)
Frame packing Secondary(HDTV 1080P)
Line alternative (HDTV 1080P)
10 1920*1080 25 33 Side-by-side(Full) (HDTV 1080P)
Top-and-Bottom Secondary(HDTV 1080P)
Side-by-side(half) Secondary(HDTV 1080P)
Frame packing (HDTV 1080P)
Line alternative (HDTV 1080P)
11 1920*1080 33.716 / 33.75 29.976 / 30.00 74.25 34 Side-by-side(Full) (HDTV 1080P)
Top-and-Bottom (HDTV 1080P)
Side-by-side(half) Secondary(HDTV 1080P)
Top-and-Bottom Primary(HDTV 1080P)
12 1920*1080 56.250 50 148.5 31
Side-by-side(half) Secondary(HDTV 1080P)
Top-and-Bottom Primary(HDTV 1080P)
13 1920*1080 67.43 / 67.5 59.94 / 60 148.35/148.50 16
Side-by-side(half) Secondary(HDTV 1080P)
Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
8.3. RGB-PC Input(3D)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed
1 1920*1080 67.5 60 148.5 Side by Side, Top & Bottom HDTV 1080P
L R LLLLL R
1 L
R
L
Copyright © LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
ADJUSTMENT INSTRUCTION
1. Application Range 3.1.3. Adjustment
This specification sheet is applied to all of the LED LCD TV (1) Adjustment method
with LD23E chassis. - U sing RS-232, adjust items in the other shown in
"3.1.3.3)"
In case of keeping module is in the circumstance of below Ref.) ADC Adj. RS232C Protocol_Ver1.0
-20 °C, it should be placed in the circumstance of above 15
°C for 3 hours. (3) Adj. order
- aa 00 00 [Enter ADC adj. mode]
[Caution] - xb 00 04 [Change input source to Component1 (480i&
When still image is displayed for a period of 20 minutes or 1080p)]
longer (Especially where W/B scale is strong. Digital pattern - ad 00 10 [Adjust 480i&1080p Comp1]
13ch and/or Cross hatch pattern 09ch), there can some - xb 00 06 [Change input source to RGB(1024*768)]
afterimage in the black level area. - ad 00 10 [Adjust 1920*1080 RGB]
- ad 00 90 End adj.
Copyright © LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only
Only for training and service purposes
3.3. LAN Inspection 3.4. LAN PORT INSPECTION(PING TEST)
3.3.1. Equipment & Condition Connect SET → LAN port == PC → LAN Port
▪ Each other connection to LAN Port of IP Hub and Jig SET PC
Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
Only for training and service purposes
* Manual Download (Model Name and Serial Number) 3.6.2. Check the method of CI+ key value(RS232)
If the TV set is downloaded by OTA or service man, sometimes 1) Into the main ass’y mode(RS232: aa 00 00)
model name or serial number is initialized.(Not always) CMD 1 CMD 2 Data 0
It is impossible to download by bar code scan, so It need
Manual download. A A 0 0
1) Press the "Instart" key of Adjustment remote control.
2) Go to the menu "6.Model Number D/L" like below photo. 2) Check the mothed of CI+ key by command
3) Input the Factory model name(ex 42LD450-TA) or Serial (RS232: ci 00 20)
number like photo. CMD 1 CMD 2 Data 0
C I 2 0
3) Result value
i 01 OK 1d1852d21c1ed5dcx
CI+ Key Value
3) result value
- normally status for download : OKx
- abnormally status for download : NGx
Copyright © LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only
Only for training and service purposes
4. Manual Adjustment ▪ Reference
- HDMI1 ~ HDMI4 / RGB
* ADC adjustment is not needed because of OTP(Auto ADC
adjustment) - In the data of EDID, bellows may be different by S/W or
Input mode.
Copyright © LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only
Only for training and service purposes
# HDMI 3(C/S : 9D 9A) 4.2. White Balance Adjustment
EDID Block 0, Bytes 0-127 [00H-7FH]
4.2.1. Overview
0 1 2 3 4 5 6 7 8 9 A B C D E F ▪ W/B adj. Objective & How-it-works
00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 (1) Objective: To reduce each Panel's W/B deviation
10 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 (2) How-it-works : When R/G/B gain in the OSD is at 192, it
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
means the panel is at its Full Dynamic Range. In order to
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
prevent saturation of Full Dynamic range and data, one
40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
of R/G/B is fixed at 192, and the other two is lowered to
50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39
find the desired value.
60 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC
(3) Adjustment condition : normal temperature
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43
1) Surrounding Temperature : 25 °C ± 5 °C
2) Warm-up time: About 5 Min
EDID Block 1, Bytes 128-255 [80H-FFH
3) Surrounding Humidity : 20 % ~ 80 %
0 1 2 3 4 5 6 7 8 9 A B C D E F
00 02 03 37 F1 4E 10 9F 04 13 05 14 03 02 12 20 21
4.2.2. Equipment
10 22 15 01 26 15 07 50 09 57 07 78 03 0C 00 30 00
(1) Color Analyzer: CA-210 (LED Module : CH 14)
20 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16
(2) Adjustment Computer(During auto adj., RS-232C protocol
30 10 28 10 E3 05 03 01 02 3A 80 18 71 38 2D 40 58
is needed)
40 2C 45 00 A0 5A 00 00 00 1E 01 1D 80 18 71 1C 16
(3) Adjustment Remote control
50 20 58 2C 25 00 A0 5A 00 00 00 9E 01 1D 00 72 51
(4) Video Signal Generator MSPG-925F 720p/216-Gray
60 D0 1E 20 6E 28 55 00 A0 5A 00 00 00 1E 00 00 00
(Model: 217, Pattern: 78)
70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F1
-> Only when internal pattern is not available
# HDMI 4(C/S : 9D 8A) ▪ Color Analyzer Matrix should be calibrated using CS-1000.
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
4.2.3. Equipment connection MAP
00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
Co lo r Analyzer
10 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
Probe RS -232C
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C Co m p ut er
RS -232C
40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30 RS -232C
Copyright © LG Electronics. Inc. All rights reserved. - 16 - LGE Internal Use Only
Only for training and service purposes
Ex) wb 00 00 -> Begin white balance auto-adj. ▪ Adjustment condition and cautionary items
wb 00 10 -> Gain adj. 1) Lighting condition in surrounding area
ja 00 ff -> Adj. data Surrounding lighting should be lower 10 lux. Try to
jb 00 c0 isolate adj. area into dark surrounding.
... 2) Probe location
... : Color Analyzer(CA-210) probe should be within 10 cm
wb 00 1f → Gain adj. completed and perpendicular of the module surface (80° ~ 100°)
*(wb 00 20(Start), wb 00 2f(end)) → Off-set adj. 3) Aging time
wb 00 ff → End white balance auto-adj. - After Aging Start, Keep the Power ON status during 5
Minutes.
▪ Adj. Map - In case of LCD, Back-light on should be checked
Command Data Range Default using no signal or Full-white pattern.
Adj. item
(lower caseASCII) (Hex.) (Decimal)
CMD1 CMD2 MIN MAX 4.2.6. Reference(White balance adjusmtment coordinate
R Gain j g 00 C0 and color temperature)
G Gain j h 00 C0 ▪ Luminance : 216 Gray
B Gain j i 00 C0 ▪ Standard color coordinate and temperature using CS-1000
Cool
R Cut (over 26 inch)
G Cut
Coordinate
B Cut Mode Temp ∆uv
x y
R Gain j a 00 C0
G Gain j b 00 C0 Cool 0.269 0.273 13000 K 0.0000
B Gain j c 00 C0 Medium 0.285 0.293 9300 K 0.0000
Medium
R Cut Warm 0.313 0.329 6500 K 0.0000
G Cut
B Cut
▪ Standard color coordinate and temperature using CA-210(CH 9)
R Gain j d 00 C0
G Gain j e 00 C0 Coordinate
Mode Temp ∆uv
Warm B Gain j f 00 C0 x y
R Cut Cool 0.269 ± 0.002 0.273 ± 0.002 13000K 0.0000
G Cut
Medium 0.285 ± 0.002 0.293 ± 0.002 9300K 0.0000
Warm 0.313 ± 0.002 0.329 ± 0.002 6500K 0.0000
4.2.5. Adj. method
(1) Auto adj. method 4.2.7. ALELF & EDGE LED White balance table
1) Set TV in adj. mode using POWER ON key. - EDGE LED module change color coordinate because of
2) Zero calibrate probe then place it on the center of the aging time.
Display. - Apply under the color coordinate table, for compensated
3) Connect Cable.(RS-232C to USB) aging time.
4) Select mode in adj. Program and begin adj. - ALEF(LM860*)
5) When adj. is complete (OK Sign), check adj. status pre
mode. (Warm, Medium, Cool) Aging Cool Medium Warm
6) Remove probe and RS-232C cable to complete adj. GP4 time X y x y x y
▪ W/B Adj. must begin as start command “wb 00 00” , and (Min) 269 273 285 293 313 329
finish as end command “wb 00 ff”, and Adj. offset if need. 1 0-2 293 305 309 323 330 348
2 3-5 292 303 308 321 330 347
(2) Manual adjustment. method 3 6-9 291 302 307 320 329 346
1) Set TV in Adj. mode using POWER ON.
4 10-19 288 298 304 316 326 342
2) Zero Calibrate the probe of Color Analyzer, then place it
5 20-35 286 295 302 313 324 339
on the center of LCD module within 10 cm of the
surface. 6 36-49 285 293 301 311 322 337
3) Press ADJ key → EZ adjust using adj. R/C → 7. White- 7 50-79 283 291 299 309 321 335
Balance then press the cursor to the right(key ►). 8 80-149 282 289 298 308 320 334
(When right key(►) is pressed 216 Gray internal pattern 9 Over 150 281 287 298 306 319 332
will be displayed)
4) One of R Gain / G Gain / B Gain should be fixed at 192,
and the rest will be lowered to meet the desired value.
5) Adjustment is performed in COOL, MEDIUM, WARM 3
modes of color temperature.
▪ If internal pattern is not available, use RF input. In EZ
Adj. menu 7.White Balance, you can select one of 2
Test-pattern: ON, OFF. Default is inner(ON). By selecting
OFF, you can adjust using RF signal in 216 Gray pattern.
Copyright © LG Electronics. Inc. All rights reserved. - 17 - LGE Internal Use Only
Only for training and service purposes
4.3. EYE-Q function check 4.4. Local Dimming Function Check
(1) Turn on TV. Step 1) Turn on TV.
(2) Press EYE key of Adjustment remote control. Step 2) At the Local Dimming mode, module Edge Backlight
moving right to left Back light of IOP module moving.
Step 3) Confirm the Local Dimming mode.
Step 4) Press "exit" key.
(3) Cover the Eye Q II sensor on the front of the using your
hand and wait for 6 seconds.
Copyright © LG Electronics. Inc. All rights reserved. - 18 - LGE Internal Use Only
Only for training and service purposes
4.7. Wi-Fi Test 4.9. Inspection of light scattering
Step 1) Turn on TV ▪ Test Method
Step 2) Select Network Connection option in Network Menu. (1) Push “Power only” key.
(2) Push “HDMI” hot key.
(3) Inspect whether light scattering is occurred in internal
black pattern or not.
(4) Push “Power only” key.
▪ Test result
(1) After press LNB On key, ‘18 V LED’ and ‘22 KHz tone Result) If, The LED light is green and The Module shows
LED’ should be ON. normal stream → OK, Else → NG
(2) After press LNB OFF key, ‘18 V LED’ and ‘22 KHz tone
LED’ should be OFF.
Copyright © LG Electronics. Inc. All rights reserved. - 19 - LGE Internal Use Only
Only for training and service purposes
5. Tool Option selection 9. USB S/W Download(Service only)
▪ Method : Press "ADJ" key on the Adjustment remote control, (1) Put the USB Stick to the USB socket.
then select Tool option. (2) Automatically detecting update file in USB Stick.
- If your downloaded program version in USB Stick is Low,
it didn't work. But your downloaded version is High, USB
data is automatically detecting.(Download Version High &
6. Ship-out mode check(In-stop) Power only mode, Set is automatically Download)
▪ After final inspection, press "IN-STOP" key of the Adjustment (3) Show the message "Copying files from memory".
remote control and check that the unit goes to Stand-by
mode.
8. Audio
No. Item Min Typ Max Unit Remark
Audio practical 9.0 10.0 12.0 W Measurement condition
max Output, L/R
1.
(Distortion=10% 8.5 8.9 9.8 Vrms Auto Volume :Off
max Output) Audio EQ : Off
Speaker (8Ω Clear Voice : Off
2. 10.0 15.0 W Virtual Surround:Off
Impedance)
Measurement condition:
(1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation
(2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms
(3) RGB PC: 1 KHz sine wave signal 0.7 Vrms
Copyright © LG Electronics. Inc. All rights reserved. - 20 - LGE Internal Use Only
Only for training and service purposes
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
700
710
570
920
400
910
900
410
560
510
310
810
521
540
Dual Play
541
AG2
530
123
LV1
AG1
800
120
A22
122
A21
500
A2
580
501
301
300
Copyright © LG Electronics. Inc. All rights reserved. - 21 - LGE Internal Use Only
Only for training and service purposes
System Configuration
+3.3V_NORMAL
NVRAM
Clock for LG1152 C111
0.1uF
MAIN Clock(24Mhz) IC102
R1EX24256BSAS0A
for DiiVA(China)
C100
HP_DET I2C_SDA2
8pF
50V
Write Protection
X-TAL_1
A0 VCC I2C_SCL2
1 8 EPHY_INT
GND_1
R112
SMARTCARD_PWR_SEL
A0’h
24MHz
A2 SCL
X101
1M
SEL_USB1
SEL_USB2
SEL_USB3
SMARTCARD_DET
C101
4 5 I2C_SDA5 SMARTCARD_CLK
X-TAL_2
GND_2
XO_MAIN
R143 OPT R142
22
MOTOR_CLOSE_SW
I2C_SCL3 MOTOR_OPEN_SW
OPT 22 SC_DET
I2C_SDA3
MOTOR_CW
DiiVA_POD_CTL
MOTOR_CCW
MO_SENS_TO_MAIN_UP
MO_SENS_TO_MAIN_DOWN
Place to LVDS Wafer
EB_ADDR[0-14] EB_DATA[0-7]
OPTIC_FPGA_RESET
FPGA_LVDS_INFO
OPTIC_SERDES_RESET
R151 22 OLED_TCON_RESET
DiiVA_POD_CTL
FRC_RESET FRC3_RESET
FPGA_LVDS_INFO
R170
10K
EB_ADDR[3]
EB_ADDR[2]
EB_ADDR[1]
EB_ADDR[0]
EB_ADDR[14]
EB_ADDR[13]
EB_ADDR[12]
EB_ADDR[11]
EB_ADDR[10]
EB_ADDR[9]
EB_ADDR[8]
EB_ADDR[7]
EB_ADDR[6]
EB_ADDR[5]
EB_ADDR[4]
USB_CTL3
EB_BE_N1
EB_BE_N0
EB_DATA[7]
EB_DATA[6]
EB_DATA[5]
EB_DATA[4]
EB_DATA[3]
EB_DATA[2]
EB_DATA[1]
EB_DATA[0]
EB_OE_N
EB_WE_N
IRB_SPI_MISO
PLL SET[1:0] ==> Internal Pull-UP. N.C is high 3D_DEPTH_RESET +3.3V_NORMAL
IRB_SPI_MOSI
4.7K
R109
10K
10 : CPU clock(1152Mhz), Main0,1/2 DDR (792/672 Mhz)
11 : CPU clock(984Mhz), Main0,1/2 DDR (792/792 Mhz) IRB_SPI_SS
M25
M24
M23
N23
T27
T28
U27
U26
U28
J22
K22
J23
L26
L27
L25
N26
N27
M26
L28
L24
L23
K28
K27
K26
K25
K24
K23
V22
U22
T22
R22
P22
N22
M22
L22
T26
R28
R27
R26
P28
P27
P26
N28
R103 22
PLLSET0 I2C_SCL1 I2C_BE_SCL1
OPT
EB_CS3/GPIO64
EB_CS2/GPIO79
EB_CS1/GPIO78
EB_CS0/GPIO77
EB_OE_N
EB_WE_N
EB_WAIT
EB_BE_N1
EB_BE_N0
EB_ADDR17/GPIO84
EB_ADDR16/GPIO83
EB_ADDR15/GPIO82
EB_ADDR14
EB_ADDR13
EB_ADDR12
EB_ADDR11
EB_ADDR10
EB_ADDR9
EB_ADDR8
EB_ADDR7
EB_ADDR6
EB_ADDR5
EB_ADDR4
EB_ADDR3
EB_ADDR2
EB_ADDR1
EB_ADDR0
EB_DATA15
EB_DATA14
EB_DATA13
EB_DATA12
EB_DATA11
EB_DATA10
EB_DATA9
EB_DATA8
EB_DATA7
EB_DATA6
EB_DATA5
EB_DATA4
EB_DATA3
EB_DATA2
EB_DATA1
EB_DATA0
LOCAL_DIM_EN
EMMC_RST
BOOT MODE
"11" or "01" : NOR EMMC_CLK
A22 E28
"10" : eMMC XIN_MAIN XIN_MAIN EMMC_RST EMMC_CMD
"00" : NAND JTAG I/F FOR MAIN XO_MAIN R104 560 B22
XO_MAIN EMMC_CLK
F27
EMMC_DATA[0-7]
1% AB16 F26
OPM1 EMMC_CMD
+3.3V_NORMAL AB17 C26 EMMC_DATA[7]
OPM0 EMMC_DATA7
E27 EMMC_DATA[6]
EMMC_DATA6
AE3 E26 EMMC_DATA[5]
+3.3V_NORMAL SOC_RESET PORES_N EMMC_DATA5
D27 EMMC_DATA[4]
4.7K
R187
EMMC_DATA4
V23 D28 EMMC_DATA[3]
TRST_N0 TRST_N0 EMMC_DATA3
U25 C27 EMMC_DATA[2]
TMS0 TMS0 EMMC_DATA2
10K
10K
U24
TDO0 TDO0
OPT
OPT
Y22 R23
OPT
TRST_N1 NAND_CS1
R131
R132
AA22 P24
TMS1 NAND_CS0
AB20 N25
TRST_N0 TCK1 NAND_ALE
AB21 P23
TDI1 NAND_CLE
BOOT_MODE1 TDI0 W22 N24
TDO1 NAND_REN
TDO0 AB9 P25
PLLSET1 PLLSET1 NAND_WEN
AB8
+3.3V_NORMAL TMS0 PLLSET0 BOOT_MODE1 PLLSET0
+3.3V_NORMAL AB15 AC1
TCK0 +5V_NORMAL BOOT_MODE1 BOOT_MODE0 BOOT_MODE1 GPIO31 OPTIC_FPGA_RESET
AB14 V7
BOOT_MODE0 BOOT_MODE0 GPIO30
SOC_RESET W5
4.7K
GPIO29 OPTIC_SERDES_RESET
R188
R150 22 Y23 W4
ERROR_OUT EXT_INTR3/GPIO48 GPIO28 3D_DEPTH_RESET
G
10K
10K
OPT
100K
R202
W25 V6
EPHY_INT EXT_INTR2/GPIO63 GPIO27 /RST_PHY
BOOT_MODE0
SOC_RX
/USB_OCD2 R101 22 W24
W23
EXT_INTR1/GPIO62 IC100 GPIO26
V5
V4
OLED_TCON_RESET
D
EXT_INTR0/GPIO61 GPIO25
LG1152D-B1
OPT
OPT
R186
GPIO24
R133
R134
AA6 T6
UART1_RX UART1_RX GPIO21 For ISP
Q103 Y6 T5 4 3
2N7002K UART1_TX UART1_TX GPIO20
Delete PV
1/16W
BOOT_MODE0 AB5 T4
2.7K
R201
M_REMOTE_RX UART2_RX GPIO19 SC_DET
AA5 R6
5%
M_REMOTE_TX UART2_TX GPIO18 COMP1_DET DEBUG
+5V_NORMAL R5
GPIO17 HW_OPT_5
AB23 R4
+3.3V_NORMAL IRB_SPI_MISO SPI_DI0/GPIO39 GPIO16 HW_OPT_6
AB24 P6
IRB_SPI_MOSI SPI_DO0/GPIO38 GPIO15 M_RFModule_ISP
G
R203
100K
AA25 P5
OPT
G
I2C_SCL2 SCL1/GPIO58 GPIO5 HW_OPT_3
AC4 AD23
I2C_SDA2 SDA1/GPIO57 GPIO4 HP_DET
AD4 AE23
I2C_SCL3 SCL2/GPIO56 GPIO3 HDMI_S/W_RESET
D
AE4 AC22
FRC_EXTERNAL
DVB_C2_TUNER
DVB_T2_TUNER
SoC
ZORAN_FRC
DVB_S_TUNER
10K
10K
10K
10K
10K
10K
10K
3D_DEPTH
2N7002K
URSA5
OPTIC
OPT
I2C_SCL5
SC_VCC_SEL/GPIO88
SCL4/GPIO68
R110
R124
R138
R156
R100
R140
R145
R147
R152
R154
AD6
SC_DETECT/GPIO93
MODEL_OPT_1
SC_VCCEN/GPIO89
SD_DATA3/GPIO72
SD_DATA2/GPIO87
SD_DATA1/GPIO86
SD_DATA0/GPIO85
0 1 0 1 I2C_SDA5 SDA4/GPIO67
SC_DATA/GPIO92
SD_CD_N/GPIO75
SD_WP_N/GPIO74
USB_ANALOGTEST
AC6
SC_CLK/GPIO90
SC_RST/GPIO91
SD_CLK/GPIO76
SD_CMD/GPIO73
BT_ANALOGTEST
I2C_SCL6 SCL5/GPIO66
RMII_REF_CLK
CAM_INPACK_N
CAM_IOIS16_N
HW_OPT_0 AC7
RMII_CRS_DV
CAM_VCCEN_N
USB_TXR_RKL
I2C_SDA6 SDA5/GPIO65
CAM_IREQ_N
CAM_WAIT_N
BT_TXR_RKL
BackEnd 1
RMII_MDIO
RMII_TXEN
RMII_TXD1
RMII_TXD0
RMII_RXD1
RMII_RXD0
CAM_CE1_N
CAM_CE2_N
CAM_CD1_N
CAM_CD2_N
CAM_VS1_N
CAM_VS2_N
CAM_RESET
CAM_REG_N
BT_USB_DP
BT_USB_DM
HW_OPT_1
RMII_MDC
USB_DP1
USB_DM1
USB_DP2
USB_DM2
BackEnd 2
HW_OPT_2 HIGH LOW
Pannel Resol
HW_OPT_3 MODEL_OPT_2 FHD UD
OPTIC I/F
HW_OPT_4 MODEL_OPT_3 OPTIC NON_OPTIC
AD2
AB1
AB2
AB3
AC2
AC3
AE1
AD3
AD1
W26
V28
Y27
Y26
W28
W27
AA28
AB26
AA27
AA26
Y28
V27
V26
R25
U23
T25
T24
T23
R24
C22
C23
A23
B23
A24
B24
C24
A25
B27
A27
A26
B26
C25
B25
AA1
AA2
AA4
Y4
3D Depth IC
MODEL_OPT_4 3D DEPTH 3D_Depth_IC NON_3D_Depth_IC
HW_OPT_5
22
22
22
HW_OPT_9 Support
MODEL_OPT_9 C2 Tuner Not Support
Debug
/PCM_CE1
/PCM_CE2
CAM_CD1_N
CAM_CD2_N
CAM_IREQ_N
CAM_INPACK_N
CAM_WAIT_N
CAM_REG_N
PCM_RST
MODEL_OPT_10
R180
3.3K
R181
3.3K
R196
3.3K
R197
3.3K
R199
3.3K
R183
1.2K
R184
1.2K
USB_DM3
R178
2.2K
R179
2.2K
R182
2.2K
R195
2.2K
R198
3.3K
USB_HUB_IC_IN_DP
USB_HUB_IC_IN_DM
USB_DP3
Zoran FRC Support
EPHY_REFCLK
EPHY_CRS_DV
EPHY_MDC
EPHY_EN
EPHY_TXD1
EPHY_TXD0
EPHY_RXD1
EPHY_RXD0
Not Support
EPHY_MDIO
HW_OPT_10
(For UD)
NON_DVB_C2_TUNER
NON_DVB_T2_TUNER
NOT_ZORAN_FRC
NON_DVB_S_TUNER
HP_AMP_MUTE
10K
NON_3D DEPTH
10K
10K
10K
10K
10K
12507WS-04L
R111 FRC310K
10K
NON_CP_BOX
NON_OPTIC
10K CI
10K CI
I2C_SDA2
1GByte
10K CI
UD
I2C_SCL2
OPT
R126
I2C_SDA3
R139
PCM_5V_CTL
R158
R107
R141
R146
R148
R153
R155
1
R125
I2C_SCL3
+3.3V_NORMAL DEBUG
I2C_SDA4
R166
R167
R168
22
22
I2C_SCL4 UART1_RX 2
OPT
OPT
RCLAMP0502BA
I2C_SDA5
R173
D100
R174
R175
R176
MO_SENS_TO_MAIN_DOWN
MO_SENS_TO_MAIN_UP
MOTOR_CCW
MOTOR_CW
MOTOR_OPEN_SW
I2C_SCL5
MOTOR_CLOSE_SW
IR_B_RESET
3
I2C_SDA6
I2C_SCL6
UART1_TX 4
WIFI_DP
WIFI_DM
5
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Max 360mA
Max 12mA +1.0V_VDD
Max 35mA
+1.5V_Bypass Cap LG1152D
+1.0V_VDD
Max 1mA +1.0V_VDD AVDD10_VSB AVDD10_LVTX +1.5V_DDR
+1.0V_VDD AVDD10_DEMOD VDDC_XTAL VCC1.5V_MAIN
(18)
L305 IC100
BLM18PG121SN1D L300 Max 680mA
L302 L308 LG1152D-B1
L304 BLM18PG121SN1D BLM18PG121SN1D
BLM18PG121SN1D
0.1uF
0.1uF
BLM18PG121SN1D
C332 10uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VDD33
0.1uF
C302 10uF
0.1uF
0.1uF
C366 10uF
C369 10uF
C359 10uF
C305 10uF
C326 10uF
C312 10uF
U8 K13
ZD301
ESD_LG1152
VDD33_1 GND_21
C333
C338
5V
U9 K14
C317
C311
C329
C337
C346
C320
C323
C334
C342
C343
VDD33_2 GND_22
C368
C370
C313
U10 K15
C318
C321
VDD33_3 GND_23
V8 K16
VDD33_4 GND_24
V9 K17
On Package Decap : 0.1uF *3ea VDD33_USB V10
VDD33_5 GND_25
K18
On Package Decap : 0.1uF *1ea VDD33_6 GND_26
J21 K19
VCC1.5V_MAIN VCC1.5V_MAIN AVDD33_USB_1 GND_27
K21 K20
AVDD33_USB_2 GND_28
AA10 L7
Max 40mA Max 40mA AA11
AVDD33_BT_USB_1 GND_29
L12
R300
1K 1%
VREF_M0
R302
1K 1%
VREF_M1 AVDD33_BT_USB_2 GND_30
LG1152A VDD18
W18
W19
VDD18_1
GND_31
GND_32
L13
L14
L15
IC101 VDD18_2 GND_33
1000pF
0.1uF
Y18
1000pF
L16
0.1uF
1%
LG1152AN-B2 VDD18_3 GND_34
1%
Y19 L17
R301
R303
VDD18_4 GND_35
+1.8V_NORMAL AG28 L18
VDD18_LVTX
C362
VDD33 VDD18_A VDD18_5 GND_36
C308
C300
1K
AH27 L19
C350
1K
L326
BLM18PG121SN1D VDD18_6 GND_37
P1 J8 AA7 L21
VDD33_CVBS VDD18_LTX_1
0.1uF
VDD18_LTX_2 GND_39
C421 10uF
F18 J12 On Package Decap : 0.1uF *1ea On Package Decap : 0.1uF *1ea VDD18_LVRX_1 GND_42
AVDD33_HDMI_1 GND_29 AA13 M15
H16 J13 VDD18_MAIN_XTAL
AVDD33_HDMI_2 GND_30 VDD18_LVRX_2 GND_43
M16 J14 Max 40mA AB12 M16
VDD33_XTAL GND_31 VCC1.5V_DE VDD18_LVRX_3 GND_44
VDD25_VSB J15 VREF_M2 J28 M17
VDD25_CVBS L15
GND_32
K4
Max 340mA B28
VDD18_DISPPLL GND_45
M18
+1.5V_DDR
VDD25_VSB GND_33 VCC1.5V_DE VDD18_DR3PLL GND_46
R13 K5 G22 M19
VCC1.5V_DE
R304
1K 1%
VDD25_CVBS_2 GND_34 VDD18_MAIN_XTAL GND_47
R12 K6 N7
VDD25_REF VDD25_CVBS_1 GND_35 L301 GND_48
V13 K7 BLM18PG121SN1D F9 N12
VDD25_CVBS_3 GND_36 VDD15_M2_1 GND_49
P10 K8 G8 N13
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
AVDD25_REF GND_37 VDD15_M2_2 GND_50
G9 N14
0.1uF
R10 K9
1000pF
C303 10uF
VDD25_COMP
VDD15_M2_3 GND_51
1%
VDD25_COMP_3 GND_38 G10 N15
P9 K10
R305
R9
VDD25_COMP_1 GND_39
K11
Max 28mA G11
VDD15_M2_4 GND_52
N16
VDD25_COMP_2 GND_40 Max 100mA Max 250mA VDD25_VSB VDD15_M2_5 GND_53
C363
C306
C310
C316
C336
C340
+2.5V_NORMAL +2.5V_NORMAL H8 N17
C351
1K
V7 K12 VDD25_LVTX
VDD25_AUD VDD25_COMP_4 GND_41 +2.5V_NORMAL VDD25_CVBS VDD15_M2_6 GND_54
J16 K13 H9 N18
VDD25_AAD GND_42 VDD15_M2_7 GND_55
P6 K14 H10 N19
VDD25_AUD_1 GND_43 L313 L325 VCC1.5V_MAIN VDD15_M2_8 GND_56
P7 L4 L324 BLM18PG121SN1D BLM18PG121SN1D H11 P7
VDD25_LVTX VDD25_AUD_2 GND_44 BLM18PG121SN1D VDD15_M2_9 GND_57
V6 L5
0.1uF F22 P12
0.1uF
0.1uF
0.1uF
C375 10uF
C415 10uF
B18 L6 On Package Decap : 0.1uF *1ea G13 P13
C414 10uF
C418
VDD25_LVTX_3 GND_48
C385
L9 G17 P16
C417
C419
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VDDC10_1 GND_53 GND_66
AVDD10_VSB G7 L14 On Package Decap : 0.1uF *1ea On Package Decap : 0.1uF *1ea H13 R12
C301 10uF
C307 10uF
VDDC10_2 GND_54 VDD15_M0_10 GND_67
0.1uF
0.1uF
R15 M4 H14 R13
C309 10uF
ZD300
VDD15_M0_11 GND_68
ESD_LG1152
AVDD10_CVBS GND_55 H16 R14
K15 M5
5V
AVDD10_LVTX VDD15_M0_12 GND_69
AVDD10_VSB GND_56 H17 R15
C314
C319
C322
C325
C327
D17 M6
AVDD10_LVTX_1 GND_57 VDD15_M0_13 GND_70
D18 M7 H18 R16
C315
C324
AVDD10_LVTX_2 GND_58 VDD15_M0_14 GND_71
VDDC_XTAL N7 M8 H19 R17
AVDD10_LLPLL GND_59 VDD15_M0_15 GND_72
L16 M9 On Package Decap : 0.1uF *6ea H20 R18
VDDC_XTAL GND_60 VDD15_M0_16 GND_73
+2.5V_NORMAL M10 Max 250mA Max 10mA H21 R19
GND_61 VREF_M2 VDD15_M0_17 GND_74
G4 M11 VDD25_COMP VDD25_REF T7
VQPS GND_62 Max 50mA VREF_M1 GND_75
For HDCP OTP M12 +2.5V_NORMAL L4 T8
GND_63 +2.5V_NORMAL VDD25_AUD VREF_M2_0 GND_76
Will be change to LOW for MP N10 M13 Max 20mA +1.0V_VDD VREF_M0 F13 T9
AVSS25_REF GND_64 Max 1320mA VREF_M1_0 GND_77
AVSS25_REF K16 M14 +0.9V_VDD G12 T10
GND_XTAL GND_65 L315 L321 AVDD10_OSPREY VREF_M1_1 GND_78
D16 M15 L322 BLM18PG121SN1D BLM15BD121SN1 F14 T11
GND_1 GND_66 BLM18PG121SN1D L306 VREF_M0_0 GND_79
G5 M17 BLM18PG121SN1D AVDD10_OSPREY G15 T12
0.1uF
0.1uF
0.1uF
0.1uF
T13
C379 10uF
G8 N4
0.1uF
0.1uF
0.1uF
GND_81
C401 10uF
C341 10uF
G9 N5
0.1uF
GND_4 GND_69 VDDC10_OSPREY_1 GND_82
C347 10uF
G10 N6 M20 T15
GND_5 GND_70 VDDC10_OSPREY_2 GND_83
C386
C393
C400
C407
C345
C348
C349
G14 N9 BLM15BD121SN1 M27 T17
VDDC10_OSPREY_4 GND_85
C353
GND_7 GND_72 M28 T18
G15 N11
GND_8 GND_73 VDDC10_OSPREY_5 GND_86
H4 N12 AVSS25_REF N20 T19
GND_9 GND_74 VDDC10_OSPREY_6 GND_87
H5 N13 N21 T20
GND_10 GND_75 VDDC10_OSPREY_7 GND_88
H6 N14 On Package Decap : 0.1uF *1ea P20 T21
GND_11 GND_76 On Package Decap : 0.1uF *1ea On Package Decap : 0.1uF *3ea P21
VDDC10_OSPREY_8 GND_89
U7
H7 N15
GND_12 GND_77 On Package Decap : 0.1uF *1ea R20
VDDC10_OSPREY_9 GND_90
U11
H8 N16
GND_13 GND_78 VDDC10_OSPREY_10 GND_91
H9 P3 R21 U12
GND_14 GND_79 VDDC10_OSPREY_11 GND_92
H10 P4 +0.9V_VDD U13
GND_15 GND_80 Max 120mA +1.8V_NORMAL GND_93
H11 P5 Max 49mA K8 U14
+1.8V_NORMAL VDDC09_1 GND_94
GND_16 GND_81 VDD18_LVTX K9 U15
H12 P13 VDD18
H13
GND_17 GND_82
P15
Max 256mA Max 1mA K10
VDDC09_2 GND_95
U16
GND_18 GND_83
Max 35mA +3.3V_NORMAL VDD33_HDMI +3.3V_NORMAL
L316 VDDC09_3 GND_96
H14 P16 +3.3V_NORMAL VDD33_XTAL L312 BLM18PG121SN1D K11 U17
VDD33_CVBS BLM18PG121SN1D VDDC09_4 GND_97
GND_19 GND_84 L8 U18
0.1uF
0.1uF
H15 R3
VDDC09_5
0.1uF
GND_20 GND_85 GND_98
C395 10uF
J4 R16 L323 L9 U19
C374 10uF
GND_21 GND_86 L319 L309 VDDC09_6 GND_99
J5 R17 BLM18PG121SN1D BLM18PG121SN1D L10 U20
BLM18PG121SN1D VDDC09_7 GND_100
GND_22 GND_87
0.1uF
0.1uF
0.1uF
C410
C411
VDDC09_8 GND_101
C413 10uF
GND_23 GND_88
C371 10uF
M8 V11
C382
J7 T13
C398 10uF
C416
VDDC09_11 GND_104
C381
C403
C408
M11 V14
VDDC09_12 GND_105
N8 V15
On Package Decap:0.1uF *1ea VDDC09_13 GND_106
On Package Decap:0.1uF *1ea N9 V16
VDDC09_14 GND_107
N10 V17
VDDC09_15 GND_108
N11 V18
On Package Decap : 0.1uF *1ea On Package Decap : 0.1uF *1ea P8
VDDC09_16 GND_109
V19
VDDC09_17 GND_110
P9 V20
VDDC09_18 GND_111
P10 V21
+1.8V_NORMAL +1.8V_NORMAL Max 31mA VDDC09_19 GND_112
Max 93mA P11 W7
VDD18_MAIN_XTAL VDDC09_20 GND_113
VDD18_LVRX R8 W8
VDDC09_21 GND_114
L318 L314 R9 W9
BLM18PG121SN1D BLM18PG121SN1D VDDC09_22 GND_115
R10 W10
+0.9V_VDD VDDC09_23 GND_116
0.1uF
0.1uF
0.1uF
0.1uF
R11 W11
C397 10uF
VDDC09_24 GND_117
C378 10uF
Y7 W12
VDD09_LTX_1 GND_118
Y8 W13
VDD09_LTX_2 GND_119
MAIN_XTAL AF1 W14
C404
C384
C389
C304
VDD09_LTX_3 GND_120
F28 W15
AVDD09_DR3PLL GND_121
W16
GND_122
H22 W17
For HeatSinK, AL Block / SMD Top SMD Bottom VDD18 VDDC_MAIN_XTAL GND_123
For Tuner Sensitivity / Under DDR SMD TOP FOR ESD W20
GND_124
M315 M308 On Package Decap:0.1uF *1ea AA19 W21
M318 GASKET_8.0X6.0X7.5H SP_VQPS GND_125
MDS62110205 Y9
MDS62110205 M316 GND_126
MDS62110205 For secure BOOT OTP G23 Y10
M300 ATSC M321 ALBLOCK ESD
M304 HEATSINK ESD MDS62110217 Will be change to LOW for MP GND_MAIN_XTAL GND_127
M309 Y11
MDS62110213 MDS62110213 SMR-T-6-6.5-8 GND_128
MDS62110213 M312 M317 ESD G7 Y12
MDS62110206 OPT
MDS62110205 MDS62110205 GND_1 GND_129
H7 Y13
M305 HEATSINK GND_2 GND_130
M301 ALBLOCK ESD ESD M322 M320 H12 Y14
MDS62110213 GASKET_8.0X6.0X7.5H GND_3 GND_131
MDS62110213 M313 MDS62110205 H15 Y15
MDS62110217 GND_4 GND_132
+3.3V_NORMAL J7 Y16
M302
MDS62110205 ESD VDD33
Max 48.8mA GND_5 GND_133
ALBLOCK M306 ESD +3.3V_NORMAL J8 Y17
For Tuner Sensitivity / Under TUNER VDD33_USB GND_6 GND_134
MDS62110213 J9 Y20
MDS62110213 M314 M310
M319 L310 GND_7 GND_135
BLM18PG121SN1D J10 Y21
MDS62110205 MDS62110205 OPT GND_8 GND_136
M303 ATSC M307 MDS62110217 L317 J11 AA14
BLM18PG121SN1D
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
MDS62110213
GND_10
0.1uF
0.1uF
GND_138
MDS62110205 ESD J13 AA16
C396 10uF
GND_11 GND_139
J14 AA17
GND_12 GND_140
C388
C392
C399
C377
C383
C391
C394
C406
GND_14 GND_142
J17 AA21
GND_15 GND_143
J18 AB7
GND_16 GND_144
J19 AB10
On Package Decap : 0.1uF *1ea J20
GND_17 GND_145
AB11
GND_18 GND_146
K7 AB13
GND_19 GND_147
K12 AB22
GND_20 GND_148
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+5V_NORMAL C
+5V_NORMAL
Q506 B IC101 IC100
MMBT3904(NXP) DTV_ATV_SELECT LG1152AN-B2 LG1152D-B1
EU
Place these close to tuner EU EU
C510 E EU R507
R527
0.1uF 10K
TU_CVBS 10K
16V R592 R593 47CHB AR102
220 220 L1 AH2 AE27
INTR_GBB INTR_GBB STPI_CLK CHB_CLK
680pF EU EU L2 AG2 AE26
INTR_HDMI1 INTR_HDMI1 STPI_SOP CHB_SYNC
C506 IC500 L3 AF2 AD28
OPT INTR_AFE3CH INTR_AFE3CH STPI_VAL CHB_VAL
NLASB3157DFT2G AD27
E STPI_ERR CHB_ERR
K1 AH3 AD26 R200
100 R576 AUD_HMR00ARC AUD_HMR0ARC STPI_DATA CHB_DATA
L503 1uH EU ATV_OUT K2 AG3 AC28 47 CHB
SELECT B1 AUD_HMR0AMUTE AUD_HMR0AMUTE STPIO_CLK
SC_CVBS_IN 6 1 Q504 B EU
EU J2 AG4 AC26
MMBT3906(NXP) R599 AUD_HMR0ALRCK AUD_HMR0ALRCK STPIO_SOP/GPIO43
C508 EU C509 C J3 AF4 AB28 R556 33
R614 75 OPT
150pF 150pF VCC GND AUD_HMR0ABCK AUD_HMR0ABCK STPIO_VAL/GPIO42 USB_CTL2
EU 75 5 2 K3 AF3 AC27
50V 1% AUD_HMR0ASD4 AUD_HMR0ASD4 STPIO_ERR/GPIO41
EU H1 AH5 AB27
L504 1uH AUD_HMR0ASD3 AUD_HMR0ASD3 STPIO_DATA/GPIO40
A B0 H2 AG5
AV1_CVBS_IN 4 3 AUD_HMR0ASD2 AUD_HMR0ASD2
H3 AF5
5.5V D504
22K
AUD_SCART0_OUTRP
22K
SCART_Rout_SOC
0.01uF
0.01uF
R4 EU C2 AF8 J26 TPI_DATA[1]
SOC_RESET PORES_N AUD_MIC_LRCK AUD_MIC_LRCK TPI_DATA1
U3 H28 TPI_DATA[2]
AUAD_L_CH5_IN AUAD_L_CH5_IN TPI_DATA2
EU
R521 100
EU
V3 B3 AG9 H27 TPI_DATA[3]
SC_FB AUAD_R_CH5_IN AUAD_R_CH5_IN BB_TP_DATA0 BB_TPI_DATA0 TPI_DATA3
10K EU N3 V4 C3 AF9 H26 TPI_DATA[4]
R531
AUAD_L_CH4_IN
R532
C520
L9A_SCL AUAD_L_CH4_IN BB_TP_DATA1 BB_TPI_DATA1 TPI_DATA4
C521
EU
R522
EU
SC_ID M3 T3 D3 AE9 G28 TPI_DATA[5]
EU L9A_SDA AUAD_R_CH4_IN AUAD_R_CH4_IN BB_TP_DATA2 BB_TPI_DATA2 TPI_DATA5
NON SCART NON SCART EU U5 E3 AD9 G27 TPI_DATA[6]
R525 R524 AUAD_L_CH3_IN AUAD_L_CH3_IN BB_TP_DATA3 BB_TPI_DATA3 TPI_DATA6
R525-*1 R524-*1 T5 F3 AC9 G26
75 2.7K TPI_DATA[7]
0 0 AUAD_R_CH3_IN AUAD_R_CH3_IN BB_TP_DATA4 BB_TPI_DATA4 TPI_DATA7
U6 D4 AE10
AUAD_L_CH2_IN BB_TP_DATA5 BB_TPI_DATA5
R571 33 C549 0.047uF U14 T6 E4 AD10
CVBS_IN1 AUAD_R_CH2_IN TPI_SOP BB_TP_DATA6 BB_TPI_DATA6 TPO_CLK
R572 33 C550 0.047uF T14 U7 F4 AC10 D24
CVBS_IN2 AUAD_L_CH1_IN TPI_CLK BB_TP_DATA7 BB_TPI_DATA7 TPO_CLK TPO_SOP
R573 100 C551 0.047uF V15 T7 D5 AE11 E23
CVBS_IN3 AUAD_R_CH1_IN TPO_ERR BB_TP_VAL BB_TPI_VAL TPO_SOP TPO_VAL
R559 68 C552 0.047uF U15 E5 AD11 D25
L501 CVBS_VCM TPO_VAL BB_TP_SOP BB_TPI_SOP TPO_VAL TPO_ERR
R574 100 C553 0.047uF T15 T4 10K R534 2.2uF C537 F5 AC11 D23
DSUB_B+ CVBS_IN4 AUAD_REFN TPO_SOP BB_TP_ERR BB_TPI_ERR TPO_ERR TPO_DATA[0-7]
L500 R551 33 C554 0.047uF U16 U4 10K R520 2.2uF C547 D6 AE12 H23 TPO_DATA[0]
CVBS_IN5 AUAD_REFP TPO_CLK BB_TP_CLK BB_TPI_CLK TPO_DATA0
DSUB_G+ R557 33 C555 0.047uF V14 V5 2.2uF C548 G25 TPO_DATA[1]
CVBS_IN6 AUAD_VR_OUT TPO_DATA1
L502 R575 33 C556 0.047uF T16 CHB_DATA A5 AH11 G24 TPO_DATA[2]
DSUB_R+ CB_IN BB_SDA_I BB_SDA_I TPO_DATA2
R558 68 C557 0.047uF V16 R7 JDVR_SCLK B5 AG11 F25 TPO_DATA[3]
5.5V D501
5.5V D502
5.5V D500
OPT
OPT
OPT
75
75
75
C607
10pF
10pF
100pF
R528
R529
R530
OPT
10K
R555
75
75
OPT
75
OPT
R595
R600
C546
10pF
C524
10pF
R594
10pF
5.5V D506
OPT
5.5V D503
OPT
OPT
R606 1% 75
R605 1% 75
R604 1% 75
10pF
C578
OPTIC_BACK_CHANNEL
OPT Near Place Scart AMP AAD_GC4 AAD_GC4 TXA1N SOC_TXA1N
GND_1
D12 AE18 P1
EU EU 8pF AAD_DATAEN AAD_DATAEN TXA1P SOC_TXA1P
XIN_SUB E12 AD18 P3
SCART_AMP_R_FB AAD_DATA0 AAD_DATA0 TXA2N SOC_TXA2N
10K C513 F12 AC18 R3
AAD_DATA1 AAD_DATA1 TXA2P SOC_TXA2P
2
F13 AC19 T2
3
SOC_TXA3N
1M
GND_2
100K
R538
EU
100K
R549
EU
EU
C604 SOC_TXB3N
22K
C559
L507 C502 R510 HSR_BP1 HS_RX2_BP
EU 2.2uF 13K C16 AF22
SC_L_IN EU AUAD_L_CH4_IN
EU EU HSR_CM1 HS_RX2_CM
C572 C576
OPT
R602 EU EU C15 AF21
R516 75K HSR_CP1 HS_RX2_CP
2.2uF
330pF 330pF L510 C503 R511 B16 AG22
470K
50V 50V 2.2uF 13K AUAD_R_CH4_IN HSR_CLKM1 HS_RX2_CLKM
OPT EU EU A16 AH22
EU EU EU HSR_CLKP1 HS_RX2_CLKP
R517 100K A17 AH23
EU C582 C588 HSR_DM1 HS_RX2_DM
330pF 330pF B17 AG23
SC_R_IN R608 HSR_DP1 HS_RX2_DP
50V 50V C18 AF24
470K HSR_EM1 HS_RX2_EM
L508 OPT C504 C17 AF23
AV1_L_IN 2.2uF R512 13K AUAD_L_CH3_IN HSR_EP1 HS_RX2_EP
R603
C574 C577 R518 75K
470K L511 C505
560pF 100pF
2.2uF R513 13K AUAD_R_CH3_IN
50V 50V
OPT R519 100K
R609
AV1_R_IN
470K
C586
560pF
50V
C589
100pF
50V
LG1152A LG1152D
OPT
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC100 IC700 IC703 M0_1_DDR_VREFCA
LG1152D-B1 H5TQ2G83BFR-PBC M0_DDR_VREFCA
H5TQ2G83BFR-PBC
VCC1.5V_MAIN VCC1.5V_MAIN
M0_DDR_VREFDQ M0_1_DDR_VREFDQ
D18 DDR3 DDR3
M0_DDR_A0 M0_DDR_A0 K4 J9 M0_1_DDR_VREFCA K4 J9
E17 M0_DDR_A0 A0 2Gbit VREFCA M0_DDR_VREFCA M0_DDR_A0 A0
2Gbit VREFCA
M0_DDR_A1 M0_DDR_A1 L8 L8
E18 M0_DDR_A1 A1 M0_DDR_A1 A1
R722
1K 1%
L4 L4
R730
1K 1%
M0_DDR_A2 M0_DDR_A2
E20 M0_DDR_A2 A2 M0_DDR_A2 A2
M0_DDR_A3 M0_DDR_A3 K3 E2 K3 E2
E16 M0_DDR_A3 A3 VREFDQ M0_DDR_A3 A3 VREFDQ
M0_DDR_A4 M0_DDR_A4 L9 L9
D20 M0_DDR_A4 A4 M0_DDR_A4 A4
M0_DDR_A5 M0_DDR_A5 L3 L3
0.1uF
M0_DDR_A5 VCC1.5V_MAIN M0_DDR_A5 VCC1.5V_MAIN
1000pF
VCC1.5V_MAIN A5 A5
0.1uF
F16 R720 R739
1000pF
M9 H9 M9 H9
1%
M0_DDR_A6
1%
M0_DDR_A6 M0_DDR_A6 M0_DDR_A6
F19 A6 ZQ A6 ZQ
R723
M3 M3
R731
M0_DDR_A7 M0_DDR_A7 240 240
E15 M0_DDR_A7 A7 1% M0_DDR_A7 A7 1%
M0_DDR_A8 N9 N9
C728
M0_DDR_A8
C747
R709
C724
1K
M0_DDR_A8 M0_DDR_A8
C732
1K
D19 A8 A8
M0_DDR_A9 M0_DDR_A9 10K M4 A3 M4 A3
D14 M0_DDR_A9 A9 VDD_1 M0_DDR_A9 A9 VDD_1
M0_DDR_A10 M0_DDR_A10 H8 A10 H8 A10 C758 0.1uF
E14 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A10 A10/AP VDD_2
M0_DDR_A11 M0_DDR_A11 M0_DDR_RESET_N M8 D8 C706 0.1uF M8 D8
D17 M0_DDR_A11 A11 VDD_3 M0_DDR_A11 A11 VDD_3
M0_DDR_A12 M0_DDR_A12 K8 G3 C707 0.1uF K8 G3
F18 M0_DDR_A12 A12/BC VDD_4 M0_DDR_A12 A12/BC VDD_4 0.1uF
M0_DDR_A13 N4 G9 C708 0.1uF N4 G9 C746
M0_DDR_A13 M0_DDR_A13 M0_DDR_A13
D16 A13 VDD_5 A13 VDD_5
M0_DDR_A14 M0_DDR_A14 N8 K2 C709 0.1uF N8 K2
M0_DDR_A14 A14 VDD_6 M0_DDR_A14 A14 VDD_6 C723 0.1uF
K10 C710 0.1uF K10
F20 VDD_7 VDD_7
M0_DDR_BA0 M0_DDR_BA0 M0_DDR_CLK M2 C711 0.1uF M2 C760 0.1uF
D15 VDD_8 VDD_8
M0_DDR_BA1 M0_DDR_BA1 J3 M10 C712 0.1uF J3 M10
F17 R705 M0_DDR_BA0 BA0 VDD_9 M0_DDR_BA0 BA0 VDD_9
M0_DDR_BA2 M0_DDR_BA2 K9 VCC1.5V_MAIN VCC1.5V_MAIN K9
200 M0_DDR_BA1 BA1 M0_DDR_BA1 BA1 C751 0.1uF
J4 J4
A17 M0_DDR_BA2 BA2 M0_DDR_BA2 BA2
M0_DDR_CLK R700 0 M0_DDR_CLK B10 M0_1_DDR_VREFDQ B10
M0_DDR_CLKN VDDQ_1 M0_DDR_VREFDQ VDDQ_1 C761 0.1uF
A18 R701 0
M0_DDR_CLKN M0_DDR_CLKN F8 C2 F8 C2
F15 M0_DDR_CLK CK VDDQ_2 M0_DDR_CLK CK VDDQ_2
R724
1K 1%
G8 E3 G8 E3
R732
1K 1%
M0_DDR_CKE M0_DDR_CKE
M0_DDR_CLKN CK VDDQ_3 M0_DDR_CLKN CK VDDQ_3
G10 E10 G10 E10 C756 0.1uF
F21 M0_DDR_CKE CKE VDDQ_4 M0_DDR_CKE CKE VDDQ_4
M0_DDR_ODT M0_DDR_ODT
D22
M0_DDR_RASN M0_DDR_RASN H3 H3
0.1uF
1000pF
CS CS
0.1uF
E21
1000pF
M0_DDR_CLK G2 G2
1%
M0_DDR_CASN
1%
M0_DDR_CASN M0_DDR_ODT M0_DDR_ODT
D21 ODT ODT
R725
F4 F4
R733
M0_DDR_WEN M0_DDR_WEN
R706 M0_DDR_RASN RAS M0_DDR_RASN RAS
G4 G4
C729
C748
C725
1K
200 M0_DDR_CASN M0_DDR_CASN
C733
1K
E19 CAS CAS
M0_DDR_RESET_N M0_DDR_RESET_N H4 H4
M0_DDR_WEN WE M0_DDR_WEN WE
A1 A1
B20 M0_DDR_CLKN NC_S1 NC_S1
M0_DDR_DQSL_P M0_DDR_DQSL_P N3 A11 N3 A11
A20 M0_DDR_RESET_N RESET NC_S2 M0_DDR_RESET_N RESET NC_S2
M0_DDR_DQSL_N M0_DDR_DQSL_N N1 N1
NC_S3 NC_S3
N11 N11
B16 NC_S4 NC_S4
M0_DDR_DQSU_P M0_DDR_DQSU_P C4 C4
C16 M0_DDR_DQSL_P DQS M0_DDR_DQSU_P DQS
M0_DDR_DQSU_N M0_DDR_DQSU_N D4 D4
M0_DDR_DQSL_N DQS M0_DDR_DQSU_N DQS
C19
M0_DDR_DML M0_DDR_DML B8 A2 B8 A2
C15 M0_DDR_CKE M0_DDR_DML DM/TDQS VSS_1 M0_DDR_DMU DM/TDQS VSS_1
M0_DDR_DMU M0_DDR_DMU A8 A9 A8 A9
NF/TDQS VSS_2 NF/TDQS VSS_2
B2 B2
C20 R742 VSS_3 VSS_3
M0_DDR_DQ0 M0_DDR_DQ0 D9 D9
B19 10K VSS_4 VSS_4
M0_DDR_DQ1 M0_DDR_DQ1 F3 F3
C21 VSS_5 VSS_5
M0_DDR_DQ2 M0_DDR_DQ2 F9 F9
B18 VSS_6 VSS_6
M0_DDR_DQ3 M0_DDR_DQ3 B4 J2 B4 J2
A21 M0_DDR_DQ0 DQ0 VSS_7 M0_DDR_DQ10 DQ0 VSS_7
M0_DDR_DQ4 M0_DDR_DQ4 C8 J10 C8 J10
C18 M0_DDR_DQ1 DQ1 VSS_8 M0_DDR_DQ13 DQ1 VSS_8
M0_DDR_DQ5 M0_DDR_DQ5 C3 L2 C3 L2
B21 M0_DDR_DQ6 DQ2 VSS_9 M0_DDR_DQ14 DQ2 VSS_9
M0_DDR_DQ6 M0_DDR_DQ6 C9 L10 C9 L10
A19 M0_DDR_DQ7 DQ3 VSS_10 M0_DDR_DQ11 DQ3 VSS_10
M0_DDR_DQ7 M0_DDR_DQ7 E4 N2 E4 N2
B17 M0_DDR_DQ4 DQ4 VSS_11 M0_DDR_DQ15 DQ4 VSS_11
M0_DDR_DQ8 M0_DDR_DQ8 E9 N10 E9 N10
C14 M0_DDR_DQ3 DQ5 VSS_12 M0_DDR_DQ9 DQ5 VSS_12
M0_DDR_DQ9 M0_DDR_DQ9 D3 D3
A16 M0_DDR_DQ2 DQ6 M0_DDR_DQ8 DQ6
M0_DDR_DQ10 M0_DDR_DQ10 E8 E8
B14 M0_DDR_DQ5 DQ7 M0_DDR_DQ12 DQ7
M0_DDR_DQ11 M0_DDR_DQ11 B3 B3
B15 VSSQ_1 VSSQ_1
M0_DDR_DQ12 M0_DDR_DQ12 A4 B9 A4 B9
A14 NC_1 VSSQ_2 NC_1 VSSQ_2
M0_DDR_DQ13 M0_DDR_DQ13 F2 C10 F2 C10
C17 NC_2 VSSQ_3 NC_2 VSSQ_3
M0_DDR_DQ14 M0_DDR_DQ14 F10 D2 F10 D2
A15 NC_3 VSSQ_4 NC_3 VSSQ_4
M0_DDR_DQ15 M0_DDR_DQ15 H2 D10 H2 D10
E22 SIGN50005 240 R704 NC_4 VSSQ_5 NC_4 VSSQ_5
M0_DDR_ZQCAL H10 H10
1% NC_5 NC_5
J8 J8
NC_6 NC_6
1K 1%
E9 L4 L4
R734
1K 1%
M1_DDR_A1 M1_DDR_A1 M1_DDR_A2 A2 M1_DDR_A2 A2
F10 K3 E2 K3 E2
M1_DDR_A2 M1_DDR_A2 M1_DDR_A3 A3 VREFDQ M1_DDR_A3 A3 VREFDQ
F12 L9 L9
M1_DDR_A3 M1_DDR_A3 M1_DDR_A4 A4 M1_DDR_A4 A4
F8 L3 L3
0.1uF
M1_DDR_A4 M1_DDR_A5 VCC1.5V_MAIN M1_DDR_A5 VCC1.5V_MAIN
1000pF
M1_DDR_A4 VCC1.5V_MAIN A5 A5
0.1uF
R721 R740
1000pF
D11 M9 H9 M9 H9
1%
1%
M1_DDR_A5 M1_DDR_A5 M1_DDR_A6 A6 ZQ M1_DDR_A6 A6 ZQ
R727
E8 M3 M3
R735
240 240
M1_DDR_A6 M1_DDR_A6 M1_DDR_A7 A7 1% M1_DDR_A7 A7 1%
E11 N9 N9
C730
C749
R710
C726
1K
C734
1K
M1_DDR_A7 A8 A8
E7 10K M4 A3 M4 A3
M1_DDR_A8 M1_DDR_A8 M1_DDR_A9 A9 VDD_1 M1_DDR_A9 A9 VDD_1
D10 H8 A10 H8 A10 C757 0.1uF
M1_DDR_A9 M1_DDR_A9 M1_DDR_A10 A10/AP VDD_2 M1_DDR_A10 A10/AP VDD_2
C4 M1_DDR_RESET_N M8 D8 C713 0.1uF M8 D8
M1_DDR_A10 M1_DDR_A10 M1_DDR_A11 A11 VDD_3 M1_DDR_A11 A11 VDD_3 C752 0.1uF
C5 K8 G3 C714 0.1uF K8 G3
M1_DDR_A11 M1_DDR_A11 M1_DDR_A12 A12/BC VDD_4 M1_DDR_A12 A12/BC VDD_4
D8 N4 G9 C715 0.1uF N4 G9 0.1uF
M1_DDR_A12 M1_DDR_A12 M1_DDR_A13 A13 VDD_5 M1_DDR_A13 A13 VDD_5 C753
E10 N8 K2 C716 0.1uF N8 K2
M1_DDR_A13 M1_DDR_A13 M1_DDR_A14 A14 VDD_6 M1_DDR_A14 A14 VDD_6 C754 0.1uF
C7 K10 C717 0.1uF K10
M1_DDR_A14 M1_DDR_A14 VDD_7 VDD_7
M1_DDR_CLK M2 C718 0.1uF M2
VDD_8 VDD_8
E12 J3 M10 C719 0.1uF J3 M10 C755 0.1uF
M1_DDR_BA0 M1_DDR_BA0 R707 M1_DDR_BA0 BA0 VDD_9 M1_DDR_BA0 BA0 VDD_9
F7 K9 VCC1.5V_MAIN VCC1.5V_MAIN K9
M1_DDR_BA1 M1_DDR_BA1 200 M1_DDR_BA1 BA1 M1_DDR_BA1 BA1
D9 J4 J4
M1_DDR_BA2 M1_DDR_BA2 M1_DDR_BA2 BA2 M1_DDR_BA2 BA2
B10 M1_1_DDR_VREFDQ B10 C745 0.1uF
M1_DDR_CLKN VDDQ_1 M1_DDR_VREFDQ VDDQ_1
A9 R702 0 F8 C2 F8 C2
M1_DDR_CLK M1_DDR_CLK M1_DDR_CLK CK VDDQ_2 M1_DDR_CLK CK VDDQ_2
R728
1K 1%
B9 R703 G8 E3 G8 E3
R736
1K 1%
M1_DDR_CLKN 0 M1_DDR_CLKN M1_DDR_CLKN M1_DDR_CLKN
CK VDDQ_3 CK VDDQ_3
D7 G10 E10 G10 E10 C759 0.1uF
M1_DDR_CKE M1_DDR_CKE M1_DDR_CKE CKE VDDQ_4 M1_DDR_CKE CKE VDDQ_4
D13 H3 H3
0.1uF
M1_DDR_ODT
1000pF
M1_DDR_ODT CS 0.1uF CS
1000pF
C13 M1_DDR_CLK G2 G2
1%
1%
E13 F4 F4
R737
C750
C727
1K
IC100 N3 M8 M2_DDR_VREFDQ
M2_DDR_A0 A0 VREFCA
LG1152D-B1 P7
M2_DDR_A1 A1
P3
M2_DDR_A2 A2
N2 H1
M2_DDR_A3 A3 VREFDQ
D1 P8
M2_DDR_A0 M2_DDR_A0 M2_DDR_A4 A4
K4 P2
M2_DDR_A1 M2_DDR_A1 M2_DDR_A5 A5
D2 R8 L8 R738
SIGN50000 240
M2_DDR_A2 M2_DDR_A2 M2_DDR_A6 A6 ZQ
E5 R2 VCC1.5V_DE
M2_DDR_A3 M2_DDR_A3 M2_DDR_A7 A7
H6 T8
M2_DDR_A4 M2_DDR_A4 M2_DDR_A8 A8
E4 R3 B2
M2_DDR_A5 M2_DDR_A5 M2_DDR_A9 A9 VDD_1
J4 L7 D9 C722
M2_DDR_A10 A10/AP VDD_2 0.1uF
M2_DDR_A6 M2_DDR_A6 R7 G7
DDR3 1.5V bypass Cap - Place these caps near Memory
R718
1K 1%
1K 1%
M2_DDR_DQ6 B1
L3
M2_DDR_DQ7 M2_DDR_DQ7 VSSQ_1
J3 D7 B9
M2_DDR_DQ8 M2_DDR_DQ8 M2_DDR_DQ8 DQU0 VSSQ_2
G1 C3 D1
M2_DDR_DQ9 M2_DDR_DQ9 M2_DDR_DQ9 DQU1 VSSQ_3
K2 C8 D8
0.1uF
0.1uF
1000pF
1000pF
1%
F3 C2 E2
M2_DDR_DQ11 M2_DDR_DQ11 DQU3 VSSQ_5
R713
R719
M2_DDR_DQ11 A7 E8
J2 M2_DDR_DQ12
M2_DDR_DQ12 M2_DDR_DQ12 DQU4 VSSQ_6
A2
C701
C703
G2 F9
C700
C702
1K
1K
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+5V_CI_ON
CI HOST I/F
0.1uF
100 /CI_DET1 DAT3
C904
+5V_CI_ON /CI_CD1 R6214 36 2 CI_DATA[3]
CI TS_OUT3 DAT4 0
CI_TS_DATA[3] 37 3 CI_DATA[4]
TS_OUT4 DAT5 R913
OPT
38 4 CI_DATA[5] DIR VCC CI 16V
CI_TS_DATA[4] +5V_CI_ON 1 20
TS_OUT5 39 5 DAT6 CI_DATA[6]
R6204 R6206 CI_TS_DATA[5] CI
10K 10K TS_OUT6 40 6 DAT6 CI_DATA[7]
CI_DATA[0-7]
CI_TS_DATA[6] AR909 A0 OE
OPT OPT TS_OUT7 41 7 /CARD_EN1 CI R6224 22 R6245 CI_DATA[0] 33 2 19
CI_TS_DATA[7] /PCM_CE1
CARD_EN2 ADDR10 CI_ADDR[10] 10K CI_DATA[1]
/PCM_CE2 42 8 CI_ADDR[10] OPT
/PCM_IORD
R6249 0 VS1 43 9 /O_EN CI_DATA[2] A1 B0 EB_DATA[0]
/PCM_IOWR CI_VS1 /PCM_OE
OPT IORD CI_DATA[3] 3 18
44 10 ADDR11 CI_ADDR[11]
CI_ADDR[11] +5V_CI_ON
CI_IN_TS_DATA[0-7] IOWR 45 11 ADDR10 CI_ADDR[9]
CI_ADDR[9] A2 B1 EB_DATA[1]
TS_IN_SYN 46 12 ADDR8 CI_ADDR[8] 4 17
CI_ADDR[8]
CI_IN_TS_DATA[0] TS_IN0 ADDR13 CI_ADDR[13] R6244 R6246
47 13 CI_ADDR[13] 10K 10K
CI_IN_TS_DATA[1] TS_IN1 48 14 ADDR14 CI_ADDR[14] A3 B2 EB_DATA[2]
CI_ADDR[14] CI OPT 5 16
CI_IN_TS_DATA[2] TS_IN2 49 15 /WR_EN
/PCM_WE
CI_IN_TS_DATA[3] TS_IN3 /IRQA R6243 22 CI
50 16 /PCM_IRQA AR910
VCC 51 17 VCC C6205 0.1uF
CI C6206
0.1uF
OPT CI_DATA[4] 33 A4
6 CI 15
B3 EB_DATA[3]
EB_DATA[0-7]
+5V_CI_ON R6213 0 VPP VPP R6216 0 CI CI_DATA[5]
52 18 16V
CI_IN_TS_DATA[4] OPT TS_IN4 53 19 TS_IN_VAL OPT CI_DATA[6] A5 B4 EB_DATA[4]
CI_IN_TS_DATA[5] TS_IN5 CI_DATA[7] 7 14
54 20 TS_IN_CLK
CI_IN_TS_DATA[6] TS_IN6 55 21 ADDR12 CI_ADDR[12]
R6211 R6205 R6207 CI_ADDR[12] A6 B5 EB_DATA[5]
10K 10K 10K CI_IN_TS_DATA[7] TS_IN7 56 22 ADDR7 CI_ADDR[7] 8 13
OPT CI_ADDR[7]
OPT CI TS_OUT_CLK 57 23 ADDR6 CI_ADDR[6]
CI_TS_CLK CI_ADDR[6]
R6202 22 CI CI_RESET 58 24 ADDR5 CI_ADDR[5] A7 B6 EB_DATA[6]
PCM_RST CI_ADDR[5] 9 12
R6203 22 CI CI_WAIT 59 25 ADDR4 CI_ADDR[4]
/PCM_WAIT CI_ADDR[4] CI_DATA[0-7]
R6200 22 OPT INPACK 60 26 ADDR3 CI_ADDR[3]
PCM_INPACK CI_ADDR[3] GND B7 EB_DATA[7]
R6212 0 CI REG 61 27 ADDR2 CI_ADDR[2] 10 11
/PCM_REG CI_ADDR[2]
TS_OUT_VAL 62 28 ADDR1 CI_ADDR[1]
CI_TS_VAL CI_ADDR[1]
TS_OUT_SYN 63 29 ADDR0 CI_ADDR[0]
CI_TS_SYNC CI_ADDR[0]
TS_OUT0 DAT0 CI_DATA[0] EB_DATA[0-7]
CI_TS_DATA[0] 64 30
TS_OUT1 65 31 DAT1 CI_DATA[1] +5V_CI_ON
CI_TS_DATA[1]
CI_VS1 TS_OUT2 DAT2 CI_DATA[2]
CI_TS_DATA[2] 66 32
PCM_INPACK /CI_CD2 R6215 CI 100 /CI_DET2 67 33 /IO_BIT R6217 10K +3.3V_NORMAL
GND 68 34 GND OPT
/PCM_CE2 IC905
R6210 0 74LVC1G00GW
G2 69 G1
OPT
CI
B 1 5 VCC
0.1uF
/PCM_OE
C903
WE=>OE
CI_IN_TS_VAL A 2
16V
IOWE=>IORD /PCM_IORD
CI_IN_TS_CLK
CI_IN_TS_SYNC GND 3 4 Y
DIR
CI
CI CI
TPO_DATA[0-7] CI
AR911 AR915
AR904 33 33
TPO_DATA[0] 33 CI_ADDR[0] EB_ADDR[0] CI_ADDR[12] EB_ADDR[12]
CI_IN_TS_DATA[0]
TPO_DATA[1] CI_ADDR[1] EB_ADDR[1] CI_ADDR[13] EB_ADDR[13]
CI_IN_TS_DATA[1]
TPO_DATA[2] CI_ADDR[2] EB_ADDR[2] CI_ADDR[14] EB_ADDR[14]
CI_IN_TS_DATA[2]
TPO_DATA[3] CI_ADDR[3] EB_ADDR[3] /PCM_REG CAM_REG_N
CI_IN_TS_DATA[3]
TPO_DATA[4]
CI_IN_TS_DATA[4] CI
TPO_DATA[5] CI_IN_TS_DATA[5] AR912
TPO_DATA[6] 33 CI
CI_IN_TS_DATA[6] CI_ADDR[4] EB_ADDR[4] AR914
TPO_DATA[7] 33
CI_IN_TS_DATA[7] CI_ADDR[5] EB_ADDR[5] /PCM_OE EB_OE_N
AR905 CI CI_ADDR[6] EB_ADDR[6] /PCM_WE EB_WE_N
33 EB_BE_N1
CI_ADDR[7] EB_ADDR[7] /PCM_IORD
/PCM_IOWR EB_BE_N0
CI
AR903 CI
33
TPO_CLK CI_IN_TS_CLK AR913
33
TPO_SOP CI_IN_TS_SYNC CI_ADDR[8] EB_ADDR[8]
TPO_VAL CI_IN_TS_VAL CI_ADDR[9] EB_ADDR[9]
TPO_ERR CI_ADDR[10] EB_ADDR[10]
CI_ADDR[11] EB_ADDR[11]
IC903
0.1uF
74LVC16244ADGG
C900
+5V_NORMAL
CI 16V
2OE 1OE
48 1
1A0 1Y0
47 2
R915 CI
R916 CI
/PCM_WAIT CAM_WAIT_N
1A1 1Y1
46 3
/PCM_IRQA CAM_IREQ_N
10K
10K
GND_8 GND_1
45 4
1A2 1Y2
44 5
/CI_CD2 CAM_CD2_N
1A3 1Y3
/CI_CD1 43 6
CAM_CD1_N
VCC_4 VCC_1
CI 42 7 TPI_CLK
CI
C905 C906 2A0 2Y0
0.1uF 41 8
0.1uF CAM_INPACK_N TPI_VAL
16V 16V AR921 CI 2A1 2Y1
PCM_INPACK 40 9
GND_7 GND_2
CI TPI_SOP
CI_TS_CLK 39 10
CI_TS_VAL 2A2 2Y2
100 38 11
CI_TS_SYNC
2A3 2Y3
AR918 75
37 12
3A0
36 CI 13
3Y0
TPI_DATA[7]
AR920 CI 3A1 3Y1
35 14
CI_TS_DATA[7] TPI_DATA[6]
GND_6 GND_3
CI_TS_DATA[6] 34 15
CI_TS_DATA[5] 3A2 3Y2 TPI_DATA[5]
100 33 16
CI_TS_DATA[4]
3A3 3Y4
32 17 TPI_DATA[4]
VCC_3 VCC_2
31 18
4A0
30 19
4Y0 75 CI AR917
TPI_DATA[3]
AR919 CI 4A1 4Y1
29 20
CI_TS_DATA[3]
GND_5 GND_4 TPI_DATA[2]
CI_TS_DATA[2] 28 21
CI_TS_DATA[1] 4A2 4Y2
100 27 22 TPI_DATA[1]
CI_TS_DATA[0]
4A3 4Y3
26 23
TPI_DATA[0]
3OE 4OE
25 24
AR916 75 CI
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.5V_ST +12V
PANEL_POWER Power_DET
MMBT3906(NXP)
PD_+12V PD_+3.5V
R2362 R2366 R2376
PANEL_VCC IC2307
1
VCC 3 2 RESET
P2301 AO3407A
3
D
FW20020-24S C2359 1
R2343
+24V PD_+12V 0.1uF
C2339
GND
R2363
33K
C2332 C2335
OPT 1uF
25V
16V
L2305 10uF 0.1uF 1.2K
PWR ON 1 2 24V G 1% C2365
CIS21J121 16V 50V C2346
24V 3 4 24V OPT 0.1uF
0.1uF
16V
R2344
GND 5 6 GND 50V
5.6K
+3.5V_ST L2303 C2317
GND 7 8 GND 0.1uF +3.3V_NORMAL
BLM18SG121TN1D
3.5V 9 10 3.5V 50V PD_24V
3.5V 3.5V R2330 +24V R2372
C2307 11 12 LPB C 100K
0.1uF GND GND 1K
13 14 R2302 not to RESET at 8kV ESD
+12V 16V 100 PANEL_CTL B Q2304
GND 15 16 GND/V-sync R2312 PD_24V
L/DIM0_VS MMBT3904(NXP)
12V INV ON 100 INV_CTL IC2308
17 18 R2341 PD_24V
CIS21J121 12V A.DIM 10K E R2364 NCP803SN293
19 20 A_DIM
8.2K
12V 21 22 P.DIM1 1%
C2306 L2302 PWM_DIM
0.1uF GND/P.DIM2 Err OUT VCC 3 2 RESET
23 24
50V
1
PD_24V C2360 24V-->3.48V
25 R2365 0.1uF GND
1.5K
12V-->3.58V
SMAW200-H24S2 16V
1% PD_24V
ST_3.5V-->3.5V
P2300
PWM_DIM2
1 +5V_Normal
+12V +5V_NORMAL
MAX 1A
ERROR_OUT L2310 4
BLM18PG121SN1D
+1.0V_VDD
R2304
+12V
0
THERMAL
+3.3V_NORMAL +3.3V_TU_IN
THERMAL
3.3V_EMMC +1.8V_NORMAL R2322
EMMC_VCCQ
15
R1 1% VFB VBST C2345 VIN1 VFB 22K
9
+3.3V_TU 2 7 C2354 13 2
10uF 1%
R2308 0.1uF L2313
16V 16V
L2319 56K VREG5 SW 6.8uH VBST VREG5
L2306 3 6 12 3
BLM18PG121SN1D C2334
BLM18PG121SN1D C2318
L2314
BLM18PG121SN1D
100pF
50V
SS GND
NR8040T4R7N
C2343
SW2
4A SS
1uF
10V
11 4
C2371
0.1uF
C2372
0.1uF R2311
4
3A 5
22uF
10V
C2303
0.1uF
50V
R1 OPT
C2321
16V 16V SW1 GND R2313
10K C2336 C2342 10 5 9.1K 22pF
R2 1uF 2200pF C2319 1% 50V
1% R2309
10V 50V 100K 3300pF
PGND2 PG 50V
9 6
+1.0VDC
Switching freq: 700K Vout=0.765*(1+R1/R2) PGND1 EN
8 7 R2310 10K
C2305
0.1uF POWER_ON/OFF2_3
OPT
L2316
1 3. soft start 2uH
+3.5V_ST IC2300
+2.5V +2.5V_NORMAL
22uF
10V
22uF
10V
1 8
1% R1
THERMAL
PG FB 1/16W
9
C2301 2 7 C2315
C2313 PG FB
9
Vout=0.8*(1+R1/R2) IC2305
Vout=0.8*(1+R1/R2) +12V EAN62348501 [EP]GND Max 5926 mA
R2377
100K RT/CLK PWRGD
1 14
2 4
DDR MAIN 1.5V
THERMAL
1/16W +0.9V_VDD
L2315 5% C2349
15
GND_1 BOOT
2 13
MAX 4.7 A
+3.3V_NORMAL 1074 mA
GND_2 PH_2
0.1uF
16V L2317
R2339
POWER_ON/OFF2_3 +0.9V_VDD
10K
3 12
1uH OPT
C2325
PVIN_1 PH_1 C2350 C2363 C2370
4 11
22uF 22uF 10uF
+3.3V_NORMAL
0.1uF C2347 10V 10V 10V
+3.5V_ST 16V C2327 +1.5V_DDR
10uF PVIN_2 EN
0.1uF 5 10
16V
C2375
R2378
1/16W
EP[GND]
6.8K
16V 180pF
CIS21J121
VIN_3
PWRGD
VIN SS/TR
CIS21J121
1%
50V R1
BOOT
6 9
L2318
L2308
L2307
+12V
OPT
EN
50V
16
15
14
13
C2374
[EP]LX 1 12
BLM18PG121SN1D POWER_ON/OFF2_3
R2379
1/16W
R2307
1.3K
*NOTE 17 THERMAL
VIN_2 PH_2 NR8040T3R6N C2302
22000pF
12K
PGND NC_2 2 11
17 R2
R2319
1 8 C2320
1%
50V
2 7 10V
50V
10V 10V 10V 10V 50V 16V
C2311 OPT TPS54319TRE C2329 10V 10V
C2373
AGND EN GND_2 4 9 SS/TR
3A
C2348
3 6 2200pF
R2382
1/16W
4700pF
R2349
30K
C2338
47pF
FB COMP
5
1/16W
16V 16V 16V 50V
R2381 0
4 5
1%
OPT
6A R1
100pF
50V
AGND
VSENSE
COMP
RT/CLK
5%
R2342
1/16W 330K 5%
D2350
R2320
R2340 C2330
R2318 4700pF
ADUC 20S 02 010L
POWER_ON/OFF2_1 15K
10K
1%
C2310 10K
0.1uF 1/16W 5% 50V
16V
R2 R2
R2350
Vout=0.6*(1+R1/R2) Switching freq: 400 ~ 580 Khz
56K
1/16W
3A $ 0.145 1%
Vout=0.8*(1+R1/R2) Vout=0.827*(1+R1/R2)=1.521V
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Renesas MICOM +3.3V_NORMAL
R3035
4.7K
OPT
HDMI_WAUP:HDMI_INIT
10K
+3.5V_ST
R3000
FLG_POD_DR
8pF
8pF
POD_WAKEUP_N
MICOM_DEBUG
/RST_DIIVA
R3014 1K
R3011 10K
LOGO_LIGHT
C3002
C3003
MICOM_DEBUG
MICOM_DEBUG
/RST_DIIVA
LOGO_LIGHT
MICOM_RESET
P3000
12507WS-12L POD_WAKEUP_N
FLG_POD_DR X3000
22
1
MICOM_DIIVA
32.768KHz
22
2
MICOM_DIIVA
for DiiVA R3023 +3.5V_ST
R3002
3
4.7M
R3001
4 OPT
5
MICOM_DEBUG
10K
22
MICOM_DIIVA
6
R3025
R3026
8
MICOM_RESET_SW
GND SW3000
+3.5V_ST
9
MICOM_RESET JTP-1127WEM
2 1
22
10
R3027
270K
EXT_AMP_MUTE
OPT
C3004
P124/XT2/EXCLKS
0.47uF
11
0.1uF
4 3
16V
R3024
12
EXT_AMP_RESET
P122/X2/EXCLK
P41/TI07/TO07
13 C3000
0.1uF COMMERCIAL_12V_CTL
C3001
12V_EXT_PWR_DET
P137/INTP0
P120/ANI19
P40/TOOL0
P123/XT1
P121/X1
+3.3V_NORMAL
SCART_MUTE
RESET
REGC
VDD
VSS
R3032 R3033
10K 10K POWER_ON/OFF2_4
AMP_RESET_BY_MICOM
GP4 High/MID Power SEQUENCE
48
47
46
45
44
43
42
41
40
39
38
37
P60/SCLA0 1 36 P140/PCLBUZ0/INTP6 RL_ON
+3.3V_NORMAL
I2C_SCL3
POWER_ON/OFF! P61/SDAA0 P00/TI00/TXD1
I2C_SDA3
2 35 SCART_MUTE R3037
P62 P01/TO00/RXD1 For Japan:LNB_INIT 10K
AMP_RESET_N
R3003 22
3 34 POWER_ON/OFF2_4 OPT
POWER_ON/OFF2_1
AMP_RESET_BY_MICOM P63 4 33 P130
PANEL_CTL
P31/TI03/TO03/INTP4 IC3000 P20/ANI0/AVREFP
POWER_ON/OFF2_1
MODEL1_OPT_5
5 32 KEY2
IR
P75/KR5/INTP9/SCK01/SCL01 6 R5F100GEAFB 31 P21/ANI1/AVREFM
POWER_ON/OFF2_2 KEY1
P74/KR4/INTP8/SI01/SDA01 7 30 P22/ANI2 +3.3V_NORMAL
HDMI_CEC MODEL1_OPT_2
P73/KR3/SO01 MICOM P23/ANI3
POWER_ON/OFF2_3 POWER_ON/OFF2_2 8 29 MODEL1_OPT_1
R3036
POWER_ON/OFF2_3 POWER_ON/OFF2_3
P72/KR2/SO21 9 28 P24/ANI4 10K
MODEL1_OPT_0
OPT
P71/KR1/SI21/SDA21 10 27 P25/ANI5
POWER_ON/OFF2_4 EEPROM_SDA SIDE_HP_MUTE
EEPROM_SCL
P70/KR0/SCK21/SCL21 11 26 P26/ANI6
MODEL1_OPT_4
P30/INTP3/RTC1HZ/SCK11/SCL11 12 25 P27/ANI7
MODEL1_OPT_6 MODEL1_OPT_3
SOC_RESET
13
14
15
16
17
18
19
20
21
22
23
24
R3018 R3019
3.3K 3.3K
P50/INTP1/SI11/SDA11
P51/INTP2/SO11
P17/TI02/TO02
P16/TI01/TO01/INTP5
P15/PCLBUZ1/SCK20/SCL20
P14/RXD2/SI20/SDA20
P13/TXD2/SO20
P12/SO00/TXD0/TOOLTXD
P11/SI00/RXD0/TOOLRXD/SDA00
P10/SCK00/SCL00
P146
P147/ANI18
+3.5V_ST
10K
10K
10K
10K
MICOM_JAPAN
MICOM_DIIVA
10K
10K
10K
MICOM_PDP
MICOM_GED
MICOM_MHL
TACT_KEY TOUCH_KEY
MODEL_OPT_2
R3005
R3007
R3009
R3012
R3016
R3020
R3030
MODEL1_OPT_0
10K
IR Wafer IR Wafer
MODEL1_OPT_1
MODEL_OPT_4
MODEL1_OPT_2 12/15Pin 10Pin For Sample Set
MODEL1_OPT_3 (GP3_Soft touch) (GP4_TOOL)
R3022
MODEL1_OPT_4
SOC_RX
SOC_RESET
INV_CTL
COMMERCIAL_12V_CTL
EXT_AMP_RESET
AMP_MUTE
LED_B/GP4_LED_R
SOC_TX
EXT_AMP_MUTE
+3.3V_NORMAL
For CEC
MICOM_GP3_12/15PIN
MICOM_NON_JAPAN
MICOM_NON_DIIVA
MICOM_LCD/OLED
MICOM_TACT_KEY
MICOM_NON_GED
MICOM_NON_MHL
10K
10K
10K
10K
10K
10K
10K
R3034
4.7K
R3006
R3008
R3010
R3013
R3017
R3021
R3031
OPT
EDID_WP
C +3.5V_ST
MODEL_OPT_4 B Q3000
0 1 MMBT3904(NXP)
EDID_WP
MODEL_OPT_2 E
R3028 R3029
N/A MC8101_ABOV
0 27K 120K
G
(TACT_KEY)
D3000
BAT54_SUZHO
CM3231_CAPELLA CEC_REMOTE HDMI_CEC
1 CM3231_CAPELLA
S
(GP3 Soft touch) (GP4 Soft touch) Q3001
RUE003N02
G
HDMI_CEC_FET_ROHM
Q3001-*1
SI1012CR-T1-GE3
S
HDMI_CEC_FET_VISHAY
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
AVDD12_3
[EP]GND
VDD33_2
TPVDD12
TCVDD12
VDD12_3
R0X2P
R0X2N
R0X1P
R0X1N
R0X0P
R0X0N
R0XCP
R0XCN
TXCN
TXCP
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
ARC
BODY_SHIELD
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
UD
R1XCN 1 66 RSVDL
R1XCP 2 65 SPDIF_IN
THERMAL
R1X0N 3 64 INT
89
5V_HDMI_1 5V_HDMI_4 R1X0P CSCL
BODY_SHIELD GND R1X1N
4 63
CSDA
5 62
IC3202 R1X1P 6 61 RESET_N
[EP] TPS2554 R1X2N 7 60 TPWR
THERMAL
18 18 D3206 R3X1N 15 52 WKUP
GND R3X1P LPSBV
GND MBR230LSFT1G 16 51
11
R3222 OUT_2 IN_1 R3X2N 17 50 PWRMUX_OUT
17 17 9 2 R3X2P 18 49 SBVCC5
DDC_DATA R3207 0 DDC_DATA 0 AVDD12_2 19 48 R5PWR5V[VGA]
DDC_SCL_4 8 3
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
15 DDC_SCL_1 15
NC
R4X0N
R4X0P
R4X1N
R4X1P
R4X2N
R4X2P
VDD12_2
DSDA0
DSCL0
CBUS_HPD0
R0PWR5V
DSDA1
DSCL1
CBUS_HPD1
R1PWR5V
DSDA3
DSCL3
CBUS_HPD3
R3PWR5V
DSDA4
DSCL4
CBUS_HPD4
ARC
D3204
14 14 ILIM0 ILIM_SEL
CE_REMOTE CE_REMOTE 7 4
CEC_REMOTE CEC_REMOTE
13 13
CK- ARC CK- 5%
Limit 0.8A
Limit 0.8A
R3248
CK_GND
1K
C
EAG62611201
10K MHL_DET
EAG62611201
11
1/10W
R3201
1/10W
R3200
11 CK+ R3245
5%
1/16W
220K
R3206
CK+ C3202 A2
10
62K
62K
10 CK+_HDMI1 1uF SPDIF_OUT_ARC CK+_HDMI4
D0-
OPT
D0- 9
9 10V OPT D0-_HDMI4
D0-_HDMI1
R3249
C3226 D0_GND
3.9K
D0_GND 8
OPT
8 0.1uF
D0+ 16V D0+
7 7 D0+_HDMI4
D0+_HDMI1
D1- D1- +3.5V_ST
6 6 D1-_HDMI4
D1-_HDMI1
D1_GND D1_GND
5 5
R3246
D1+ D1+
SPDIF_OUT_ARC
10K
4 4 D1+_HDMI4
D1+_HDMI1
D2- D2-
3 3 D2-_HDMI4 R3247 E MMBT3906(NXP)
D2-_HDMI1 R3243 10K Q3201 HDMI1
D2_GND 2
D2_GND
1K HDMI S/W OUTPUT
2
D2-_HDMI1
D1+_HDMI1
D1-_HDMI1
D0+_HDMI1
D0-_HDMI1
CK+_HDMI1
CK-_HDMI1
B
D2+_HDMI1
HDMI_RX1-
HDMI_CLK-
HDMI_RX0-
HDMI_RX0+
HDMI_RX1+
HDMI_RX2-
HDMI_RX2+
HDMI_CLK+
D2+ D2+ 1/16W
1 1 D2+_HDMI4 C
D2+_HDMI1 5% C3223 C
D3207
0.047uF
5.6V
B
25V MHL_DET
Q3200
HDMI4 With MHL
R3221
JK3202 RSD-105156-100 MMBT3904(NXP) E
JK3203
10
RSD-105156-100
HDMI1 With ARC
OPT
+5V_NORMAL
5V_HDMI_1 +5V_NORMAL
5V_HDMI_2
L3202
L3203
A1
A2
BODY_SHIELD 5V_HDMI_2
A1
A2
D3200
20
D3202
C
HP_DET 16V
HDMI_HPD_2
AVDD12_3
C
19 0.1uF
C3224
[EP]GND
VDD33_2
TPVDD12
TCVDD12
VDD12_3
5V C3225
R3219 0.1uF
18 R3217
R0X2P
R0X2N
R0X1P
R0X1N
R0X0P
R0X0N
R0XCP
R0XCN
GND 16V
47K 47K R3228
TXCN
TXCP
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
R3225
R3209
ARC
17 47K
DDC_DATA 0 DDC_SDA_1 47K
DDC_SDA_2
16 R3210 DDC_SDA_2 +3.3V_NORMAL
DDC_CLK 0 DDC_SCL_1
15 DDC_SCL_2 DDC_SCL_2
10K
R3202
NC
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
14
CE_REMOTE +5V_NORMAL HDMI2 R1XCN 1 66 RSVDL OPT
CEC_REMOTE 5V_HDMI_3 +5V_NORMAL CK-_HDMI2
13 +3.5V_ST
CK- 5V_HDMI_4 R1XCP 2 65 SPDIF_IN R3224 33
SPDIF_OUT
12
CK-_HDMI2 CK+_HDMI2 THERMAL
R1X0N INT R3211 33
A1
A2
CK_GND
3 89 64 HDMI_INT
EAG62611201
D0-_HDMI2
A1
A2
A1
A2
11
CK+ D3201 R1X0P 4 63 CSCL R3236 33
10 CK+_HDMI2 I2C_SCL5
D3203 D3205 D0+_HDMI2
C
D1-_HDMI2
D0_GND R1X1P 6 61 RESET_N R3214 33
8 HDMI_S/W_RESET
D1+_HDMI2
D0+ R3218 R3220 R1X2N TPWR
7 D0+_HDMI2 47K 47K R3226 R3229 7 60
D2-_HDMI2
D1- 47K 47K R1X2P 8 59 GPIO1
6 D1-_HDMI2
DDC_SDA_3 DDC_SDA_4
D2+_HDMI2 IC3201
D1_GND AVDD12_1 9 58 GPIO0
5
D1+ DDC_SCL_3
DDC_SCL_4
VDD12_1 SII9587CNUC CD-SENSE4
4 D1+_HDMI2 10 57 MHL_DET
D2- HDMI3 R3XCN 11 56 CD_SENSE3
3
2
D2_GND
D2-_HDMI2 CK-_HDMI3
CK+_HDMI3
R3XCP 12 FHD 55 GPIO2 +3.5V_ST
+5V_NORMAL +3.3V_NORMAL
D2+ R3X0N 13 54 CD_SENSE1
1 D2+_HDMI2 D0-_HDMI3 1/16W
10K
R3203
10K
R3244
R3X0P 14 53 CD_SENSE0 R3213
D0+_HDMI3 5.1K
D1-_HDMI3
R3X1N 15 Device Address : 0XB0 52 WKUP 5% HDMI_WKUP
JK3200 R3X1P LPSBV
D1+_HDMI3
16 51
RSD-105156-100
HDMI2 +3.3V_NORMAL R3X2N 17 50 PWRMUX_OUT
D2-_HDMI3 R3216
R3X2P 18 49 SBVCC5 10 RGB_5V
L3200 D2+_HDMI3 R3242
BLM18PG121SN1D
AVDD12_2 19 48 R5PWR5V[VGA] 10
VDD33_1 20 47 DSCL5[VGA]
R4XCN DSDA5[VGA] RGB_DDC_SCL
21 46
C3205 C3211
10uF C3210 0.1uF
R4XCP 22 45 R4PWR5V RGB_DDC_SDA
10V 0.1uF 16V C3221
C3209 C3215
16V C3222
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
0.1uF 0.1uF
5V_HDMI_3 16V 16V 1uF 10uF
BODY_SHIELD 10V 10V
C3212
C3218
R4X0N
R4X0P
R4X1N
R4X1P
R4X2N
R4X2P
VDD12_2
DSDA0
DSCL0
CBUS_HPD0
R0PWR5V
DSDA1
DSCL1
CBUS_HPD1
R1PWR5V
DSDA3
DSCL3
CBUS_HPD3
R3PWR5V
DSDA4
DSCL4
CBUS_HPD4
20
BLM18PG121SN1D
1uF 10uF
HP_DET IC3200 10V 10V
HDMI_HPD_3
19
5V
AZ1117BH-1.2TRE1
18
GND
L3201
17 R3204
DDC_DATA 0
DDC_SDA_3 IN OUT
16 R3205 3 2
DDC_CLK 0
DDC_SCL_3 1
15 OPT
NC GND/ADJ C3203 C3201 C3206 C3216
14 10uF 10uF 0.1uF 10uF R3215 33
CE_REMOTE C3200 10V 10V 16V 10V HDMI_WKUP 12V_EXT_PWR_DET
CEC_REMOTE 10uF
13 10V
CK-
CK-_HDMI3
12 R3212 33
CK_GND
MHL_DET
EAG62611201
11
CK+
10 CK+_HDMI3
C3204 C3207
D0- C3217
9 0.1uF 0.1uF
D0-_HDMI3 0.1uF
16V 16V
D0_GND 16V
8
D0+
7
DDC_SDA_1
DDC_SCL_1
DDC_SCL_2
DDC_SDA_2
D0+_HDMI3
D0-_HDMI4
D0+_HDMI4
D1-_HDMI4
D1+_HDMI4
D2-_HDMI4
D2+_HDMI4
CK-_HDMI4
CK+_HDMI4
DDC_SDA_3
DDC_SCL_3
DDC_SDA_4
DDC_SCL_4
HDMI_HPD_1
HDMI_HPD_2
HDMI_HPD_3
HDMI_HPD_4
D1-
6 D1-_HDMI3
D1_GND
5
4
D1+
D1+_HDMI3
Vout=0.8*(1+R1/R2)
D2- HDMI4
3 D2-_HDMI3
D2_GND
2
D2+
1 D2+_HDMI3 5V_HDMI_1 5V_HDMI_2 5V_HDMI_3 5V_HDMI_4
R3240 R3238
R3231 R3232 10 10
10 10
JK3201
1/16W 1/16W
RSD-105156-100 1/16W 1/16W C3220 R3241 C3219 R3239
C3213 R3233 C3214 R3234
HDMI3 1uF 5.1K 1uF 5.1K
1uF 5.1K
5%
1uF
5.1K
5%
5% 5%
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
RGB/ PC AUDIO/ SPDIF
R3641
RGB_EDID
R3642 R3645
IC3600
M24C02-RMN6T 2.7K 2.7K 10K
E0 VCC
1 8
RGB_EDID JK3602
+3.3V_NORMAL
E1
2 7
WC 2F11TC1-EM52-4F
EDID_WP
E2 SCL R3643 22 VIN
3 6
RGB_DDC_SCL
SPDIF OUT A
Fiber Optic
VSS SDA R3644 22
4 5
RGB_DDC_SDA
VCC B
R3620
C3633 C3634 2.7K
18pF 18pF R3615 OPT
50V 50V 33 GND C
SPDIF_OUT
D3613 C3615 4
5.5V 0.1uF
16V
SHIELD
D3613-*1 ADUC 5S 02 0R5L
DSUB_VSYNC 5.5V OPT
D3621 ADUC 5S 02 0R5L
D3615
ADUC 5S 02 0R5L ESD_MTK
30V 5.5V
OPT OPT
DSUB_HSYNC D3622
ADUC 5S 02 0R5L
D3616 5.5V
30V OPT
OPT
RGB_DEBUG
R3602
100
DSUB_B+ SOC_RX
RGB_DEBUG
R3647 PC AUDIO
100
SOC_TX
R3600 D3600 JK3601
0 20V D3601 KJA-PH-0-0177
R3601
NON_RGB_DEBUG OPT 0 20V
OPT 5 GND
NON_RGB_DEBUG
4 L
PC_L_IN
+3.3V_NORMAL
DSUB_G+
3 DETECT D3611
5.6V D3611-*1
R3646 ESD_MTK
10K 1 R OPT
5.6V
DSUB_DET
D3623 PC_R_IN
5.6V
DSUB_R+ OPT
D3612
D3612-*1
5.6V
ESD_MTK
OPT
5.6V
11
12
13
14
10
15
6
1
7
2
8
3
9
Closed to JACK
11
12
13
14
15
16
16
10
6
9
1
JK3603
SLIM-15F-D-2
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
HP_LOUT JK3700
+3.3V_NORMAL KJA-PH-0-0177
GND 5
R3700
10K L 4
HP_OUT
DETECT 3
HP_DET
R 1
HP_ROUT EAG61030001
HP_OUT
VA3700
5.6V
OPT
VA3700-*1
VA3700-*2
5.6V
5.6V
ESD_MTK_HP_OUT
ESD_LG1152_HP_OUT
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
12V_COMMERCIAL_OUT
12V_COMMERCIAL_OUT
RS232C 10
CVBS 1 PHONE JACK
5 +3.3V_NORMAL
9
IR_OUT 4
R3810
10K
IC3800 +3.5V_ST RS232 8
MAX3232CDR 100 R3820
3 AV1_CVBS_DET
7
RS232 D3800
0.1uF C3800 C1+ VCC 100
1 16 R3821 5.6V
2 AV_JACK_BLACK OPT
RS232 +3.5V_ST
OPT_RS232 6 JK3800
C3801 V+ GND D3804 D3805
0.1uF 2 15 R3834 KJA-PH-1-0177
20V 20V
1 5 M5_GND
RS232 OPT OPT 10K
C1- DOUT1 RS232
3 14 FOR COMMERCIAL
4 M4
SPG09-DB-009 AV1_CVBS_IN
0.1uF C3802 C2+ RIN1
4 13 JK3803 3 M3_DETECT
RS232 RS232
C2- ROUT1 1 M1
5 12
6 M6
0.1uF C3803 V- DIN1
6 11
RS232
DOUT2 DIN2
7 10 AV_JACK_YELLOW AV1_L_IN
JK3800-*1
RIN2 ROUT2 KJA-PH-1-0177-1 D3801
8 9 SOC_RX
5.6V
5 M5_GND
OPT
EAN41348201
SOC_TX
4 M4
UART_4PIN_STRAIGHT UART_4PIN_ANGLE
+3.5V_ST 3 M3_DETECT
+3.5V_ST P3800 P3801
12507WS-04L 12507WR-04L
1 M1
R3811 R3814 AV1_R_IN
4.7K 4.7K 6 M6
OPT OPT 1 1 D3802
5.6V
OPT
2 2
3 3
4 4
5 5
D3800-*1 D3800-*2
R3806 5.6V 5.6V
10K ESD_MTK ESD_LG1152
COMP1_DET
3 M3_DETECT
1 M1
6 M6
COMP_JACK_GREEN COMP1_Pb
JK3801-*1
KJA-PH-1-0177-2
5 M5_GND
4 M4
3 M3_DETECT
1 M1 COMP1_Pr
6 M6
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.5V_ST
R4100
0
9
IR_BYPASS
C4107 D4104 OPT
100pF 5.6V
+3.5V_ST 50V AMOTECH CO., LTD. 10
COMMERCIAL
COMMERCIAL_IR_EU 11
+3.5V_ST
R4109
1K
R4105 COMMERCIAL_IR
22
IR_OUT R4115
COMMERCIAL_IR COMMERCIAL_IR_EU3.3K
R4111
Q4102 C 10K
MMBT3904(NXP) B
COMMERCIAL_IR_EU E R4119
C 47K
B
Q4104
MMBT3904(NXP)
E COMMERCIAL_IR
Soft Touch Micom D/L
COMMERCIAL_IR
R4108
0
Zener Diode is
COMMERCIAL_IR_US
close to wafer
D4105-*1
ADUC 20S 02 010L
20V 10pF
ESD_MTK
D4106-*1
ADUC 20S 02 010L
20V 10pF
ESD_MTK
D4100-*2
ESD_MTK
D4101-*2
5.6V 200pF
D4101-*1
ADMC 5M 02 200L
5.6V200pF
ESD_LG1152
ADMC 5M 02 200L
ESD_MTK
D4104-*2
5.6V 200pF
D4104-*1
ADMC 5M 02 200L
5.6V 200pF ESD_LG1152
ADMC 5M 02 200L
ESD_MTK
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
USB_DM1
USB_DP1
C4209
25V
1uF
USB_HUB_IC_IN_DP
USB_HUB_IC_IN_DM
0.1uF
C4208
C4205
C4207
15pF
15pF
SUSP_IND/LOCAL_PWR/NON_REM[0]
R4205
1% 1M
1/16W 1%
R4204
R4206
100K
X4200 USB_DM2
12K
24MHz
XTALIN/CLKIN
USB_DP2
+3.3V_NORMAL
VDDA33_3
USBDM_UP
USBDP_UP
XTALOUT
PLLFILT
VDD33_3
[EP]VSS
RBIAS
C4203
28
29
30
31
32
33
34
35
36
R4200 0.1uF
100K VBUS_DET 27 1 USBDM_DN[1]
THERMAL
RESET_N 26 37 2 USBDP_DN[1] +3.3V_NORMAL
/RST_HUB
C4200
HS_IND/CFG_SEL[1] 25 3 USBDM_DN[2]
0.1uF
OPT SCL/SMBCLK/CFG_SEL[0] USBDP_DN[2]
24 4
IC4200
VDD33_2 23 USB2512B-AEZG 5 VDDA33_1
SDA/SMBDATA/NON_REM[1]
NC_8
22
USB HUB 6 NC_1
NC_2
C4210
0.1uF
C4211
0.1uF
C4212
0.1uF
C4213
0.1uF
C4214
1uF
25V
21 7
OPT OPT OPT
NC_7 20 8 NC_3
NC_6 19 9 NC_4
18
17
16
15
14
13
12
11
10
R4203
R4202
R4201
100K
100K
100K
NC_5
OCS_N[2]
PRTPWR[2]/BC_EN[2]
VDD33_1
CRFILT
OCS_N[1]
PRTPWR[1]/BC_EN[1]
TEST
VDDA33_2
+3.3V_NORMAL
C4204
0.1uF
C4201 C4202
4.7uF
0.1uF
C4206
R4209
25V
1uF
22
22
100K
OPT
OPT
OPT
R4207
R4208
R4210
100K
OPT
/USB_OCD2
USB_CTL2
/USB_OCD1
USB_CTL1
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V_NORMAL
D4304-*1
C4327
0.1uF GND FAULT
SX34
1 10
40V
16V
16V
THERMAL
L4308
+24V 0.1uF C4329 IC4305 6.8uH
11
IN_1 OUT_2
TPS54331D
USB1
R4330
2 9
0
L4305
D4304
SMAB34
820
R4343
35V 3 6
50V
1%
3AU04S-305-ZC-(LG)
R4300
1/10W
R4341
1/10W
C4332 C4334 JK4303
27K
SS/TR VSENSE
27K
OPT
4 5 47pF 4700pF
330K
50V 50V
OPT
R4329
R1
1
R4338
10K
0.01uF 20K C4338
1000pF USB_DM1
2
50V
50V
RCLAMP0502BA
3
USB_DP1
R4339
Vout=0.8*(1+R1/R2)
D4303
4
R2
1%
2K
OPT
5
R4332
IC4306 POWER_ON/OFF2_4
10K
[EP]GND SN1104041, DC-DC+2CH USB SW C4300
0.1uF
16V
+12V +3.3V_NORMAL
V7V EN
24 1
USB_DCDC_SN1104041
THERMAL
C4341 R4342
25
R4304 10K
10K
10K
VIN_2 SS C4340 C4340-*1
USB2
OPT
OPT
22 3 C4342 4700pF 0.01uF
100pF
R4301
50V 50V
R4302
R4303
50V USB_DCDC_BD86180
C4325
10uF
VIN_1
21 4
ROSC
USB_DCDC_SN1104041
MAX 1.5A
16V +5V_USB_2
PGND_2 EN_SW2
20 5 3AU04S-305-ZC-(LG)
USB_CTL2
JK4302
PGND_1 EN_SW1
19 6
1
/USB_OCD2
2
USB_DM2
C4331
L4307
0.1uF
RCLAMP0502BA
3.6uH LX_2 NFAULT1
16V
17 8
3
USB_DP2
DEV_USB_DCDC_BD86180
IC4306-*1
BD86180MUV [EP]GND
C4337 C4301 +5V_USB_3
LX_1 SW_OUT2 C4322
D4302
22uF 22uF 16 9
4
EN VREG
1 24
10uF
THERMAL
OPT
10V 10V
25
COMP GND_3
2 23
10V
5
SS VIN_2
3 22
RT VIN_1
SW_IN_3 AGND_1
4 21
15 10
CTL2 PGND_2
5 20
CTL1 PGND_1
6 19
FLG2
7 18
BST
SW_IN_2 AGND_2 +5V_USB_2
FLG1
8 17
SW_2
14 11
USB_OUT2 SW_1
9 16
GND_1 USB_IN_3
10 15
SW_IN_1 SW_OUT1
GND_2
11 14
USB_IN_2
13 12
USB_OUT1 USB_IN_1
12 13
USB3
MAX 1.5A
+5V_USB_3
3AU04S-305-ZC-(LG)
JK4300
1
USB DOWN STREAM
ESD for MTK
2
ESD for LG1152
RCLAMP0502BA
3
D4300
C4310
4
OPT
10uF
5
10V
RCLAMP0502BA
D4300-*2
ESD_LG1152
USB_WIFI
RCLAMP0502BA
+5V_USB
D4302-*1
ESD_LG1152
12507WR-04L
ESD_LG1152
USB_DM3
WIFI
VDD
USB_DP3 1
DM
WIFI_DM 2
USB_CTL3
/USB_OCD3 DP
WIFI_DP 3
GND
4
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V_NORMAL
+12V
EU
R4601
Full Scart(18 Pin Gender) 10K CLOSE TO JUNCTION
SC_DET
EU EU
E EU EU
D4611 D4611-*2 D4611-*1 C4604 MMBT3906(NXP) C4606
R4605
5.6V 5.6V 5.6V 0.1uF Q4600 470 0.1uF
200pF 200pF 50V
OPT B
C EU EU
ESD_LG1152_SCART ESD_MTK_SCART Q4601 R4606
EU
MMBT3904(NXP)
C 47K
R4602
SC_CVBS_IN 390 B EU
C4607
47uF
D4609 D4609-*1 D4609-*2 E 25V
5.5V 5.5V 5.5V EU
SHIELD 15pF 15pF R4603
OPT 390
ESD_MTK_SCART ESD_LG1152_SCART DTV/MNT_V_OUT
19 Gain=1+Rf/Rg EU
Rf EU R4607
AV_DET Rg
75 R4600 R4604 15K
180
18
COM_GND EU
D4610 EU
5.5V D4610-*1 C4605
17
SYNC_IN OPT 5.5V 100uF
15pF 16V R4608
16 0
SYNC_OUT ESD_MTK_SCART
15 OPT
SYNC_GND
14
RGB_IO
13 SC_FB
R_OUT D4601
12 5.6V D4601-*1
R_GND OPT D4601-*2
5.6V 5.6V
11 200pF 200pF
G_OUT
ESD_MTK_SCART ESD_LG1152_SCART
10
G_GND
9 SC_R
ID
8 D4602
B_OUT D4602-*1
5.5V 5.5V
7
AUDIO_L_IN OPT 15pF
6 ESD_MTK_SCART
B_GND
5 SC_G
AUDIO_GND
4 D4603
AUDIO_L_OUT D4603-*1
5.5V 5.5V
3 15pF
AUDIO_R_IN OPT
ESD_MTK_SCART
2
AUDIO_R_OUT
1
SC_B
D4604 D4604-*1
5.5V 5.5V
DA1R018H91E 15pF
OPT
JK4600 ESD_MTK_SCART
EU
SC_ID
SC_L_IN
BLM18PG121SN1D
L4600
DTV/MNT_L_OUT
D4607 EU EU EU
5.6V C4600 C4602
OPT 1000pF 4700pF
50V
BLM18PG121SN1D
L4601
DTV/MNT_R_OUT
EU
D4608 EU EU C4603
5.6V C4601 4700pF
OPT 1000pF
50V
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
ZigBee_Radio Pulse M_REMOTE OPTION
+3.3V_NORMAL
P4800
12507WR-08L
L4800
M_REMOTE 120-ohm
1
3.3V M_REMOTE AR4800
C4800 100
2
GND 0.1uF
1/16W
RX
3 M_REMOTE_RX
TX
4 M_REMOTE_TX
RESET
5 M_RFModule_RESET
DC
6 M_RFModule_ISP
DD
7 3D_SYNC_RF
8
GND M_REMOTE
9
3D_SYNC_RF
Only For PDP
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Ethernet Block
LAN_JACK_POWER
P1[CT]
1
P2[TD+]
2
EPHY_TDP
P3[TD-]
3
EPHY_TDN
P4[RD+]
4
EPHY_RDP
P5[RD-]
5
EPHY_RDN
P8
8
P9
9
P10[GND]
10
P11
11
YL_C
D1
YL_A
D2
GN_C
D3
GN_A
D4
ESD for MTK ESD for LG1152
12
SHIELD ESD_LG1152
D5000-*1
ESD_MTK
D5000-*2
ADUC 5S 02 0R5L
5.5V
ADUC 5S 02 0R5L
ESD_LG1152
D5001-*1
ESD_MTK
ADUC 5S 02 0R5L D5001-*2
5.5V
ADUC 5S 02 0R5L
ESD_LG1152
D5002-*1
ESD_MTK
ADUC 5S 02 0R5L D5002-*2
5.5V
ADUC 5S 02 0R5L
ESD_LG1152
D5003-*1
ESD_MTK
D5003-*2
ADUC 5S 02 0R5L
5.5V
ADUC 5S 02 0R5L
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Ethernet Block
+3.3V_NORMAL
+3.3V_NORMAL
+3.3V_NORMAL
4.7K
4.7uF
4.7K
10V 16V 16V
R5216
Place 0.1uF close to each power pins
R5215
LAN_JACK_POWER
EPHY_LINK
EPHY_ACTIVITY
ET_RXER
R5217 4.7K
ET_COL/SNI
C5208 C5210
0.1uF 10uF
16V 10V
OPT
EPHY_ACTIVITY
EPHY_CRS_DV
ET_COL/SNI
ET_RXER
C5206
15pF
50V
+3.3V_NORMAL
X5200
25MHZ
R5210
25MHz, CL 18pF, ESR , max 30 Ohm, +/-30ppm
22
R5205
LED1/PHYAD[1]
Place this cap. near IC C5207 0
CRS/CRS_DV
DVDD10OUT
RXER/FXEN
15pF
AVDD33_2
+3.3V_NORMAL
CKXTAL2
CKXTAL1
50V
C5204
[EP]
C5205
COL
10uF Place this Res. near IC
10V 0.1uF
OPT 16V
R5212
1/16W
1.5K
32
31
30
29
28
27
26
25
R5204
2.49K 1%
5%
RSET 1 24 LED0/PHYAD[0]/PMEB
EPHY_LINK
THERMAL
AVDD10OUT 2 33 23 MDIO EPHY_MDIO
Route Single 50 Ohm, Differential 100 Ohm
MDI+[0] 3 22 MDC EPHY_MDC
EPHY_TDP
MDI-[0] IC5200 PHYRSTB
4 21 /RST_PHY
EPHY_TDN RTL8201F-VB-CG
MDI+[1] 5 20 TXEN
EPHY_RDP EPHY_EN C5212
+3.3V_NORMAL 0.1uF
MDI-[1] 6 19 TXD[3]
EPHY_RDN OPT
AVDD33_1 7 18 TXD[2]
R5203 RXDV TXD[1]
8 17 EPHY_TXD1
4.7K
10
11
12
13
14
15
16
9
RXD[0]
RXD[1]
22 RXD[2]/INTB
RXD[3]/CLK_CTL
RXC
DVDD33
TXC
TXD[0]
+3.3V_NORMAL
22
22
C5211
R5207
R5206
0.1uF
C5209
R5201
16V
L5211
100NH
56pF
C5202
4.7K
EPHY_RXD0
EPHY_RXD1
EPHY_TXD0
EPHY_INT
56pF
Place near IC
R5208
EPHY_REFCLK
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
DUAL COMPONENT +3.3V_NORMAL AMP_RESET_N
C5415
1000pF
Q1801 1ST : 0TRIY80001A 2ND : 0TR387500AA 50V
50V
L5401
+24V_AMP
22000pF
BLM18PG121SN1D
C5416
OPT
AUD_MASTER_CLK R5406
3.3
+24V_AMP OPT
+24V
C5424
OUT1A_2
OUT1A_1
PVDD1_3
PVDD1_2
PVDD1_1
C5418 C5420 C5422
0.1uF 0.1uF 10uF 0.01uF
VDD_IO
GND_IO
/RESET
PGND1A
C5413 C5414 50V
50V 50V 35V
CLK_I
BST1A
10uF
L5400 0.1uF
10V
[EP]
AD
1N4148W R5407 R5414
12 12 L5404
100V 10.0uH C5436 R5415
OPT OPT 0.1uF
OPT C5409 C5411 5.1K
C5400 C5401 C5405 C5407 10uF 0.1uF C5429 50V
0.1uF 0.1uF 390pF NRS6045T100MMGK
50V 50V 10uF 4.7uF 10V 16V 50V C5434
10V 10V L5405 0.47uF
48
47
46
45
44
43
42
41
40
39
38
37
C5403
1000pF
50V
10.0uH 50V
SPEAKER_L
C5402 C5430 C5437
100pF R5404 AGND_PLL 1 36 OUT1B_2 D5401
390pF
50V
NRS6045T100MMGK 0.1uF
50V
R5416
50V 3.3K 1N4148W R5408 R5412 5.1K
AVDD_PLL 2 35 OUT1B_1 100V
OPT
12 12
THERMAL SPK_L-
DVDD_PLL 3 49 34 PGND1B C5425
22000pF
LF 4 33 BST1B 50V
WAFER-ANGLE
R5403 100
I2C_SCL1
C5406 C5408
+3.3V_NORMAL
33pF 33pF
50V 50V SPK_R+
SCL
/FAULT
MONITOR0
MONITOR1
MONITOR2
BST2B
PGND2B
OUT2B_1
OUT2B_2
PVDD2_1
PVDD2_2
PVDD2_3
WOOFER_MUTE TP5403
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+24V +24V_AMP_WOOFER
L5501
CIS21J121
C5529
0.1uF
50V
50V
BLM18PG121SN1D R5505
SPK_WOOFER_L- 1
+24V_AMP_WOOFER
22000pF
C5514
10K OPT
AUD_MASTER_CLK R5506
3.3 SPK_WOOFER_L+ 2
OPT
WOOFER WOOFER WOOFER C5522
OUT1A_2
OUT1A_1
PVDD1_3
PVDD1_2
PVDD1_1
WOOFER C5516 C5518 C5520
WOOFER 0.1uF 0.1uF 10uF 0.01uF
VDD_IO
GND_IO
/RESET
C5511 C5512
PGND1A 50V 50V 35V 50V
CLK_I
BST1A
0.1uF 10uF
[EP]
10V SPK_WOOFER_L+
16V
D5500 WOOFER WOOFER L5503 WOOFER
AD
4.7K
R5517
12 12 10.0uH WOOFER_STEREO
C5503 C5505 100V C5537 R5513
WOOFER
WOOFER
0.47uF
+24V_AMP_WOOFER WOOFER_STEREO L5505 50V
C5533 10.0uH WOOFER_STEREO
WOOFER_STEREO
390pF C5538
D5503 50V 0.1uF R5519
NRS6045T100MMGK 50V
1N4148W R5509 R5510 5.1K
100V 12 12
OPT
WOOFER WOOFER WOOFER SPK_WOOFER_R-
C5517 C5519 C5521 WOOFER_STEREO WOOFER_STEREO
0.1uF 0.1uF 10uF
WOOFER WOOFER 50V 50V
R5504 35V
C5515
WOOFER_MUTE
100 WOOFER
C5510
22000pF
1000pF 50V
50V
WOOFER_MONO
5%
1/16W
4.7K
R5518
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+12V
EU
AUD_OUT >> EU/CHINA_HOTEL_OPT
IC6000 L6000
AZ4580MTR-E1
EU
EU
2.2K R6000 OUT1 8 VCC C6004
DTV/MNT_L_OUT 1
EU
C6000 OPT
0.1uF
50V R6011
EU
C6008
[SCART AUDIO MUTE]
OPT R6002 EU IN1- OUT2 SIGN600005 2.2K
1uF 33K R6004 2 7
25V C6002 470K DTV/MNT_R_OUT
EU 6800pF
33pF C6003
IN1+
3
EU 6 IN2- R6008
EU
33K
OPT
R6010
OPT
C6007
1uF
25V
DTV/MNT_L_OUT
EU 470K
6800pF +3.5V_ST
VEE 5 IN2+ C
4 C6005 EU
33pF Q6000 B
SCART_AMP_L_FB MMBT3904(NXP)
R6012
4.7K
SCART_AMP_R_FB E EU
OPT
EU
R6013
510 SCART_MUTE
SCART_Lout
SCART_Rout
DTV/MNT_R_OUT
C
Q6001 B
MMBT3904(NXP)
E EU
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
CI POWER ENABLE CONTROL
+5V_CI_ON
+5V_NORMAL
Q6201
AO3407A
D
CI
C6202 R6248
OPT C6210
0.1uF 10K
G
1uF
16V C6207 CI
CI R6241 25V
22K 4.7uF OPT
R6221 10V
10K OPT
OPT
R6242
2.2K
CI
C
R6223
4.7K B Q6200
PCM_5V_CTL
MMBT3904(NXP)
CI CI
R6218
E
10K
CI
C6210-*1
1uF
25V
CI_MTK
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V_NORMAL
C6403 C6405
10uF 0.1uF
10V 16V
R6406
10
HP_LOUT
Close to the IC C6402 1/16W
1uF 5%
10V C6408
0.47uF
OUTL
SGND
+3.3V_NORMAL 16V
VDD
EN
C6406
C6400
1uF 16 15 14 13 2.2uF R6404
10V INL- HPVDD 10V 4.7K
HP_LOUT_MAIN 1 12
C
INL+ CPP R6405
2 11 Q6400 B 1K
MMBT3904(NXP) SIDE_HP_MUTE
IC6400 C6407
INR+ TPA6132A2 PGND 2.2uF
10V E From Micom
HP_AMP_MUTE
3 10
C6401
1uF
10V INR- CPN
4 EAN60724701 9
HP_ROUT_MAIN
5 6 7 8
R6400
R6402
4.7K
OUTR
G0
G1
HPVSS
4.7K
R6407
R6401
10
OPT
OPT
R6403 HP_ROUT
4.7K C6404 1/16W
2.2uF 5%
10V C6409
0.47uF
16V
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
T/C/S & H/NIM & T2/C TUNER(EU & CHINA)
RF_SWITCH_CTL USE: T2/C,T/C,ATSC,DTMB.ISDB-T LNB_TX CHB_CVBS
ERROR & VALID PIN
TU6504 TU6500 TU6501 TU6502 TU6503
LNB_OUT CHB_ERR L9_T2/C/S
THERMAL
PG GND NOT_T/C&AT 12K
0.1uF
R6528
9
GND_3 GND_3 2 7 11K 1/16W
SHIELD 29 29 DVB_S&CHB
1% 1%
R6529 R1
L6501 +1.23V_TU
EN ADJ
BLM18PG121SN1D R6523
10K 10K
SD_1.23V_DEMOD
30 +1.23V_S2_DEMOD
30 DVB_S&CHB 3 6 1%
C6512 C6515 C6519 +3.3V_D_Demod NOT_T/C&AT VOUT NOT_T/C&AT
VIN
100pF 0.1uF 10uF C6533
SD_RESET 31 S2_RESET 31 DVB_S&CHB 10V
OPT
R6512 10uF
4 2A 5
DVB_S&CHB 2.2K +5V_NORMAL
16V VCTRL NC NOT_T/C&AT
R6513
SD_3.3V_DEMOD32 +3.3V_S2_DEMOD
32 10 EAN61387601 C6549
C6521 /S2_RESET
0.1uF DVB_S&CHB 10uF
N.C_8 33 S2_F22_OUTPUT 33 OPT +3.3V_D_Demod 16V
OPT
SD_SCL 34 S2_SCL 34 C6524 C6527 C6535
100pF 0.1uF 1uF
LNB_TX OPT OPT
SD_SDA 35 S2_SDA 35
R6503 22
LNB 36 C6517 DVB_S&CHB
I2C_SCL4 Vout=0.6*(1+R1/R2)
36 18pF
OPT 50V
GND_4 37 CHB : Max 480mA
38 R6504 22 else : Max 240mA
I2C_SDA4
C6518 DVB_S&CHB
SHIELD 18pF
LNB_OUT OPT 50V +3.3V_D_Demod +3.3V_TU
+1.8V_TU
SHIELD +3.3V_TU
IC6503
NOT_T/C&AT
L6506 AZ1117BH-1.8TRE1
BLM18PG121SN1D
NOT_T/C&AT
NOT_T/C&AT IN OUT
C6538 C6542 3 2
C6531 10uF 0.1uF 1 R6531
0.1uF 10V
ADJ/GND 1
BR_F/NIM_V CN_ATBM T2/C/S2
CN_LG3921 TU6503-*1
TU6501-*1 TU6501-*2 TDSQ-G351D
TDSN-B051F TDSN-C251D TU6501-*3
TDSN-C051D N.C_1
1
RF_S/W_CTL RF_S/W_CTL RESET
1 1 2
2
RESET
2
RESET 1
RF_S/W_CTL 3
SCL
SDA
C6546 C6548
RESET 4
SCL SCL
3 3 2
SCL
5
+B1[3.3V]
10uF 0.1uF
SDA SDA 3 SIF
4
+B1[3.3V]
4
+B1[3.3V] 4
SDA
6
7
+B2[1.8V]
Close to the tuner 10V 16V
5 5 CVBS
+B1[3.3V] 8
SIF SIF 5
6 6 N.C_2
9
+B2[1.8V] +B2[1.8V] SIF N.C_3
7 7 6 10
AT_H/NIM_V CVBS CVBS +B2[1.8V] 11
N.C_4
8 8 7
TU6500-*1 +B3[3.3V]
CVBS 12
TDSS-H151F NC_1 NC_1 8 +B4[1.23V]
9 9 13
NC_2 NC_2 NC_1 N.C_5
10 10 9 14
NC_2 GND_1
NC_3 NC_3
NC 11 11 10 15
ERROR BR_TW_CN_TUNER
1 +B3[3.3V] +B3[3.3V] 11
NC_3 16
465mA(MAX)
2
RESET 12
+B4[1.23V]
12
+B4[1.23V] 12
+B3[3.3V]
17
18
SYNC
VALID
R6532-*1
13 13
3
SCL
14
NC_4
14
NC_4 13
+B4[1.23V] 19
MCLK
D0
BLM18PG121SN1D 150mA(MAX)
NC_4 20
SDA GND GND 14
15 15 D1
4 21
ERROR ERROR GND D2
+B1[3.3V] 16 16 15 22
5 SYNC SYNC 16
ERROR 23
D3 120-ohm
6
SIF 17
18
VALID
17
18
VALID 17
SYNC 24
25
D4
D5
+3.3V_NORMAL +3.3V_TU
+B2[1.8V] MCLK MCLK VALID D6
7 18
8
CVBS
19
20
D0
19
20
D0 19
MCLK
26
27
D7
GND_2
+5V_NORMAL +5V_TU
D0 28
D1 D1 20
IF_AGC 21 21 29
GND_3
9 D1
DIF[P] 22
D2
22
D2 21
D2
30
+B5[1.23V]
33
+B6[3.3V]
S2_F22_OUTPUT
BLM18PG121SN1D 0
D5 D5 D4 S2_SCL
25 25 24 34
D5 S2_SDA
12 D6 D6 25 35
26 26 LNB
SHIELD 27
D7
27
D7 26
D6 36
GND_4
C6529 C6532 C6534
37
C6526 C6530 22uF C6536 C6539
D7 38
28 28 27
0.1uF 22uF 0.1uF
28 SHIELD 0.1uF 22uF 0.1uF
SHIELD SHIELD
16V 10V 16V 16V 10V 16V
SHIELD
10V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES Close to the tuner
Close to the tuner
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS TUNER 2011.11.21
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 65
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
DCDC_GND and A_GND are connected
DCDC_GND and A_GND are connected in pin#27
DVB-S2 LNB Part Allegro PCB_GND and A_GND are connected
(Option:LNB)
Input trace widths should be sized to conduct at least 3A
D6901-*1
LNB_SX34 D6903-*1
40V 40V
LNB_SX34
D6901
LNB_SMAB34 D6903
2A 40V 40V
LNB_SMAB34
3A
+12V_LNB
C6901 C6902 C6912 C6906
0.01uF 1uF 68uF 68uF
50V 50V 35V 35V LNB
LNB LNB LNB LNB L6900
33UH
LNB_OUT SP-7850_33 C6911
close to Boost pin(#1) C6910
0.1uF
2.4A 10uF
50V
25V close to VIN pin(#25)
LNB LNB
C6915 C6916 C6913 C6914 R6906 DCDC_GND DCDC_GND
18pF 18pF 33pF 33pF 2.2K
D6904 1W D6900 DCDC_GND
OPT LNB OPT LNB LNB A_GND
LNB MBR230LSFT1G
30V
LNB C6904 D6902
0.1uF LNB_SMAB34
Close to Tuner
Surge protectioin LNB 50V 40V
C6900
0.22uF
LNB 25V
D6902-*1
LNB_SX34
GNDLX
[EP]
NC_9
A_GND 40V
LNB
VIN
BFI
BFO
LX
A_GND
28
27
26
25
24
23
22
A_GND
BOOST 1 21 NC_8
C6903 0.1uF THERMAL
VCP 2 29 20 NC_7
11
12
13
14
8
+3.3V_NORMAL
Max 1.3A
GND
VREG
SDA
ADD
SCL
NC_2
IRQ
A_GND
+12V +12V_LNB
R6903
L6901
4.7K BLM18PG121SN1D
R6900 33
R6901 33
LNB
LNB
LNB
50V 50V
LNB LNB
27pF
27pF
LNB
OPT
OPT
C6907
C6908
C6909
A_GND
I2C_SDA4
I2C_SCL4
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
[51Pin LVDS Connector]
(For FHD FRC3 HS_LVDS)
P7200 L/DIM0_SCLK
FI-RE51S-HF-J-R1500
L/DIM0_MOSI
L/DIM0_VS
NC
1 I2C_BE_SDA1
L/DIM0_SCLK
NC
2 L/DIM0_MOSI I2C_BE_SCL1
NC
3 FRC3_RESET
L/DIM0_VS
NC
4 I2C_BE_SDA1
NC
5 I2C_BE_SCL1
NC
6 FRC3_RESET
LVDS_SEL
7
R7201
NC 0
8 FRC3_FLASH_WP
NC
9
R7200
10K
BPL_IN
L/DIM_ENABLE
10 LOCAL_DIM_EN
GND TP7204 LOCAL_DIM_EN
11
RA0N
12 TXA0N
RA0P
13 TXA0P
RA1N
14 TXA1N
RA1P
15 TXA1P
RA2N
16 TXA2N
RA2P
17 TXA2P
GND
18
RACLKN
19 TXACLKN
RACLKP
20 TXACLKP
GND
21
RA3N
22 TXA3N
RA3P
23 TXA3P
RA4N
24 TXA4N
RA4P
25 TXA4P
GND
26
BIT_SEL
27
RB0N
28 TXB0N
RB0P
29 TXB0P
RB1N
30 TXB1N
RB1P
31 TXB1P
RB2N
32 TXB2N
RB2P
33 TXB2P
GND
34
RBCLKN
35 TXBCLKN
RBCLKP
36 TXBCLKP
GND
37
RB3N
38 TXB3N
RB3P
39 TXB3P
RB4N
40 TXB4N
RB4P
41 TXB4P
GND PANEL_VCC
42
GND
43
GND L7200
44 120-ohm
GND
45
GND
46
NC C7200 C7201 C7202
47 10uF 1000pF 0.1uF
VLCD 16V 50V 16V
48 OPT OPT OPT
VLCD
49
VLCD
50
VLCD
51
52
GND
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
LOCAL DIMMING
[To LED DRIVER]
+3.3V_NORMAL
P7600
12507WR-08L R7600
10K
OPT
1
AR7600
R7601
10K
33
2 1/16W
3 L/DIM0_SCLK
5 L/DIM0_MOSI
6 I2C_SCL1
7 I2C_SDA1
8 R7606 33
L/DIM0_VS
9
R7607
4.7K
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
eMMC I/F
EMMC_VCCQ
47K
47K
47K
47K
R8117
R8116
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
EMMC DATA LINE
10K PULL/UP
R8100-*1
R8101-*1
R8102-*1
R8103-*1
R8104-*1
R8105-*1
R8106-*1
R8107-*1
R8100
R8101
R8102
R8103
R8104
R8105
R8106
R8107
IC8100 IC8100-*3
IC8100-*1 IC8100-*2
SDIN5D2-4G-974L1 H26M31001EFR
H26M21001ECR KLM2G1HE3F-B001
AR8100
EMMC_DATA[0-7] 22
1/16W
EMMC_DATA[0] A3 C8 A3 C8
DAT0 NC_25 DAT0 NC_25 A3 C8 A3 C8
EMMC_DATA[1] A4 C9 A4 C9 DAT0 NC_25 DAT0 NC_25
DAT1 NC_26 DAT1 NC_26 A4 C9 A4 C9
EMMC_DATA[2] A5 C10 A5 C10 DAT1 NC_26 DAT1 NC_26
DAT2 NC_27 DAT2 NC_27 A5 C10 A5 C10
EMMC_DATA[3] B2 C11 B2 C11 DAT2 NC_27 DAT2 NC_27
EMMC_DATA[4] DAT3 NC_28 DAT3 NC_28 B2 C11 B2 C11
B3 C12 B3 C12 DAT3 NC_28 DAT3 NC_28
EMMC_DATA[5] DAT4 NC_29 DAT4 NC_29 B3 C12 B3 C12
B4 C13 B4 C13 DAT4 NC_29 DAT4 NC_29
EMMC_DATA[6] DAT5 NC_30 DAT5 NC_30 B4 C13 B4 C13
B5 C14 B5 C14 DAT5 NC_30 DAT5 NC_30
EMMC_DATA[7] AR8101 DAT6 NC_31 DAT6 NC_31 B5 C14 B5 C14
22 B6 D1 B6 D1 DAT6 NC_31 DAT6 NC_31
1/16W DAT7 NC_32 DAT5 DAT7 NC_32 B6 D1 B6 D1
D2 D2 DAT7 NC_32 DAT7 NC_32
NC_33 NC_33 D2 D2
D3 D3 NC_33 NC_33
NC_34 NC_34 D3 D3
M6 D4 M6 D4 NC_34 NC_34
CLK NC_35 CLK NC_35 M6 D4 M6 D4
M5 D12 M5 D12 CLK NC_35 CLK NC_35
CMD NC_36 CMD NC_36 M5 D12 M5 D12
D13 D13 CMD NC_36 CMD NC_36
NC_37 NC_37 D13 D13
D14 D14 NC_37 NC_37
NC_38 NC_38 D14 D14
A6 E1 A6 E1 NC_38 NC_38
NC_3 NC_39 NC_3 NC_39 A6 E1 A6 E1
A7 E2 A7 E2 NC_3 NC_39 NC_3 NC_39
NC_4 NC_40 NC_4 NC_40 A7 E2 A7 E2
C5 E3 C5 E3 NC_4 NC_40 NC_4 NC_40
NC_23 NC_41 NC_23 NC_41 C5 E3 C5 E3
E5 E12 E5 E12 NC_23 NC_41 NC_23 NC_41
NC_42 NC_46 NC_42 NC_46 E5 E12 E5 E12
E8 E13 E8 E13 NC_42 NC_46 NC_42 NC_46
NC_43 NC_47 NC_43 NC_47 E8 E13 E8 E13
AR8102 22 E9 E14 E9 E14 NC_43 NC_47 NC_43 NC_47
EMMC_CLK NC_44 NC_48 NC_44 NC_48 E9 E14 E9 E14
E10 F1 E10 F1 NC_44 NC_48 NC_44 NC_48
EMMC_CMD NC_45 NC_49 DAT6 NC_45 NC_49 E10 F1 E10 F1
F10 F2 F10 F2 NC_45 NC_49 NC_45 NC_49
EMMC_RST NC_52 NC_50 NC_52 NC_50 F10 F2 F10 F2
G3 F3 G3 F3 NC_52 NC_50 NC_52 NC_50
NC_58 NC_51 NC_58 NC_51 G3 F3 G3 F3
G10 F12 G10 F12 NC_58 NC_51 NC_58 NC_51
NC_59 NC_53 NC_59 NC_53 G10 F12 G10 F12
H5 F13 H5 F13 NC_59 NC_53 NC_59 NC_53
NC_66 NC_54 NC_66 NC_54 H5 F13 H5 F13
J5 F14 J5 F14 NC_66 NC_54 NC_66 NC_54
C8107 NC_73 NC_55 NC_73 NC_55 J5 F14 J5 F14
OPT 10pF K6 G1 K6 G1 NC_73 NC_55 NC_73 NC_55
NC_80 NC_56 NC_80 NC_56 K6 G1 K6 G1
50V K7 G2 K7 G2 NC_80 NC_56 NC_80 NC_56
NC_81 NC_57 NC_81 NC_57 K7 G2 K7 G2
K10 G12 K10 G12 NC_81 NC_57 NC_81 NC_57
NC_82 NC_60 NC_82 NC_60 K10 G12 K10 G12
GED_SANDISK_EMMC_4GB
P7 G13 P7 G13 NC_82 NC_60 NC_82 NC_60
NC_116 NC_61 NC_116 NC_61 P7 G13 P7 G13
P10 G14 P10 G14 NC_116 NC_61 NC_116 NC_61
NC_119 NC_62 NC_119 NC_62 P10 G14 P10 G14
H1 H1 NC_119 NC_62 NC_119 NC_62
HYNIX_EMMC_2GB
NC_63 NC_63 H1 H1
DEV_GED_HYNIX_EMMC_4GB
H2 H2 NC_63 NC_63
NC_64 NC_64 H2 H2
K5 H3 K5 H3 NC_64 NC_64
RESET NC_65 RESET NC_65 K5 H3 K5 H3
H12 H12 RESET NC_65 RSTN NC_65
SAMSUNG_EMMC_2GB
C8100 NC_67 NC_67 H12 H12
0.1uF H13 H13 NC_67 NC_67
OPT NC_68 NC_68 H13 H13
16V C6 H14 C6 H14 NC_68 NC_68
VCCQ_1 NC_69 VCCQ_1 NC_69 C6 H14 C6 H14
EMMC_VCCQ 3.3V_EMMC M4 J1 M4 J1 VCCQ_1 NC_69 VDD_1 NC_69
VCCQ_2 NC_70 VCCQ_2 NC_70 M4 J1 M4 J1
N4 J2 N4 J2 VCCQ_2 NC_70 VDD_2 NC_70
VCCQ_3 NC_71 VCCQ_3 NC_71 N4 J2 N4 J2
P3 J3 P3 J3 VCCQ_3 NC_71 VDD_3 NC_71
VCCQ_4 NC_72 VCCQ_4 NC_72 P3 J3 P3 J3
P5 J12 P5 J12 VCCQ_4 NC_72 VDD_4 NC_72
VCCQ_5 NC_74 VCCQ_5 NC_74 P5 J12 P5 J12
DAT3
DAT4
DAT5
DAT6
EMMC_CLK_BALL
EMMC_CMD_BALL
EMMC_RESET_BALL
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.5V_ST
BLM18PG121SN1D
LOGO_LIGHT
P8900
L8900
12507WR-03L
R8900
100
10K
3
R8902
OPT
LOGO_LIGHT
4
C
LOGO_LIGHT
B
LOGO_LIGHT
LOGO_LIGHT
1K Q8900
LOGO_LIGHT
R8903
R8901
E
C8900 LOGO_LIGHT MMBT3904(NXP)
10K
0.1uF
16V
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC9300
LG1132
XTAL(24.75MHz)
R9300 R9302 R9304 R9306 R9308 R9310 R9329
100 100 100 100 100 100 1M SPI FLASH(4M Bit) IC9300
SOC_TXA0P
AB17
RXA0P TXA0P
A10
TXA0P
LG1132
+3.3V_NORMAL
AA17 B10 X9300
SOC_TXA0N RXA0N TXA0N TXA0N 24.75MHz +1.0VDC
Y16 C9 X-TAL_1 GND_2
SOC_TXA1P RXA1P TXA1P TXA1P XTAL_IN
Y17 C10 1 4
SOC_TXA1N RXA1N TXA1N TXA1N H8 E17
AA16 B9 GND_1 X-TAL_2 XTAL_OUT VDD_1 VSS_24
SOC_TXA2P RXA2P TXA2P TXA2P 2 3 H9 E18
AB16 A9 IC9301 VDD_2 VSS_25
SOC_TXA2N RXA2N TXA2N TXA2N H14 F5
AB15 A8 C9333 C9339 W25X40BVSSIG C9365 VDD_3 VSS_26
SOC_TXACLKP RXACLKP TXACLKP TXACLKP 30pF 30pF R9334 R9335 H15 F18
AA15 B8 0.1uF VDD_4 VSS_27
SOC_TXACLKN RXACLKN TXACLKN TXACLKN 50V 50V 4.7K 10K J8 G5
Y14 C7 OPT VDD_5 VSS_28
SOC_TXA3P RXA3P TXA3P TXA3P CS VCC J15 G18
LG1132_FLASH
Y15 C8 1 8 VDD_6 VSS_29
SOC_TXA3N RXA3N TXA3N TXA3N SPI_CS K8 H5
AA14 B7 VDD_7 VSS_30
SOC_TXA4P RXA4P TXA4P TXA4P K15 H18
AB14 A7 R9337 DO[IO1] HOLD R9343 VDD_8 VSS_31
SOC_TXA4N RXA4N TXA4N TXA4N 2 7 L8 J5
R9301 R9303 R9305 R9307 R9309 R9311 SPI_DI VDD_9 VSS_32
100 100 100 100 100 100 33 3.3K L15 J9
AB13 A6 VDD_10 VSS_33
SOC_TXB0P RXB0P TXB0P TXB0P WP CLK M8 J10
AA13 B6 SPI/I2C For Aardvak Interface FLASH_WP 3 6 SPI_SCLK M15
VDD_11 VSS_34
J11
SOC_TXB0N RXB0N TXB0N TXB0N
Y12 C5 VDD_12 VSS_35
R9336
1/16W
SOC_TXB1P RXB1P TXB1P TXB1P N8 J12
100K
Y13 C6 GND DI[IO0] VDD_13 VSS_36
SOC_TXB1N RXB1N TXB1N TXB1N 4 5 SPI_DO N15 J13
AA12 B5 +3.3V_NORMAL VDD_14 VSS_37
SOC_TXB2P RXB2P TXB2P TXB2P P9300 P8 J14
AB12 A5 VDD_15 VSS_38
SOC_TXB2N RXB2N TXB2N TXB2N 12507WR-10L P15 J18
AB11 A4 VDD_16 VSS_39
SOC_TXBCLKP RXBCLKP TXBCLKP TXBCLKP R8 K5
AA11 B4 VDD_17 VSS_40
SOC_TXBCLKN RXBCLKN TXBCLKN TXBCLKN R9 K9
Y10 C3 VDD_18 VSS_41
SOC_TXB3P RXB3P TXB3P TXB3P R10 K10
Y11 C4 1 VDD_19 VSS_42
SOC_TXB3N RXB3N TXB3N TXB3N R11 K11
AA10 B3 VDD_20 VSS_43
SOC_TXB4P RXB4P TXB4P TXB4P R12 K12
AB10 A3 2 VDD_21 VSS_44
SOC_TXB4N RXB4N TXB4N TXB4N SPI_CS R13 K13
VDD_22 VSS_45
R14 K14
AB9 A18 VDD_23 VSS_46
RXC0P TXC0P TXC0P R15 K18
AA9 B18 3 SPI_DO VDD_24 VSS_47
RXC0N TXC0N TXC0N +3.3V_IO L5
Y8 C17 VSS_48
RXC1P TXC1P TXC1P F4 L9
Y9
RXC1N TXC1N
C18
TXC1N 4 SPI_SCLK
TEST MODE Configuration G4
VDD33_1 VSS_49
L10
AA8 B17 VDD33_2 VSS_50
RXC2P TXC2P TXC2P LG1132 Has Internal Pull-up H4 L11
AB8 A17 VDD33_3 VSS_51
RXC2N TXC2N TXC2N Default Setting J4 L12
AB7 A16 5 SPI_DI All ’H’ = Normal Operation Mode VDD33_4 VSS_52
RXCCLKP TXCCLKP TXCCLKP K4 L13
AA7 B16 VDD33_5 VSS_53
RXCCLKN TXCCLKN TXCCLKN L4 L14
Y6 C15 6 TMODE[3:0] VDD33_6 VSS_54
RXC3P TXC3P TXC3P 3D_DEPTH_RESET M4 L18
Y7 C16 DEBUG 0000 => System PLL Test VDD33_7 VSS_55
P9301 RXC3N TXC3N TXC3N 0001 => LVDS Rx Isolation Test N4 M5
AA6 B15 VDD33_8 VSS_56
12507WS-04L +3.3V_NORMAL RXC4P TXC4P TXC4P OPT 0010 => LVDS Tx Isolation Test P4 M9
AB6 A15 7 R9330 0 TMODE0 VDD33_9 VSS_57
TXC4N 0011 => LVDS Bypass Test R4 M10
RXC4N TXC4N
0100 => ALL PLL Test R9338 100 OPT VDD33_10 VSS_58
TMODE0 T4 M11
AB5 A14 R9331 0 1001 => DDR PLL IsolationTest VDD33_11 VSS_59
TXD0P 8 FLASH_WP 1010 => Functional Test R9339 100 OPT U4 M12
1 RXD0P TXD0P TMODE1
AA5 B14 DEBUG 1011 => MBIST VDD33_12 VSS_60
RXD0N TXD0N TXD0N R9340 100 OPT +2.5V_LVDS_RX M13
Y4 C13 1100 => Scan Test(Normal) TMODE2 VSS_61
TXD1P R9332 0 W7 M14
RXD1P TXD1P 9 1101 => Scan Test (Adaptive) R9341 100 OPT
2 Y5 C14 I2C_SDA2 TMODE3 LVRX_VDD25_1 VSS_62
RXD1N TXD1N TXD1N +3.3V_NORMAL OPT 1110 => Display PLL Test W8 M18
AA4 B13 1111 => Normal Operation LVRX_VDD25_2 VSS_63
RXD2P TXD2P TXD2P W9 N5
AB4 A13 R9333 0 LVRX_VDD25_3 VSS_64
TXD2N 10 I2C_SCL2 W10 N9
DEBUG 3 RXD2N TXD2N
AB3 A12 OPT LVRX_VDD25_4 VSS_65
10K
10K
W11 N10
10K
10K
W14
OPT
OPT
TXD3N N13
OPT
RXD3N TXD3N
R9320
R9324
R9322
R9326
10K
10K
10K
100
U3 +3.3V_NORMAL LVTX_VDD25_4 VSS_79
GPIO[7] D11 R5
R9315 33 E2 U2 LVTX_VDD25_5 VSS_80
I2C_SDA2 SDA_M GPIO[8] D12 R18
R9316 33 E1 U1 LVTX_VDD25_6 VSS_81
I2C_SCL2 SCL_M GPIO[9] D13 T5
LVTX_VDD25_7
R9321
R9325
D1 T3 VSS_82
R9323
R9327
R9342
GPIO[10] R9328
R9318 33 E3 T2 LVTX_VDD25_8 VSS_83
I2C_SCL2 SCL_S GPIO[11] D15 T19
T1 SW9300 10K LVTX_VDD25_9 VSS_84
GPIO[12] OPT D16 U5
F2 R3 JTP-1127WEM LVTX_VDD25_10 VSS_85
U18
OPT 0
R9344
G3 R1 DISP_VDD VSS_87
DEBUG
Y22
1
I2C_SCL1 H1 N3 VSS_91
TRST_N TRST_N GPIO[19] AA19 V8
TRST_N H3 N2 DISP_AVDD VSS_92
R9319 33 AA20 V9
TDO TDO TDO GPIO[20]
H2 N1 DR3P_AVDD VSS_93
TDI TDI GPIO[21] AB20 V10
TDI J3 M3 SSP_AVDD VSS_94
+3.3V_XTAL_AVDD AB19 V11
TCK TCK TCK GPIO[22]
J2 M2 XTAL_AVDD VSS_95
TMS TMS GPIO[23] V12
TMS M1 VSS_96
GPIO[24] V13
F3 L1 Monitoring Pins for VSS_97
3D_DEPTH_RESET PORES_N GPIO[25] 3D-Depth Interanl status A2 V14
L2 VSS_1 VSS_98
GPIO[26] A19 V15
AB21 L3 VSS_2 VSS_99
XTAL_OUT XTALO GPIO[27] B19 V16
AA21 K1 VSS_3 VSS_100
XTAL_IN XTALI GPIO[28] C19 V17
K2 VSS_4 VSS_101
GPIO[29] D4 V18
K3 VSS_5 VSS_102
GPIO[30] D5 V19
J1 VSS_6 VSS_103
GPIO[31] D6 W4
VSS_7 VSS_104
D17 W5
VSS_8 VSS_105
D18 W6
VSS_9 VSS_106
D19 W15
+1.0V Power Separation E4
VSS_10 VSS_107
W16
VSS_11 VSS_108
E5 W17
VSS_12 VSS_109
+3.3V_IO Decaps +1.0VDC E6
VSS_13 VSS_110
W18
TXA0P TXC0P +2.5V LVDS_RX Decaps E7 W19
VSS_14 VSS_111
TXA0N TXC0N E8 W20
+3.3V_IO +2.5V_LG1132 +2.5V_LVDS_RX +2.5V_LVDS_RX VSS_15 VSS_112
TXA1P TXC1P E9 W21
VSS_16 VSS_113
TXA1N TXC1N E10 W22
C9353 C9361 VSS_17 VSS_114
TXA2P TXC2P L9303 E11 Y18
BLM18SG121TN1D 4.7uF 4.7uF
VSS_18 VSS_115
TXA2N TXC2N 10V 10V E12 Y19
VSS_19 VSS_116
TXACLKP TXCCLKP E13 AA1
C9300 C9304 C9308 C9311 C9312 VSS_20 VSS_117
C9315 C9318 C9321 C9324 C9327 C9330 E14 AA18
TXACLKN TXCCLKN 0.1uF 0.1uF 0.1uF 10uF 10uF
4.7uF 4.7uF 0.1uF 0.1uF 0.1uF 0.1uF VSS_21 VSS_118
TXA3P TXC3P 16V 16V 16V 10V 10V E15 AB18
OPT OPT OPT 10V 10V 16V 16V 16V 16V
OPT OPT VSS_22 VSS_119
TXA3N TXC3N E16
VSS_23
TXA4P TXC4P
TXA4N TXC4N
+1.0VDC Decaps
TXB0P TXD0P
+1.0VDC
TXB0N TXD0N +3.3V Power Separation
TXB1P TXD1P +2.5V LVDS_TX Decaps
TXB1N TXD1N
TXB2P TXD2P +3.3V_NORMAL +3.3V_IO +2.5V_LVDS_TX +2.5V_LVDS_TX
+2.5V_LG1132
TXB2N TXD2N L9300 C9348 C9354 C9356 C9360 C9364 C9366
TXBCLKP TXDCLKP BLM18SG121TN1D L9304
BLM18SG121TN1D 0.1uF 0.1uF 10uF 10uF 0.1uF 0.1uF
TXBCLKN TXDCLKN 16V 16V 10V 10V 16V 16V
OPT OPT OPT OPT M9300 ALBLOCK
TXB3P TXD3P C9301 C9303
C9316 C9319 C9322 C9328 MDS62110213
TXB3N TXD3N 4.7uF 4.7uF
4.7uF 4.7uF 0.1uF 0.1uF
TXB4P TXD4P 10V 10V
10V 10V 16V 16V ALBLOCK
OPT M9301
TXB4N TXD4N
MDS62110213
M9302 ALBLOCK
MDS62110213
+3.3V XTAL AVDD Decaps
+1.0V_XTAL/DDR3 PLL/SS PLL/DIS PLL_VDD
M9303 ALBLOCK
+3.3V_XTAL_AVDD
+2.5V DDR PLL/SS PLL/DIS PLL AVDD Decaps +1.0V_PLL_VDD
+3.3V_IO +3.3V_XTAL_AVDD +1.0VDC +1.0V_PLL_VDD MDS62110213
+2.5V_LG1132 +2.5V_AVDD +2.5V_AVDD
L9302 L9309
BLM18SG121TN1D L9305 BLM18SG121TN1D For Heat Sink
BLM18SG121TN1D
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
DDR0 PHY VREF
+1.5VQ +0.75V_VREF_M0 +1.5VQ +0.75V_VREF_M1
+1.5V_LG1132
IC9400 IC9300 +1.5VQ
DDR_A[0-13]
H5TQ1G63DFR-PBC +0.75V_VREF_M0 LG1132 R9406 R9410
DDR_A[0-13] 1K 1K
1% 1%
+0.75V_VREF_M1
DDR_A[0] N3 M8
A0 VREFCA DDR_A[0] V21
DDR_A[1] P7 DDR_A[0] L9400
A1 DDR_A[1] B22 BLM18SG121TN1D
DDR_A[2] P3 DDR_A[1]
A2 DDR_A[2] V20 R9407 R9411
DDR_A[3] N2 H1 DDR_A[2] 1K C9413 C9417 1K C9420 C9422
A3 VREFDQ DDR_A[3] T20 1% 0.1uF 1000pF 1% 0.1uF 1000pF
DDR_A[4] P8 DDR_A[3]
A4 DDR_A[4] C22 C9401 C9407
DDR_A[5] P2 DDR_A[4] 4.7uF 4.7uF
A5 R9402 DDR_A[5] T21
DDR_A[6] R8 L8 +1.5VQ DDR_A[5]
A6 ZQ 240 1% DDR_A[6] C21
DDR_A[7] R2 DDR_A[6]
A7 DDR_A[7] T22
DDR_A[8] T8 DDR_A[7]
A8 DDR_A[8] C20
DDR_A[9] R3 B2 DDR_A[8]
A9 VDD_1 DDR_A[9] U22
DDR_A[10] L7 D9 DDR_A[9]
A10/AP VDD_2 DDR_A[10] D22
DDR_A[11] R7 G7 DDR_A[10] +1.5VQ +1.5VQ
A11 VDD_3 DDR_A[11] B21 +0.75V_VREF_D0 +0.75V_VREF_D1
DDR_A[12] N7 K2 Connect A13 for DDR_A[11]
A12/BC VDD_4 DDR_A[12] D20
DDR_A[13] T3 K8 Using 2Gbit Memory DDR_A[12]
A13 VDD_5 DDR_A[13] U21
N1 DDR_A[13]
Connect A13 for VDD_6 B20
M7 N9 DDR_DATA[0-15] DDR_A[14]
Using 2Gbit Memory A15 VDD_7
R1
VDD_8 DDR_DATA[0] M22 R9404 R9408
M2 R9 DDR_DQ[0]
DDR_BA[0] BA0 VDD_9 DDR_DATA[1] G20
N8 DDR_DQ[1] 1K 1K
DDR_BA[1] BA1 DDR_DATA[2] N20 1% 1%
M3 DDR_DQ[2]
DDR_BA[2] BA2 DDR_DATA[3] F22 R9405 R9409
A1 DDR_DQ[3] C9400 1K C9406 C9410 C9415 1K C9419 C9421
VDDQ_1 DDR_DATA[4] N22 0.1uF 1% 0.1uF 1000pF 0.1uF 1% 0.1uF 1000pF
J7 A8 DDR_DQ[4]
DDR_CLK 100 1% CK VDDQ_2 DDR_DATA[5] F20
R9401 K7 C1 DDR_DQ[5]
DDR_CLKN CK VDDQ_3 DDR_DATA[6] N21
K9 C9 DDR_DQ[6]
DDR_CKE CKE VDDQ_4 DDR_DATA[7] F21
D2 DDR_DQ[7]
+1.5VQ VDDQ_5 DDR_DATA[8] H21
L2 E9 DDR_DQ[8]
CS VDDQ_6 DDR_DATA[9] L22
K1 F1 DDR_DQ[9]
DDR_ODT ODT VDDQ_7 DDR_DATA[10] G22
J3 H2 DDR_DQ[10]
DDR_RASN RAS VDDQ_8 DDR_DATA[11] M20
R9400 K3 H9 DDR_DQ[11]
DDR_CASN CAS VDDQ_9 DDR_DATA[12] H22
200 L3 DDR_DQ[12]
DDR_WEN WE DDR_DATA[13] L21
J1 DDR_DQ[13]
NC_1 DDR_DATA[14] H20
T2 J9 DDR_DQ[14]
DDR_RESET_N RESET NC_2 DDR_DATA[15] L20
L1 DDR_DQ[15]
NC_3
L9
NC_4 E22 +1.5VQ
F3 T7 DDR_CLK DDR_CK
DDR_DQS[0] DQSL NC_6 E21
G3 DDR_CLKN DDR_CK_N DDR3 1.5V Decaps - Place these caps near Memory
DDR_DQS_N[0] DQSL K22
DDR_DQS[0] DDR_DQS[0]
K21
C7 A9 DDR_DQS_N[0] DDR_DQS_N[0]
DDR_DQS[1] DQSU VSS_1 J22
B7 B3 DDR_DQS[1] DDR_DQS[1]
DDR_DQS_N[1] DQSU VSS_2 J21
E1 DDR_DQS_N[1] DDR_DQS_N[1]
VSS_3 E20
E7 G8 DDR_CKE DDR_CKE
DDR_DATA[0-15] DDR_DM[0] DML VSS_4 R20 C9402 C9404 C9405 C9408 C9411 C9412 C9414 C9416 C9418
D3 J2 DDR_WEN DDR_WE_N
DDR_DM[1] DMU VSS_5 P20
J8 DDR_RASN DDR_RAS_N 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
VSS_6 P21 OPT OPT OPT OPT
DDR_DATA[0] E3 M1 DDR_CASN DDR_CAS_N
DQL0 VSS_7 P22
DDR_DATA[1] F7 M9 DDR_ODT DDR_ODT
DQL1 VSS_8 G21
DDR_DATA[2] F2 P1 DDR_DM[0] DDR_DM[0]
DQL2 VSS_9 M21
DDR_DATA[3] F8 P9 DDR_DM[1] DDR_DM[1]
DQL3 VSS_10 R21
DDR_DATA[4] H3 T1 DDR_BA[0] DDR_BA[0]
DQL4 VSS_11 +0.75V_VREF_D0 D21
DDR_DATA[5] H8 T9 DDR_BA[1] DDR_BA[1]
DQL5 VSS_12 R22
DDR_DATA[6] G2 DDR_BA[2] DDR_BA[2]
DQL6 U20
DDR_DATA[7] H7 +0.75V_VREF_D1 DDR_RESET_N DDR_RST_N
DQL7 R9403 240 A20
B1 DDR_ZQ_CAL
VSSQ_1 1%
DDR_DATA[8] D7 B9
DQU0 VSSQ_2 V22
DDR_DATA[9] C3 D1 DDR_VREF0 DDR3 1.5V/0.75V Decap
DQU1 VSSQ_3 A21
DDR_DATA[10] C8 D8 DDR_VREF1 - Place these caps near IC101
DQU2 VSSQ_4
DDR_DATA[11] C2 E2
DQU3 VSSQ_5 E19
DDR_DATA[12] A7 E8 DDR_VDDQ_1 +0.75V_VREF_D0 +0.75V_VREF_D1
DQU4 VSSQ_6 F19
DDR_DATA[13] A2 F9 DDR_VDDQ_2
DQU5 VSSQ_7 G19
DDR_DATA[14] B8 G1 DDR_VDDQ_3
DQU6 VSSQ_8 H19
DDR_DATA[15] A3 G9 DDR_VDDQ_4
DQU7 VSSQ_9 J19
DDR_VDDQ_5
+1.5VQ J20 C9403 C9409
DDR_VDDQ_6
K19 0.1uF 0.1uF
DDR_VDDQ_7
K20
DDR_VDDQ_8
L19
DDR_VDDQ_9
M19
DDR_VDDQ_10
N19
DDR_VDDQ_11
P19
DDR_VDDQ_12
R19
DDR_VDDQ_13
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
3D-Depth Analog for 2.5V
+2.5V_LG1132
+2.5V
IC9500
+1.5V_LG1132 AP7173-SPG-13 HF(DIODES)
+1.5V_DDR Max 600 mA
+3.3V_NORMAL [EP]
L9500 IN OUT
1 8
THERMAL
BLM18PG121SN1D PG FB
9
+5V_USB 2 7
R9502
VCC SS 4.3K R1
5.48VTO5.76V
3 6 1% C9513 C9514
1.5A
ZD9500
C9500 10uF 0.1uF
10uF R9500
10K EN GND C9501 10V 16V
10V 4 5 R9501
2200pF 2K
50V 1% R2
Vout=0.8*(1+R1/R2)
+1.0VDC
+1.0V_VDD BLM18PG121SN1D
+1.0V_VDD
Max 2000 mA
C9502
10uF
NON_UD UD 16V
+1.0VDC CIC21J501NE
L9502
IC9501
TPS54327DDAR [EP]GND
POWER_ON/OFF2_3 R9504
10K EN VIN
1 8
**NON UD Model UD 16V
THERMAL
0.1uF
R1 1% VFB VBST C9506
9
2 7
UD
**UD Model UD
LG1132 DDR = 792Mhz Switching freq: 700K Vout=0.765*(1+R1/R2)
LG1152 1.0V ==> IC2501
LG1132 1.1V ==> IC2306
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LG1132 Power 2011. 06. 28
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR LG1132 POWER
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
+3.3V_NORMAL
R10006
R10007
10K
10K
+3.3V_NORMAL
+12V_MOTOR
IC10001
R10008
100
MOTOR_CLOSE_SW BD6222HFP
R10023
R10022
4.7K
4.7K
R10009 VREF
1
100
C10004 C10005
MOTOR_OPEN_SW OPT
R10020 0
OUT1
ZD10000
ZD10001
UDZS8.2B
UDZS8.2B
L/DIM0_VS
0.1uF 0.1uF MOTOR+ 2
8.2V
8.2V
16V 16V
R10029
GND
4
R10028
OUT2
R10018 0 MOTOR- 6
A_DIM
OPT R10034 1 VCC
7
P10000 R10033 1
12507WR-06L
MOTOR_SENSOR
CLOSE
1
R10027 0
JP10000 MOTOR_SENSOR
OPEN
2 MOTOR_SENSOR
JP10001
3
L10000
JP10002
MLB-201209-0120P-N2
4 MOTOR-
JP10003
L10001
5 MOTOR+
JP10004 MLB-201209-0120P-N2
6 C10000 C10001
OPT 0.1uF 0.1uF OPT
7 50V 50V
MOTOR DRIVER
+12V +12V_MOTOR
MAX 1500mA
Close to IC7406 MLB-201209-0120P-N2
MLB-201209-0120P-N2 L10003
L10002
C10011 C10012
C10009 10uF 0.1uF
50V 50V
0.1uF
50V MOTOR Ground
+12V_MOTOR
+12V_MOTOR
+12V_MOTOR
R10014
MOTOR_SENSOR
1/16W
MOTOR_SENSOR
+12V_MOTOR
MOTOR_SENSOR_UP
22K
IC10000
MOTOR_SENSOR
R10004
1%
MOTOR_SENSOR
1/10W
R10024
MOTOR_SENSOR KA4558D
1/16W
C10002
1K
1%
D10000 MOTOR_SENSOR
20K
0.1uF
1%
BAT54SWT1 25V
JP10006 R10012
MOTOR_SENSOR R10010 0 20K 1 8
A AC MO_SENS_TO_MAIN_DOWN 1 8
MOTOR_SENSOR_UP
C MOTOR_SENSOR MOTOR_SENSOR
R10013
R10030 JP10007
E R10016 0 2 7 20K 0 R10036
10K
+3.3V_NORMAL R10003 2 7
OPT
MOTOR_SENSOR_O MO_SENS_TO_MAIN_UP
MOTOR_SENSOR
10K
MOTOR_SENSOR MOTOR_SENSOR_UP
R10026
R10011
R10001
1/16W B C10006 3 6
MOTOR_SENSOR
C10007 R10021 0
1/16W
10K
10K
MOTOR_SENSOR_UP
MOTOR_SENSOR_UP
3 6
OPT
1% Q10001 0.1uF MOTOR_SENSOR_O
0.1uF
22K
C
1%
MOTOR_SENSOR_UP
R10015
MMBT3906(NXP) 50V
R10035
MOTOR_SENSOR
50V
1/10W
10K
C 4 5
12K
MOTOR_SENSOR_O 0.1uF
MOTOR_SENSOR_UP
B Q10000
R10025
50V 50V
1/10W
2SC3052 JP10005 C10010 50V
R10005
MOTOR_SENSOR
MOTOR_SENSOR
MOTOR_SENSOR
22K
0.1uF MOTOR_SENSOR_UP
1/8W
C10003
1%
E
51K
1%
0.1uF 50V
R10000
R10002
MOTOR_SENSOR
1/16W
MOTOR_SENSOR
1/16W
50V MOTOR_SENSOR_UP
18K
1%
1K
1%
MOTOR_SENSOR
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IR BLASTER
IR_Bla IR_Bla
JP11002
Pattern Width : 0.5mm R11020 Pattern Width : 0.5mm
+3.3V_NORMAL +3.3V_IR_Bla 0 R 1
D11001
+3.3V_IR_Bla
IR_Bla
IR_Bla C DETECT 3
IR_Bla L11001 JP11001
D
SBT2222A_AUK L 4
IR_Bla BLM18PG121SN1D
IR_Bla
C11009 IR_Bla
D11002
AO3438 E
0.1uF GND 5
Q11002 R11019
G
+5V_NORMAL 16V
0 KJA-PH-0-0177
OPT IR_Bla
JK11001
IR_Bla C11004 C11008 C11006
R11021 10uF 10uF 0.1uF
10V 16V
10K IR_Bla IR_Bla OPT
Close to JK11001
+3.3V_IR_Bla
+3.3V_IR_Bla
P11001
12507WS-04L
IC11002
MC96FR3128R 1
IR_Bla
VSS VDD
1 28 2
IR_Bla DEV_IR_Bla
P11/KS9/MISO1 P06/KS6
6 23
P14/KS12/SS1/INT2 P03/KS3/T3/PWM3
9 20
P31/XCK0/SENSOR P36/INT0/XCK0
14 15
R11006 22 IR_Bla
IRB_SPI_MOSI
R11007 22 IR_Bla
IRB_SPI_MISO
R11008 22 IR_Bla
IRB_SPI_SS
R11009 22 IR_Bla
IRB_SPI_CK
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
All of OPT decaps must be placed on PCB Bottom side
IC100 The Vx1_HS Tx AC-coupling Caps must be IC100 IC100
LG1122 placed near by LG1122 LG1122 +0.9VDC
LG1122
+3.3V_IO
R103
3.3K
R104
3.3K
R105
3.3K
15
DISPLAY_OPT OLED LCD
R177 OPT 0
8 FLASH_WP 8
R178 0 9
9 I2C_SDA_S
Write Protection
- HIGH : Normal Operation R179 0
- LOW : Write Protection 10 I2C_SCL_S
11
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC200 IC100 IC201
DDR0_A[0-12] LG1122 DDR1_A[0-12]
H5TQ1G63DFR-PBC +0.75V_VREF0_M0 H5TQ1G63DFR-PBC +0.75V_VREF1_M0
DDR0_A[0-12] DDR1_A[0-12]
+0.75V_VREF0_M1 +0.75V_VREF1_M1
DDR0_A[0] N3 M8 DDR0_A[0] AB25 AE9 DDR1_A[0] DDR1_A[0] N3 M8
A0 VREFCA DDR0_A[0] DDR1_A[0] A0 VREFCA
DDR0_A[1] P7 DDR0_A[1] F26 AF25 DDR1_A[1] DDR1_A[1] P7
A1 DDR0_A[1] DDR1_A[1] A1
DDR0_A[2] P3 DDR0_A[2] AB24 AD9 DDR1_A[2] DDR1_A[2] P3
A2 DDR0_A[2] DDR1_A[2] A2
DDR0_A[3] N2 H1 DDR0_A[3] Y24 AD11 DDR1_A[3] DDR1_A[3] N2 H1
A3 VREFDQ DDR0_A[3] DDR1_A[3] A3 VREFDQ
DDR0_A[4] P8 DDR0_A[4] G26 AF24 DDR1_A[4] DDR1_A[4] P8
A4 DDR0_A[4] DDR1_A[4] A4
DDR0_A[5] P2 DDR0_A[5] Y25 AE11 DDR1_A[5] DDR1_A[5] P2
A5 R202 DDR0_A[5] DDR1_A[5] A5 R223
DDR0_A[6] R8 L8 +1.5VQ0 DDR0_A[6] G25 AE24 DDR1_A[6] DDR1_A[6] R8 L8
A6 ZQ 240 1% DDR0_A[6] DDR1_A[6] A6 ZQ 240 1%
DDR0_A[7] R2 DDR0_A[7] Y26 AF11 DDR1_A[7] DDR1_A[7] R2 +1.5VQ1
A7 DDR0_A[7] DDR1_A[7] A7
DDR0_A[8] T8 DDR0_A[8] G24 AD24 DDR1_A[8] DDR1_A[8] T8
A8 DDR0_A[8] DDR1_A[8] A8
DDR0_A[9] R3 B2 DDR0_A[9] AA26 AF10 DDR1_A[9] DDR1_A[9] R3 B2
A9 VDD_1 DDR0_A[9] DDR1_A[9] A9 VDD_1
DDR0_A[10] L7 D9 DDR0_A[10] H26 AF23 DDR1_A[10] DDR1_A[10] L7 D9
A10/AP VDD_2 DDR0_A[10] DDR1_A[10] A10/AP VDD_2
DDR0_A[11] R7 G7 DDR0_A[11] F25 AE25 DDR1_A[11] DDR1_A[11] R7 G7
A11 VDD_3 DDR0_A[11] DDR1_A[11] A11 VDD_3
DDR0_A[12] N7 K2 DDR0_A[12] H24 AD23 DDR1_A[12] DDR1_A[12] N7 K2
A12/BC VDD_4 DDR0_A[12] DDR1_A[12] A12/BC VDD_4
T3 K8 AA25 AE10 T3 K8
A13 VDD_5 DDR0_A[13] DDR1_A[13] A13 VDD_5
N1 F24 AD25 N1
VDD_6 DDR0_DATA[0-15] DDR0_A[14] DDR1_A[14] VDD_6
M7 N9 M7 N9
A15 VDD_7 A15 VDD_7
R1 DDR0_DATA[0] T26 AF15 DDR1_DATA[0] DDR1_DATA[0-15] R1
VDD_8 DDR0_DQ[0] DDR1_DQ[0] VDD_8
M2 R9 DDR0_DATA[1] L24 AD20 DDR1_DATA[1] M2 R9
DDR0_BA[0] BA0 VDD_9 DDR0_DQ[1] DDR1_DQ[1] DDR1_BA[0] BA0 VDD_9
N8 DDR0_DATA[2] U24 AD14 DDR1_DATA[2] N8
DDR0_BA[1] BA1 DDR0_DQ[2] DDR1_DQ[2] DDR1_BA[1] BA1
M3 DDR0_DATA[3] K26 AF21 DDR1_DATA[3] M3
DDR0_BA[2] BA2 DDR0_DQ[3] DDR1_DQ[3] DDR1_BA[2] BA2
A1 DDR0_DATA[4] U26 AF14 DDR1_DATA[4] A1
VDDQ_1 DDR0_DQ[4] DDR1_DQ[4] VDDQ_1
J7 A8 DDR0_DATA[5] K24 AD21 DDR1_DATA[5] J7 A8
DDR0_CLK 100 1% CK VDDQ_2 DDR0_DQ[5] DDR1_DQ[5] DDR1_CLK 100 1% CK VDDQ_2
R201 K7 C1 U25 AE14 R222 K7 C1
DDR0_CLKN DDR0_DATA[6] DDR1_DATA[6] DDR1_CLKN
CK VDDQ_3 DDR0_DQ[6] DDR1_DQ[6] CK VDDQ_3
K9 C9 DDR0_DATA[7] K25 AE21 DDR1_DATA[7] K9 C9
DDR0_CKE CKE VDDQ_4 DDR0_DQ[7] DDR1_DQ[7] DDR1_CKE CKE VDDQ_4
D2 DDR0_DATA[8] M25 AE19 DDR1_DATA[8] D2
+1.5VQ0 VDDQ_5 DDR0_DQ[8] DDR1_DQ[8] +1.5VQ1 VDDQ_5
L2 E9 DDR0_DATA[9] R26 AF16 DDR1_DATA[9] L2 E9
CS VDDQ_6 DDR0_DQ[9] DDR1_DQ[9] CS VDDQ_6
K1 F1 DDR0_DATA[10] L26 AF20 DDR1_DATA[10] K1 F1
DDR0_ODT ODT VDDQ_7 DDR0_DQ[10] DDR1_DQ[10] DDR1_ODT ODT VDDQ_7
J3 H2 DDR0_DATA[11] T24 AD15 DDR1_DATA[11] J3 H2
DDR0_RASN RAS VDDQ_8 DDR0_DQ[11] DDR1_DQ[11] DDR1_RASN RAS VDDQ_8
R200 K3 H9 DDR0_DATA[12] M26 AF19 DDR1_DATA[12] R221 K3 H9
DDR0_CASN CAS VDDQ_9 DDR0_DQ[12] DDR1_DQ[12] DDR1_CASN CAS VDDQ_9
150 L3 DDR0_DATA[13] R25 AE16 DDR1_DATA[13] 150 L3
DDR0_WEN WE DDR0_DQ[13] DDR1_DQ[13] DDR1_WEN WE
J1 DDR0_DATA[14] M24 AD19 DDR1_DATA[14] J1
NC_1 DDR0_DQ[14] DDR1_DQ[14] NC_1
T2 J9 DDR0_DATA[15] R24 AD16 DDR1_DATA[15] T2 J9
DDR0_RESET_N RESET NC_2 DDR0_DQ[15] DDR1_DQ[15] DDR1_RESET_N RESET NC_2
L1 L1
NC_3 NC_3
L9 J26 AF22 L9
NC_4 DDR0_CLK DDR0_CK DDR1_CK DDR1_CLK NC_4
F3 T7 J25 AE22 F3 T7
DDR0_DQS[0] DQSL NC_6 DDR0_CLKN DDR0_CK_N DDR1_CK_N DDR1_CLKN DDR1_DQS[0] DQSL NC_6
G3 P26 AF17 G3
DDR0_DQS_N[0] DQSL DDR0_DQS[0] DDR0_DQS[0] DDR1_DQS[0] DDR1_DQS[0] DDR1_DQS_N[0] DQSL
P25 AE17
DDR0_DQS_N[0] DDR0_DQS_N[0] DDR1_DQS_N[0] DDR1_DQS_N[0]
C7 A9 N26 AF18 C7 A9
DDR0_DQS[1] DQSU VSS_1 DDR0_DQS[1] DDR0_DQS[1] DDR1_DQS[1] DDR1_DQS[1] DDR1_DQS[1] DQSU VSS_1
B7 B3 N25 AE18 B7 B3
DDR0_DQS_N[1] DQSU VSS_2 DDR0_DQS_N[1] DDR0_DQS_N[1] DDR1_DQS_N[1] DDR1_DQS_N[1] DDR1_DQS_N[1] DQSU VSS_2
E1 J24 AD22 E1
VSS_3 DDR0_CKE DDR0_CKE DDR1_CKE DDR1_CKE VSS_3
E7 G8 W24 AD12 E7 G8
DDR0_DATA[0-15] DDR0_DM[0] DML VSS_4 DDR0_WEN DDR0_WE_N DDR1_WE_N DDR1_WEN DDR1_DM[0] DML VSS_4
D3 J2 V24 AD13 DDR1_DATA[0-15] D3 J2
DDR0_DM[1] DMU VSS_5 DDR0_RASN DDR0_RAS_N DDR1_RAS_N DDR1_RASN DDR1_DM[1] DMU VSS_5
J8 V25 AE13 J8
VSS_6 DDR0_CASN DDR0_CAS_N DDR1_CAS_N DDR1_CASN VSS_6
DDR0_DATA[0] E3 M1 V26 AF13 DDR1_DATA[0] E3 M1
DQL0 VSS_7 DDR0_ODT DDR0_ODT DDR1_ODT DDR1_ODT DQL0 VSS_7
DDR0_DATA[1] F7 M9 L25 AE20 DDR1_DATA[1] F7 M9
DQL1 VSS_8 DDR0_DM[0] DDR0_DM[0] DDR1_DM[0] DDR1_DM[0] DQL1 VSS_8
DDR0_DATA[2] F2 P1 T25 AE15 DDR1_DATA[2] F2 P1
DQL2 VSS_9 DDR0_DM[1] DDR0_DM[1] DDR1_DM[1] DDR1_DM[1] DQL2 VSS_9
DDR0_DATA[3] F8 P9 W25 AE12 DDR1_DATA[3] F8 P9
DQL3 VSS_10 +0.75V_VREF0_D0 DDR0_BA[0] DDR0_BA[0] DDR1_BA[0] DDR1_BA[0] +0.75V_VREF1_D0 DQL3 VSS_10
DDR0_DATA[4] H3 T1 H25 AE23 DDR1_DATA[4] H3 T1
DQL4 VSS_11 DDR0_BA[1] DDR0_BA[1] DDR1_BA[1] DDR1_BA[1] DQL4 VSS_11
DDR0_DATA[5] H8 T9 W26 AF12 DDR1_DATA[5] H8 T9
DQL5 VSS_12 DDR0_BA[2] DDR0_BA[2] DDR1_BA[2] DDR1_BA[2] DQL5 VSS_12
DDR0_DATA[6] G2 +0.75V_VREF0_D1 AA24 AD10 +0.75V_VREF1_D1 DDR1_DATA[6] G2
DQL6 DDR0_RESET_N DDR0_RST_N DDR1_RST_N DDR1_RESET_N DQL6
DDR0_DATA[7] H7 R211 240 E25 AD26 R216 240 DDR1_DATA[7] H7
DQL7 DDR0_ZQ_CAL DDR1_ZQ_CAL DQL7
B1 1% 1% B1
VSSQ_1 VSSQ_1
DDR0_DATA[8] D7 B9 AB26 AF9 DDR1_DATA[8] D7 B9
DQU0 VSSQ_2 DDR0_VREF0 DDR1_VREF0 DQU0 VSSQ_2
DDR0_DATA[9] C3 D1 E26 AE26 DDR1_DATA[9] C3 D1
DQU1 VSSQ_3 DDR0_VREF1 DDR1_VREF1 DQU1 VSSQ_3
DDR0_DATA[10] C8 D8 J23 AC11 DDR1_DATA[10] C8 D8
DQU2 VSSQ_4 +1.5VQ0 DDR0_VDDQ_1 DDR1_VDDQ_1 +1.5VQ1 DQU2 VSSQ_4
DDR0_DATA[11] C2 E2 DDR1_DATA[11] C2 E2
DQU3 VSSQ_5 DQU3 VSSQ_5
DDR0_DATA[12] A7 E8 K23 AC12 DDR1_DATA[12] A7 E8
DQU4 VSSQ_6 DDR0_VDDQ_2 DDR1_VDDQ_2 DQU4 VSSQ_6
DDR0_DATA[13] A2 F9 L23 AC13 DDR1_DATA[13] A2 F9
DQU5 VSSQ_7 DDR0_VDDQ_3 DDR1_VDDQ_3 DQU5 VSSQ_7
DDR0_DATA[14] B8 G1 M23 AC14 DDR1_DATA[14] B8 G1
DQU6 VSSQ_8 DDR0_VDDQ_4 DDR1_VDDQ_4 DQU6 VSSQ_8
DDR0_DATA[15] A3 G9 N23 AC15 DDR1_DATA[15] A3 G9
DQU7 VSSQ_9 DDR0_VDDQ_5 DDR1_VDDQ_5 DQU7 VSSQ_9
P23 AC16
DDR0_VDDQ_6 DDR1_VDDQ_6
R23 AC17
DDR0_VDDQ_7 DDR1_VDDQ_7
T23 AC18
DDR0_VDDQ_8 DDR1_VDDQ_8
U23 AC19
DDR0_VDDQ_9 DDR1_VDDQ_9
V23 AC20
DDR0_VDDQ_10 DDR1_VDDQ_10
W23 AC21
DDR0_VDDQ_11 DDR1_VDDQ_11
DDR3 1.5V/0.75V Decap Y23 AC22
DDR0_VDDQ_12 DDR1_VDDQ_12 DDR3 1.5V/0.75V Decap
- Place these caps near IC100
- Place these caps near IC100
C206 C201 C202 C203 C204 C237 C238 C241 C242 C244
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C211 R206 C214 C215 C217 R210 C220 C221 C223 R215 C226 C227 C229 R220 C232 C233
1K 1K
0.1uF 1% 0.1uF 1000pF 0.1uF 1% 0.1uF 1000pF 0.1uF 1K 0.1uF 1000pF 0.1uF 1K 0.1uF 1000pF
1% 1%
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
FRC-III AIP for 1.8V TYP 0.278A FRC-III CORE for 0.9V TYP 2.521A
MAX 0.345A MAX 3.124A
VLCD_POWER
VLCD_POWER
(+12V)
(+12V)
L302 L306
MLB-201209-0120P-N2 MLB-201209-0120P-N2
+1.8V
OPT
C328 C326
C307 C309 C311
R1 IC300 10uF 10uF
0.1uF 10uF 10uF
25V 25V
R313 R304 TPS54327DDAR 16V 25V 25V +0.9V
[EP]GND OPT
0 C300 10K
22pF IC302 L304
+0.9V 3.6uH
R300 50V EN VIN AOZ1038PI [EP]LX
1 8
30K
THERMAL
1% +1.8V NR8040T3R6N
VFB VBST C305 PGND NC_2
9
Vout=0.765*(1+R1/R2) 2 7 1 8
R1
THERMAL
0.1uF 16V L300 C329 C332 C336
3.6uH +3.3V
VREG5 SW VIN NC_1 22uF 22uF 3300pF
9
R2 3 6 C334 R316 2 7
10V 10V 50V
100pF 0 R310
OPT
R301 NR8040T3R6N C322
SS GND 50V AGND EN 10K
22K 4 5
OPT R306 0.1uF 3 6
C312 C315
1% 4.7K 16V
C301 C303 22uF 22uF C320
1% FB COMP R312
1uF 3300pF 10V 10V 4 5
25V 50V R2 3.3K 4700pF
50V
R307
22K
1%
tss(ms)=[C303(nF)*Vref]/Iss(uA)
Vout=0.8*(1+R1/R2)
FRC-III DDR3 for 1.5V TYP 1.149A FRC-III I/O for 3.3V TYP 0.043A
MAX 1.184A MAX 0.046A
VLCD_POWER
(+12V)
VLCD_POWER
(+12V)
L307
MLB-201209-0120P-N2
THERMAL
1% C306 +1.5V 1% C323 +3.3V
VFB VBST VFB VBST
9
9
Vout=0.765*(1+R1/R2) 2 7 Vout=0.765*(1+R1/R2) 2 7
0.1uF 16V L301 0.1uF 16V L305
R2 VREG5 SW 3.6uH R2 VREG5 SW 3.6uH
3 6 3 6
R303 R309
NR8040T3R6N NR8040T3R6N
22K SS GND 22K SS GND
4 5 4 5
1% C314 C316 1% C331 C333
C304 22uF 22uF 22uF 22uF
C302 C319 C321
0.01uF 10V 10V 10V 10V
1uF 1uF 0.01uF OPT
50V
25V 25V 50V
tss(ms)=[C304(nF)*Vref]/Iss(uA) tss(ms)=[C321(nF)*Vref]/Iss(uA)
Ton_DIO 20us(min)
Ton_CORE 40us(min)
Core Power +0.9V
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
IC401 IC401
LGE5812B LGE5812B
[All of OPT decaps must be placed on PCB Bottom side]
+3.3VDD
TX0P A13 R1 D3 A5
RX0P LLV0P LLV0P VDD33_1 GND_39
TX0N B13 R2 D16 A14
RX0N LLV0N LLV0N VDD33_2 GND_40
TX1P A12 T1 E3 A16
RX1P LLV1P LLV1P VDD33_3 GND_41
TX1N B12 U1 E16 B1
RX1N LLV1N LLV1N VDD33_4 GND_42
TX2P A11 U2 F3 B2 +3.3AVDD_PLL Decaps
RX2P LLV2P LLV2P VDD33_5 GND_43
TX2N B11 V2 F16 B5
RX2N LLV2N LLV2N VDD33_6 GND_44
TX3P A10 T2 G3 B14 VCC_LCM
RX3P LLVCLKP LLVCLKP VDD33_7 GND_45
TX3N B10 T3 G16 B15 (+3.3V) +3.3AVDD_PLL +3.3AVDD_PLL
RX3N LLVCLKN LLVCLKN VDD33_8 GND_46
TX4P A9 V3 H3 B16
RX4P LLV3P LLV4P VDD33_9 GND_47
TX4N B9 U3 H16 B17 L400
RX4N LLV3N LLV4N VDD33_10 GND_48 MLB-201209-0120P-N2
TX5P A8 U4 J3 C2
RX5P LLV4P LLV5P VDD33_11 GND_49
TX5N B8 V4 J16 C3
RX5N LLV4N LLV5N VDD33_12 GND_50
TX6P A7 T4 K16 C4
RX6P LLV5P LLV6P VDD33_13 GND_51 C401 C407 C413
TX6N B7 T5 +3.3AVDD_TX C5 4.7uF 4.7uF 0.1uF
RX6N LLV5N LLV6N GND_52
TX7P A6 R6 C6 10V 10V 16V
RX7P AVDD33_TX_1 GND_53
TX7N B6 V5 R7 C7
RX7N LRV0P LRV0P AVDD33_TX_2 GND_54
U5 R8 C8
LRV0N LRV0N AVDD33_TX_3 GND_55
SOE R402 33 L1 U6 R9 C9
SOE LRV1P LRV1P AVDD33_TX_4 GND_56
GSP R403 33 M1 V6 R10 C10
GSP LRV1N LRV1N AVDD33_TX_5 GND_57
GOE R404 33 N2 T6 R11 C13
GOE LRV2P LRV2P AVDD33_TX_6 GND_58
GSC R405 33 N1 T7 R12 C14
GSC LRV2N LRV2N AVDD33_TX_7 GND_59
POL R406 33 E2 V7 R13 C15
POL LRVCLKP LRVCLKP AVDD33_TX_8 GND_60
FLK R407 33 F1 U7 +1.0VDD C16
FLK LRVCLKN LRVCLKN GND_61
DPM R408 33 F2 U8 G7 C17
DPM LRV3P LRV4P VDD10_1 GND_62
H_CONV R409 33 M2 V8 G12 D4 +1.0VDD_PLL Decaps
H_CONV LRV3N LRV4N VDD10_2 GND_63
OPT_P R410 33 D1 T8 H7 D5
OPT_P LRV4P LRV5P VDD10_3 GND_64
OPT_N R411 33 E1 T9 H12 D6 VCORE
OPT_N LRV4N LRV5N VDD10_4 GND_65
V9 J7 D7 (+1.0V) +1.0VDD_PLL +1.0VDD_PLL
LRV5P LRV6P VDD10_5 GND_66
RBF B4 U9 J12 D8
RBF LRV5N LRV6N VDD10_6 GND_67
1. RBF R412 33 A2 K7 D9 L401
- Pattern selection of No Video input LR_IND_OUT VDD10_7 GND_68 MLB-201209-0120P-N2
AGP_EN OPT A4 U10 K12 D10
LOW : Rolling Pattern AGP_EN RLV0P RLV0P VDD10_8 GND_69
HIGH : Black Pattern 3D_EN B3 V10 L7 D11
3D_EN RLV0N RLV0N VDD10_9 GND_70
3D_LR A3 T10 L12 D12
2. AGP_EN 3D_LR_IN RLV1P RLV1P VDD10_10 GND_71 C402 C408 C414
- NO input indicator T11 M7 D13 4.7uF 4.7uF 0.1uF
RLV1N RLV1N VDD10_11 GND_72
LOW : Normal R413 15K P1 V11 M8 D14 10V 10V 16V
HIGH : No input RMLVDS RLV2P RLV2P VDD10_12 GND_73
1% U11 M9 D15
RLV2N RLV2N VDD10_13 GND_74
3. 3D_EN N16 U12 M10 E4
- 2D/3D mode selection TMODE0 RLVCLKP RLVCLKP VDD10_14 GND_75
M18 V12 M11 E5
LOW : 2D mode TMODE1 RLVCLKN RLVCLKN VDD10_15 GND_76
HIGH : 3D mode L17 T12 M12 E6
TMODE2 RLV3P RLV4P VDD10_16 GND_77
L18 T13 +3.3AVDD_PLL E7
4. 3D_LR TMODE3 RLV3N RLV4N GND_78
- Left/Right frame Indicator K17 V13 B18 E8
TMODE4 RLV4P RLV5P AVDD33_PLL GND_79
LOW : Left K18 U13 +1.0VDD_PLL E9
HIGH : Right TMODE5 RLV4N RLV5N GND_80
J17 U14 A17 E10
TMODE6 RLV5P RLV6P VDD10_PLL GND_81
J18 V14 +3.3AVDD_VX1 E11
TMODE7 RLV5N RLV6N GND_82 +3.3VDD Decaps
H17 C11 E12
TMODE8 AVDD33_VX1_1 GND_83
H18 T14 C12 E13
SW400 TMODE9 RRV0P RRV0P +1.0VDD AVDD33_VX1_2 GND_84
VCC_LCM T15 E14 VCC_LCM
JTP-1127WEM RRV0N RRV0N GND_85
(+3.3V) TCON_SCL R414 33 F18 V15 G8 E15 (+3.3V) +3.3VDD
SCL_M RRV1P RRV1P AVDD10_VX1_1 GND_86
TCON_SDA R415 33 F17 U15 G9 F4
SDA_M RRV1N RRV1N AVDD10_VX1_2 GND_87
I2C_SCL_S R416 33 E18 U16 G10 F5 L402
SCL_S RRV2P RRV2P AVDD10_VX1_3 GND_88 MLB-201209-0120P-N2
I2C_SDA_S R417 33 E17 V16 G11 F14
SDA_S RRV2N RRV2N AVDD10_VX1_4 GND_89
T16 F15
R400 RRVCLKP RRVCLKP GND_90
10K TCON_RST C18 T17 L9 G4
RST_N RRVCLKN RRVCLKN GND_1 GND_91
V17 L10 G5 C403 C409
RRV3P RRV4P GND_2 GND_92 0.1uF 0.1uF
G17 U17 L11 G14
EEP_ADDR RRV3N RRV4N GND_3 GND_93 16V 16V
EEP_ADDR = HIGH -> EEPROM Address = 0xA6 WP_EEPROM_TCON R418 33 G18 U18 L14 G15
WP RRV4P RRV5P GND_4 GND_94
T18 L15 H4
RRV4N RRV5N GND_5 GND_95
R426 3.9K A15 R17 L16 H5
1% VX1_RBG RRV5P RRV6P GND_6 GND_96
D18 R18 M4 H8
No USE(NC at Rx side) HPD_VX1 RRV5N RRV6N GND_7 GND_97
TX_LOCK R425 33 D17 M5 H9
LOCKN_VX1 GND_8 GND_98
M14 H10
GND_9 GND_99
D2 M15 H11
GPIO0 GND_10 GND_100
C1 M16 H14
GPIO1 GND_11 GND_101
K3 N4 H15
GPIO2 GND_12 GND_102
L3 N5 J4 +3.3AVDD_TX Decaps
GPIO3 GND_13 GND_103
M3 N14 J5
GPIO4 GND_14 GND_104
N3 N15 J8 VCC_LCM
GPIO5 GND_15 GND_105
N17 P2 J9 (+3.3V) +3.3AVDD_TX
GPIO6 GND_16 GND_106
N18 P3 J10
GPIO7 GND_17 GND_107
M17 P4 J11 L403
GPIO8 GND_18 GND_108 MLB-201209-0120P-N2
P5 J14
GND_19 GND_109
K1 P6 J15
NC1 GND_20 GND_110
K2 P7 K4
NC2 GND_21 GND_111 C404 C410
J1 P8 K5 0.1uF 0.1uF
NC3 GND_22 GND_112
J2 P9 K8 16V 16V
NC4 GND_23 GND_113
H1 P10 K9
NC5 GND_24 GND_114
H2 P11 K10
NC6 GND_25 GND_115
G1 P12 K11
NC7 GND_26 GND_116
G2 P13 K14
NC8 GND_27 GND_117
L2 P14 K15
NC9 GND_28 GND_118
P15 L4
GND_29 GND_119
P16 L5
GND_30 GND_120
P17 L8
GND_31 GND_121
P18
GND_32
I2C Slave Address : 0x70 R3 +1.0VDD Decaps
GND_33
R4
GND_34
R5 VCORE
GND_35
R14 (+1.0V) +1.0VDD
GND_36
R15
GND_37
R16 L404
GND_38 MLB-201209-0120P-N2
C405 C411
4.7uF 4.7uF
10V 10V
[T-Con EEPROM(32KBIT)]
VCC_LCM
(+3.3V)
IC400
R401 R420 +3.3AVDD_VX1 Decaps
10K 10K AT24C32D-SSHM-T
1
R421 R423 R424
10K 2K 2K VCC_LCM
C400 +3.3AVDD_VX1
A0 VCC OPT (+3.3V)
1 8 0.1uF 2 TCON_SDA
16V L405
A1 WP MLB-201209-0120P-N2
2 7 WP_EEPROM_TCON 3 TCON_SCL
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
[PMIC Block] PANEL_VCC
(+12V)
SWB
VCC_LCM
(+3.3V)
R514
VL 0 L503
(+5V) 22uH
R533
2.2A 0
C510 C514 D503
10uF 10uF SMAB34 C532 C536 C538 C540 R536
R506 40V 1uF 22uF 22uF 0.1uF
150K 25V 25V 5.1K
1% 25V 10V 10V 50V
TCOMP
C527
PANEL_VCC 0.1uF
50V
(+12V) VCORE
TH500 R509
(+1.0V)
47k-ohm L502
120K
LQM2HPN2R2MG0L R527
R516
0 C534 C537
PVINB12_2
PVINB12_1
2.2uH 0
[EP]AGND
10uF 10uF
VLOGIC1
25V 25V
SWB1_2
SWB1_1
PGND2
NC_5
BST1
NC_4
SWB2
VL C515
(+5V) 1uF
25V
40
39
38
37
36
35
34
33
32
31
VCC_LCM VGL
EN1 1 30 VLOGIC2 (+3.3V) (-5V)
TCOMP 2 29 SDA R522 33
TCOMP THERMAL I2C_SDA_S D504 D505
VL 3 41 28 SCL R523 33 R531
I2C_SCL_S 1N4148W 1N4148W R544
C509 AGND 4 27 A0 10K
1uF AVIN RST
HVDD 25V C517 5 IC501 26 R521 33 TCON_RST 100V 100V 0
(+8.4V) 0.1uF C
L501 50V PVINB3 6 MAX17139 25 NC_3 R541
C546 C548 0 C552 C553 R545
10uH BST3 7 24 CTRLN B Q501 0.22uF 10uF 10uF 3.6K
R508 3.1A 2SC3052 0.22uF 50V 1/10W
SWB3 8 23 NC_2 VGH_S 50V 25V 25V
OUT3 VGL (+27V) E OPT
0 9 22 VGL_FB VGL_FB
R507 C504 C505 R515 0 PGND3 10 21 VGH
2.7K 10uF 10uF C516 VCC_LCM
C547 C549 R542
11
12
13
14
15
16
17
18
19
20
25V 25V 0.01uF 0.22uF 2K (+3.3V)
0.22uF 50V 1/8W
50V VCC_LCM R532 680 50V 1%
SS
COMP
PGND_1
PGND_2
SW_1
SW_2
SWI
SWO
NC_1
CTRLP
(+3.3V) OPT OPT
R543 0
OPT
C524 R525 C551
10K
SWB
0.1uF 0.1uF
50V 50V
OPT
R526
R518 10K VDD_LCM
33K
C522 OPT (+16.8V)
120pF
CTRLP
50V
C525
2200pF R535
50V
PANEL_VCC 0
(+12V) C531 C533 C535 R538
10uF 10uF 10uF
25V 25V 25V 9.1K
1/8W
R503
0
L500 D502
22uH SMAB34
40V
C501 C502 C519 C521 C523
10uF 10uF 0.1uF 10uF 10uF
25V 25V 50V 25V 25V
R513 C513
2.2 1000pF
C507
0.47uF
50V
VDD_LCM VGH_S
(+16.8V) C508 (+27V)
0.47uF Q500
50V
D500 D501 MMBT3906(NXP)
R510 1N4148W 1N4148W
10 R519
E
C512
0.1uF
50V
CTRLP
[P-Gamma Block]
GMA14 GMA18
I2C_SCL_S GMA13 I2C_SCL_S GMA17
[GPM Block]
PANEL_POWER HVDD
(+8.4V)
HVDD
(+8.4V)
R539 R550
33 33
VLCD_POWER
OPT PANEL_VCC C558
(+12V) C550 1uF
EP[GND]
EP[GND]
R501 33 1uF 25V
GSC 25V
HVDD
NC_1
HVDD
NC_1
VCC_LCM VCC_LCM
SCL
GM8
GM7
SCL
GM8
GM7
(+3.3V) (+3.3V)
R502 33 FLK
GPM_ON R534
IC500
20
19
18
17
16
20
19
18
17
16
VGH VGH_S L505 CIS21J121
R549
I2C_SDA_S 33 SDA GM6 I2C_SDA_S 33 SDA GM6
(+27V) (+27V) KIA3820FK 1 15 1 15
GMA12 GMA16
R528 THERMAL THERMAL
VCC_LCM VDD_LCM PANEL_CTL_MAIN A0 2 21 14 GM5 A0 2 21 14 GM5
C560 GMA10 GMA15
(+3.3V) (+16.8V) C559 0.1uF
R554 0 VGH GPM_ON VFLK 10K DVDD GM4 DVDD GM4
1 8 0.01uF 50V 3 13 3 13
50V IC502 GMA4 IC503 GMA9
GPM_OFF Q503
AO3407A PANEL_CTL_FRC C542 VCOM_GND 4 BUF08630 12 GM3 R548 C554 VCOM_GND 4 BUF08630 12 GM3
VGH_M GND R504 1uF GMA3 10K 1uF GMA7
S
10
OPT 1uF
25V
9
3 6 10uF 0.1uF G
DPM GPM_ON PANEL_CTL_FRC C564
GPM_ON 16V 50V
VCOM_FB
AVDD_AVDD
AVDD_1
BKSEL
GM1
VCOM_FB
AVDD_AVDD
AVDD_1
BKSEL
GM1
1% OPT 0.1uF
GPM_ON CE VDD 50V
4 5 R558 PANEL_CTL_FRC
1.8K
PANEL_CTL_FRC VDD_LCM VDD_LCM
C500 GMA1 GMA5
(+16.8V) (+16.8V)
R537
56pF 0 R552 0 VCOMOUT
R512 C
50V
OPT R540 R553 0
GPM_ON PANEL_CTL_FRC B Q502 10K VCOMFB
PANEL_CTL R529 0 R546 0
MMBT3904(NXP) R551
R556 PANEL_CTL_FRC 10K
10K E R530 10 R547 10
C555 C556 C557
C543 C544 C545 4.7uF 4.7uF 0.1uF
4.7uF 4.7uF 0.1uF 50V 50V 50V
50V 50V 50V
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
[80P mini-LVDS output wafer]
VDD_LCM
(+16V)
VCC_LCM
1 1 VDD (+3.3V) 1 GND
L/DIM0_SCLK C620
2 VDD 2 LLV0+
2 0.1uF LLV0P
L/DIM0_MOSI 3 GND 3 LLV0-
50V LLV0N
G
3 4 VCC 4 LLV1+
L/DIM0_VS LLV1P
VCC HVDD LLV1-
5 5 LLV1N
4 (+8V)
I2C_SDA_S 6 GND C607 C610 6 LLV2+
D
S
0.1uF 0.01uF LLV2P
5 7 HVDD 7 LLV2-
Q600 50V 50V LLV2N
2N7002K HVDD GND
8 VGL 8
6 LG1122_RST R600 33 GND (-5V) LLVCLK+
OPT 9 9 LLVCLKP
7 10 OPT_P 10 LLVCLK-
OPT_P LLVCLKN
11 VGL 11 GND
8 FLASH_WP GND LLV3+
12 12 LLV4P
9 13 GOE VGH 13 LLV3-
PWM_BPL GOE LLV4N
14 GSC (+27V) 14 LLV4+
10 GSC LLV5P
15 GND 15 LLV4-
+3.3V LLV5N
11 16 VGH 16 LLV5+
LLV6P
17 GND 17 LLV5-
12 LLV6N
RXA0N 18 RVCOM_FB 18 GND
VCOMFB
13 C621 19 VCOM_R 19 LRV0+
RXA0P VCOMOUT LRV0P
0.1uF 20 GND 20 LRV0-
14 LRV0N
RXA1N 50V 21 ZOUT 21 LRV1+
Z_OUT LRV1P
G
15 22 GND 22 LRV1-
RXA1P LRV1N
23 GMA1 23 LRV2+
16 GMA1 LRV2P
RXA2N I2C_SCL_S 24 GMA2 24 LRV2-
D
GMA2 LRV2N
17 25 GMA3 25 GND
RXA2P Q601 GMA3
2N7002K GMA4 LRVCLK+
26 GMA4 26 LRVCLKP
18 GMA5 LRVCLK-
R601 33 27 GMA5 27 LRVCLKN
19 OPT 28 GMA6 28 GND
RXACLKN GMA6
29 GMA7 29 LRV3+
20 GMA7 LRV4P
RXACLKP 30 GMA9 30 LRV3-
GMA9 LRV4N
21 31 GMA10 31 LRV4+
GMA10 LRV5P
32 GMA12 32 LRV4-
22 GMA12 LRV5N
RXA3N 33 GMA13 33 LRV5+
GMA13 LRV6P
23 34 GMA14 34 LRV5-
RXA3P GMA14 LRV6N
35 GMA15 35 GND
24 GMA15
RXA4N 36 GMA16 36 OPT_N
GMA16 OPT_N
25 37 GMA17 37 H_CONV
RXA4P GMA17 H_CONV
38 GMA18 38 GSP
26 GMA18 GSP
39 GND 39 POL
POL
27 40 GSP 40 GND
GSP
41 POL 41 SOE
28 POL SOE
RXB0N 42 GND 42 GND
29 43 SOE 43 GMA1
RXB0P SOE GMA1
44 H_CONV 44 GMA2
30 H_CONV GMA2
RXB1N 45 OPT_N 45 GMA3
OPT_N GMA3
31 46 GND 46 GMA4
RXB1P GMA4
47 RLV0+ 47 GMA5
32 RLV0P GMA5
RXB2N 48 RLV0- 48 GMA6
RLV0N GMA6
33 49 RLV1+ 49 GMA7
RXB2P RLV1P GMA7
50 RLV1- 50 GMA9
34 RLV1N GMA9
51 RLV2+ 51 GMA10
RLV2P GMA10
35 52 RLV2- 52 GMA12
RXBCLKN RLV2N GMA12
53 GND 53 GMA13
36 GMA13
RXBCLKP 54 RLVCLK+ 54 GMA14
RLVCLKP GMA14
37 55 RLVCLK- 55 GMA15
RLVCLKN GMA15
56 GND 56 GMA16
38 GMA16
RXB3N 57 RLV3+ 57 GMA17
RLV4P GMA17
39 58 RLV3- 58 GMA18
RXB3P RLV4N GMA18
59 RLV4+ 59 GND
40 RLV5P
RXB4N 60 RLV4- 60 GND
RLV5N
41 61 RLV5+ 61 ZOUT
RXB4P RLV6P Z_OUT
62 RLV5- 62 GND VGH
42 RLV6N
63 GND 63 VCOM_L (+27V)
VCOMOUT
43 64 RRV0+ 64 LVCOM_FB
RRV0P VCOMFB
65 RRV0- 65 GND
44 VLCD_POWER RRV0N
66 RRV1+ 66 VGH
RRV1P
45 (+12V) 67 RRV1- 67 GND VGL
RRV1N
68 RRV2+ 68 GSC (-5V)
46 RRV2P GSC
69 RRV2- 69 GOE
RRV2N GOE HVDD
47 L600 70 GND 70 GND
(+8V)
MLB-201209-0120P-N2 RRVCLK+ VGL
71 RRVCLKP 71
48 RRVCLK- GND
72 RRVCLKN 72
49 73 GND 73 HVDD
C600 C601
10uF 10uF 74 RRV3+ 74 HVDD
50 RRV4P VCC_LCM
25V 25V 75 RRV3- 75 GND
RRV4N (+3.3V)
51 76 RRV4+ 76 VCC
RRV5P
77 RRV4- 77 VCC
RRV5N
52 78 RRV5+ 78 GND
RRV6P
79 RRV5- 79 VDD
RRV6N
80 GND 80 VDD
C616 C618
0.1uF 0.01uF
81 81 50V 50V
VDD_LCM
(+16V)
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Revision History
-------------------------------------------------------------------------------------------------
(0) Proto Design
R104 R106
R100 R102 1.8K 270
10K 4.7K
P100
SW100 SW102 SW104 SW106
12507WR-04L JTP-1127WEM JTP-1127WEM JTP-1127WEM JTP-1127WEM
TP100
1 2 1 2 1 2 1 2
KEY1 1 3 4 3 4 3 4 3 4
KEY1
OPT
ZD100 VOL+ VOL- MENU ENTER
TP101
5.6B
GND 2
KEY2 3 KEY2
OPT
ZD101
GND 4 5.6B
3 4 3 4 3 4 3 4
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
LCD TV Repair Guide
`12 years New Models
V : T2/C/S2
T : T2/C
S : T/C/S2
0 : T/C
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
2 types of LED - Edge
Benefit: More Clear More Real
Feature
LED Array
Upper
Metal
BLU Cover
structure
Model
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
2 types of LED - ALEF
Benefit: More Clear More Real
Feature
Best picture quality + thin TV
ALEF Type ALEF LED`
Slimmer depth
Local Dimming better picture quality
Local Local dimming depicts more
Dimming deep black.
DBEF
Prism sheets
Diffuser plate
BLU
Light Blocking Pattern
structure
Guiding Layer Model
Reflecting coating w/patterns
XXLM960V
PCB LED Array is on the back of Module
47inch : H(6) * V(4) = 24Block
55inch : H(6) * V(4) = 24Block
Local
Dimming
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Main PCB for Broadband Main + TCON all in one
3 4
To PSU
1 Main processor_Digital(LG1152D),
1
DDR Memory
Flash Memory
To FRC BOARD
2 Main processor_analog(LG1152A)
6 2
5
Local Key +IR 4 Audio AMP (10W+10W)
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
FRC Board for Broadband Main + TCON all in one
XXLM960V-ZB
1 FRC Processor(LG1122)
2 T-Con IC(LG5812)
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Block Diagram
TS In(CHB) DTV TS
CVBS(CHB)
SIF(1 Ch) L9A AUD
L9D
SPIDF_OUT
Built-in WiFi
BB_TP_DATA
Audio L/R EB_DATA
(5 Ch)
CI Slot
Line-Out
SCART 16
I2S
CHB_DATA 16
DDR3 X 3
CVBS
(8 Ch) 16
CVBS-Out
SCART 8
DAC_DATA eMMC
Component
(2 Ch)
USB2.0x3
HDMI1
HDMI2 HDMI HDMI AAD_DATA RMII
SW (1 Ch) PHY
Ethernet
HDMI3
HDMI4
TXA/B
Keypad
MICOM
M-Remote_R/TX IR
Motion-R
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Jack Interface
COMP_Y+/Pb+/Pr+
AV_CVBS_IN COMP_DET
AV_L/R_IN
AV_CVBS_DET
SPDIF_OUT
SPDIF
PC_L/R_IN
PC_Audio
SC_DET
HP_L/ROUT
SC_CVBS_IN Earphone Block
SC_FB/ID_IN 2bit
EEPROM EDID_WP
SC_R/G/B 3bit IC802/
Main Chip R1EX24002ASAS0A
SC_L/R_IN
MICOM
RGB_DDC_SCL/SDA 2bit
DSUB_R/G/B 3bit
DTV/MNT_V_OUT
MUX
SCART IC2502
ATV_OUT
Tuner
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
L9 Block diagram
Mux
CPU I2S
24b@48KHz I2S(stero) Output
Audio L/R (5-ch) Audio Codec1 Dual C-A9 (1GHz)
1ch L/R 3(lrck, lrch, sck) SPDIF
SW (Digital Part)
Audio-ADC Graphic Engine
24b@48KHz 2D-VG / 3D Open-ES2.0
Tuner_CVBS
Video
Diplay
CVBS(6ch) Engine LVDS
CVBS AFE(2-ch) 12 : CVBS
SW
12b@54MHz
MC NR,
Video Vertical MC IPC
Component(2ch) 3ch Video 12
Capture LVDS LVDS Scaler, PE OSD
SW AFE OSD, VCR
Block LVDS
PC-RGB 10b@165MHz
(3CH)
Mux
w/ LLPLL
Mux
3D or UD LVDS 12 LVDS
HDMI(1ch)
HDMI-Rx 1.4 Data bridge
HDMI
ARC (1-port PHY) 8 I2S or SPDIF
(1-Link)
(1ch) 3D, ARC, 4kx2k Audio
1 (ARC data)
Ethernet USB2.0
DDR3(x16) * 3
Audio PLL 9 Audio Clocks MAC Host (x3)
w/ DCO
I2C I2C I2C I2C PHY
6(gbb, l9da) eMMC DDR3-PHY
Controller (3-port)
interrupt 3(hdmi, 3ch, gbb)
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
L9 Block diagram
30/48 Mhz
2 port USB PHY
Clock Divide & Reset generation USB controller
30/48Mhz w/ test logic
1 port USB PHY u_crg
1 Ghz CPU
DDR3PLL
SSC setting
- 0xFD3001D4
- 0xFD3001D8 Clock Divide & Reset generation Memory Controller
w/ test logic
xi_main
CT
R Clock Divide & Reset generation Memory Controller
24Mhz 1.6Ghz w/ test logic
DDR3PLL1 1.6Gh
0 1
xo_main
z i_m01_ddrclk
SSC setting
- 0xFD3001CC 1.6Ghz i_m2_ddrclk Clock Divide & Reset generation Memory Controller
0 1
- 0xFD3001D0 w/ test logic
0 1 800Mhzi_core800_clk
1/2
DDR3PLL2
1.6Ghz Video/Audio Block
800Mhzi_core320_clk CPU peripherial
SSC setting 1/5
- 0xFD3001C4 Clock Divide & Reset generation
- 0xFD3001D8 w/ test logic
dcoin_clk
27Mhz sclk
TE
About 220 internally generated clocks
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix. Block Diagram for Edge/ALEF Backlight
SPI/Vsync
LED
LED BLU
BLU control
control
RXBN 0~4
51Pin LVDS
RRV0~6P/N
DDR1_A[0~12]
RRV0~6P/N
DDR1_DATA[0~15]
IC201 DDR1
80Pin mini LVDS
DDR0_A[0~12]
DDR0_DATA[0~15]
IC200 DDR0
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Interconnection - 1
XXLM960V-ZB [PCBs]
1 Main PCB
2 LED driver
2
3 WIFI ASSY
7 4 RF MOTION ASSY
5 IR Key PCB
1
6 FRC ASSY
7 PSU
6
4 3
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Interconnection – sub PCB( XXLM960V Series )
5 IR Key PCB
4 RF MOTION ASSY
3
1
To Main
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Contents of LCD TV Standard Repair Process
No. Error symptom (High category) Error symptom (Mid category) Page Remarks
1 No video/Normal audio 1
2 No video/No audio 2
4 Color error 4
11 M4 operating checking 11
D. Function error
12 Wifi operating checking 12
13 External device recognition error 13
First of all, Check whether there is SVC Bulletin in GCSC System for these model.
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date 2012.01.16
LCD TV symptom
No video/ Normal audio Revised date 1/15
First of all, Check whether all of cables between board is inserted properly or not.
(Main B/D↔ Power B/D, LVDS Cable,Speaker Cable,IR B/D Cable,,,)
☞A1 ☞A4
No video Normal Y Check Back Light Y Check Power Normal Y Replace T-con
Normal audio On Board or module
audio On with naked eye Board voltage
24V, 12V,3.5V etc. And Adjust VCOM
N N N
Move to No
☞A2 Check Power Board 24V output Repair Power
video/No audio Board or parts
Replace Inverter
Normal Y
or module
voltage
End
N
Repair Power
Board or parts
1
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date 2012.01.16
LCD TV symptom
No video/ No audio Revised date 2/15
☞A4
Check various Check and
Normal Y
No Video/ voltages of Power replace
No audio Board ( 3.5V,12V,20V voltage?
MAIN B/D
or 24V…)
N End
Replace Power
Board and repair
parts
2
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date 2012.01.16
LCD TV symptom
Picture broken/ Freezing Revised date 3/15
N
☞ A7
Check RF Cable
Normal Y Check SVC N Check Y
Connection Close
1. Reconnection Picture? S/W Version Bulletin? Tuner soldering
2. Install Booster N
N Y
S/W Upgrade
Normal N Contact with signal distributor
Picture? or broadcaster (Cable or Air)
Normal N
Y Picture? Replace
Main B/D
Y
Close
Close
3
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error A. Video error date 2012.01.16
LCD TV symptom
Color error Revised date 4/15
☞A9 ☞ A10
※ Check Y
Check color by input
and replace
-External Input Y Y
Color Link Cable Color Color
-COMPONENT Replace Main B/D Replace module
error? (LVDS) and error? error?
-RGB
contact
-HDMI/DVI N N N
condition
☞A12 Check
External Input/ External device Y
external
Check Test pattern Component /Cable Replace Main B/D
device and
error normal
cable
N
Request repair
for external
device/cable
4
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error B. Power error date 2012.01.16
LCD TV symptom
No power Revised date 6/15
☞A17 ☞A19
DC Power on
Check Power LED Y Normal N Check Power Y Replace
by pressing Power Key OK? Power
Power LED On? operation? On ‘”High”
On Remote control B/D
. Stand-By: Red or Turn Off
N Y N
. Operating: Turn Off
Check Power cord Replace Main B/D
was inserted properly
☞A4
N Measure voltage of each output of Power B/D
Normal?
Y
Y Y
※ Normal
voltage?
Replace Main B/D
Close Normal
Check ST-BY 3.5V Y
voltage? N
☞A18
Replace Power B/D
N
Replace Power
B/D
6
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error B. Power error date 2012.01.16
LCD TV symptom
Off when on, off while viewing, power auto on/off Revised date 7/15
Check outlet
☞A22
N Y
Check A/C cord Error? Check Power Off CPU Normal? End
Replace Main B/D
Mode Abnormal
N
Check for all 3- phase
power out Y Abnormal Replace Power B/D
1
* Please refer to the all cases which Status Power off List Explanation
"POWEROFF_REMOTEKEY" Power off by REMOTE CONTROL
can be displayed on power off mode.
"POWEROFF_OFFTIMER" Power off by OFF TIMER
"POWEROFF_SLEEPTIMER" Power off by SLEEP TIMER
"POWEROFF_INSTOP" Power off by INSTOP KEY
"POWEROFF_AUTOOFF" Power off by AUTO OFF
Normal "POWEROFF_ONTIMER" Power off by ON TIMER
"POWEROFF_RS232C" Power off by RS232C
"POWEROFF_RESREC" Power off by Reservated Record
"POWEROFF_RECEND" Power off by End of Recording
"POWEROFF_SWDOWN" Power off by S/W Download
"POWEROFF_UNKNOWN" Power off by unknown status except listed case
"POWEROFF_ABNORMAL1" Power off by abnormal status except CPU trouble
Abnormal
"POWEROFF_CPUABNORMAL" Power off by CPU Abnormal
7
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error C. Audio error date 2012.01.16
LCD TV symptom
No audio/ Normal video Revised date 8/15
☞A24 ☞A25
Check user N Check audio B+ Y
No audio Normal
menu > Off 24V of Power
Screen normal voltage
Speaker off Board
Y N
Check N
Disconnection Replace MAIN Board End
Speaker
disconnection
Y
Replace Speaker
8
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error C. Audio error date 2012.01.16
LCD TV symptom
Wrecked audio/ discontinuation/noise Revised date 9/15
☞A25
Wrecked audio/
Check and replace
Discontinuation/ Check audio
speaker and
Noise for B+ Voltage (24V)
connector
Check input all audio
signal Y Y
Signal
-RF
normal? Wrecked audio/
-External Input Normal
signal Discontinuation/
N Replace Main B/D voltage?
Noise only
for D-TV
N
Wrecked audio/
Discontinuation/
Replace Power B/D
Noise only
for Analog
(When RF signal is not
received)
Request repair to external Wrecked audio/ Replace Main B/D End
cable/ANT provider Discontinuation/
Noise only
for External Input
(In case of N
External Input Connect and check Normal
signal error) other external audio?
Check and fix device
external device Y
9
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Replace R/C
10
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Normal Y
☞A7 operating? Close
Is show ok N Press the back
RF Receiver ver N message? key about 5sec
Close N
is “00.00”?
Y
Replace M4
Y Close
11
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
☞A7 ☞A29
Check the Wi-Fi Mac value N Check the Wifi wafer Normal N Replace
INSTART menu is “NG”? Voltage?
(P4301)_1pin Main B/D
Y
☞A29 Y
☞A7
Wi-Fi Mac value N
is “NG”? Close
12
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error D. Function error date 2012.01.16
LCD TV symptom
External device recognition error Revised date 13/15
Y Check technical
Check External Input and
Signal information Technical N
input Component Replace Main B/D
input? - Fix information information?
signal Recognition error
- S/W Version
N Y
RGB,HDMI/
Check and fix DVI, Optical
Fix in Replace Main B/D
external device/cable Recognition error
accordance
with technical
information
13
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error E. Noise date 2012.01.16
LCD TV symptom
Circuit noise, mechanical noise Revised date 14/15
14
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process
Established
Error F. Exterior defect date 2012.01.16
LCD TV symptom
Exterior defect Revised date 15/15
Cabinet
damage Replace cabinet
Remote
controller Replace remote controller
damage
Stand
dent Replace stand
15
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Contents of LCD TV Standard Repair Process Detail Technical Manual
17 B. Power error_ No power Check power input Voltage & ST-BY 3.5V A18
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_No video/Normal audio date
2011. 12 .14
LCD TV
Revised
Content Check LCD back light with naked eye A1
date
<XXLM9600>
After turning on the power and disassembling the case, check with the naked eye,
whether you can see light from 2 locations.
A1
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_No video/Normal audio date
2011. 12 .14
LCD TV
Revised
Content LED driver B+ 24V measuring method A2
date
1~5 24V
6 ~ 10 GND
11 Detect
12 Inverter On/Off
13 Int. PWM
A2
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_No video/Normal audio date
2011. 12 .14
LCD TV
Revised
Content Check White Balance value A3
date
<ALL MODELS>
Entry method
Entry method
1.
1. Press
Press the
the ADJ
ADJ button
button on
on the
the remote
remote controller
controller for
for adjustment.
adjustment.
2. Enter into
2. Enter into White
White Balance
Balance of
of item
item 10.
6.
3.
3. After
After recording
recording the
the R,
R, G,
G, B
B (GAIN,
(GAIN, Cut)
Cut) value
value of
of Color
Color Temp
Temp
(Cool/Medium/Warm),
(Cool/Medium/Warm), re-enter the value after replacing the
re-enter the value after replacing the MAIN
MAIN BOARD.
BOARD.
A3
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_No video/ Audio date
2011. 12 .14
LCD TV
Revised
Content Power Board voltage measuring method A4
date
ALEF LED
Check the DC 24V, 12V, 3.5V.
5 GND 6 GND
7 GND 8 GND
9 3.5V 10 3.5V
11 3.5V 12 3.5V
13 GND 14 GND
15 GND 16 N.C
(Only LPB : V-sync)
19 12V 20 N.C
(LPB, Lamp : A-dim)
23 N.C 24 Error-out
(only Lamp SCANNING Model
: PWM Dim #2)
A4
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_Video error, video lag/stop date
2011. 12 .14
LCD TV
TUNER input signal strength checking method Revised
Content A6
date
<ALL MODELS>
A6
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_Video error, video lag/stop date
2011. 12 .14
LCD TV
LCD-TV Version checking method Revised
Content A7
date
Version
A7
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom
A. Video error_Video error, video lag/stop 2011. 12 .14
LCD TV date
TUNER checking part Revised
Content A8
date
<ALL MODELS>
Checking method:
1. Check the signal strength or check whether the screen is normal when the external device is connected.
2. After measuring each voltage from power supply, finally replace the MAIN BOARD.
A8
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error A. Video error _Vertical/Horizontal bar, Established
symptom 2011. 12 .14
LCD TV residual image, light spot date
Revised
Content LCD TV connection diagram (1) A9
date
<ALL MODELS>
A9
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_Color error date
2011. 12 .14
LCD TV
Revised
Content Check Link Cable (LVDS) reconnection condition A10
date
<ALL MODELS>
Check the contact condition of the Link Cable, especially dust or mis insertion.
A10
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom
A. Video error_Color error 2011. 12 .14
LCD TV date
Adjustment Test pattern - ADJ Key Revised
Content A12
date
Checking item : 1. Defective pixel 2. Residual image 3. MODULE error (ADD-BAR,SCAN BAR..)
4.Video error (Classification of MODULE or Main-B/D!)
A12
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange T-Con Board (1)
Solder defect, CNT Broken Solder defect, CNT Broken Solder defect, CNT Broken
A - 1/5
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange T-Con Board (2)
Solder defect, Short/Crack Fuse Open, Abnormal power section Abnormal Display
A - 2/5
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange LED driver Board (PSU)
No picture/Sound Ok
A - 3/5
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange the Module (1)
Panel Mura, Light leakage Panel Mura, Light leakage Press damage
Un-repairable Cases
In this case please exchange the module.
Press damage
A - 4/5
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Appendix : Exchange the Module (2)
Un-repairable Cases
In this case please exchange the module.
Horizontal Block
Gate TAB IC Defect
Gate TAB IC Defect
A - 5/5
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom B. Power error _No power date
2011. 12 .14
LCD TV
Revised
Content Check front display LED A17
date
<XXLM9600>
A17
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom B. Power error _No power date
2011. 12 .14
LCD TV
Revised
Content Check power input voltage and ST-BY 3.5V A18
date
<XXLM9600>
5 GND 6 GND
7 GND 8 GND
9 3.5V 10 3.5V
11 3.5V 12 3.5V
13 GND 14 GND
15 GND 16 N.C
(Only LPB : V-sync)
19 12V 20 N.C
(LPB, Lamp : A-dim)
23 N.C 24 Error-out
(only Lamp SCANNING Model
: PWM Dim #2)
A18
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom B. Power error _No power date
2011. 12 .14
LCD TV
Revised
Content Checking method when power is ON A19
date
<XXLM9600>
5 GND 6 GND
7 GND 8 GND
9 3.5V 10 3.5V
11 3.5V 12 3.5V
13 GND 14 GND
15 GND 16 N.C
(Only LPB : V-sync)
19 12V 20 N.C
(LPB, Lamp : A-dim)
23 N.C 24 Error-out
(only Lamp SCANNING Model
: PWM Dim #2)
A19
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error
symptom B. Power error _Off when on, off whiling viewing Established 2011. 12 .14
LCD TV date
Revised
Content POWER OFF MODE checking method A22
date
<ALL MODELS>
Entry method
A22
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom C. Audio error_No audio/Normal video 2011. 12 .14
LCD TV date
Revised
Content Checking method in menu when there is no audio A24
date
<ALL MODELS>
Checking method
1. Press the Setting button on the remote controller
2. Select the Sound function of the Menu
3. Select the Sound Setting
4. Select TV Speaker from Off to On
A24
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom C. Audio error_No audio/Normal video date
2011. 12 .14
LCD TV
Voltage and speaker checking method Revised
Content A25
when there is no audio date
<XXLM9600>
③ Connect the tester RX1 to the speaker terminal and if you hear the Chik Chik sound when you touch the
GND and output terminal, the speaker is normal.
A25
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom D. Function error date
2011. 12 .14
LCD TV
Revised
Content Remote controller operation checking method A27
date
<XXLM9600>
P4102
1 SCL
2 SDA
3 GND
4 KEY1
5 KEY2
③ 6 St 3.5V
7 GND
8 GP4_LED_R
④ 9 IR
10 GND
Checking order
1, 2. Check IR cable condition between IR & Main board.
3. Check the st-by 3.3V on the terminal 6.
4. When checking the Pre-Amp when the power is in ON condition, it is normal when the
Analog Tester needle moves slowly, and defective when it does not move at all.
A27
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom D. Function error date
2011. 12 .14
LCD TV
Revised
Content Motion Remote operation checking method A28
date
<XXLM9600>
P4800
③ 1 3.3V
2 GND
3 RX
4 TX
5 RESET
6 DC
7 DD
8 GND
Checking order
1, 2. Check Motion cable condition between Motion assy & Main board.
3. Check the 3.3V on the terminal 1.
A28
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes
Standard Repair Process Detail Technical Manual
Error Established
symptom D. Function error date
2011. 12 .14
LCD TV
Revised
Content Wifi operation checking method A29
date
<XXLM9600>
P4301
③ 1 VDD
2 DM
3 DP
4 GND
②
①
Checking order
1, 2. Check Wifi cable condition between Wifi assy & Main board.
3. Check the 5V on the terminal 1.
A29
Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
Only for training and service purposes