International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882

Volume 4, Issue 3, March 2015

DESIGN AND SIMULATION OF CMOS 2-BIT HALF SUBTRACTOR

USING
32NM, 45NM AND 65NM FOUNDRY
Pranay Kumar Rahi1, Shashi Dewangan2, Nishant Yadav3
1
ME Scholar, 2Assistant Professor, 3MTech Scholar,
1
Department of Electronics & Communication Engineering
National Institute of Technical Teachers Training & Research
Chandigarh, UT, India
2
Department of Physics
Kamala Nehru College, Korba, Chhattisgarh, India
3
Department of Computer Science and Engineering,
Indian Institute of Technology, Kharagpur, West Bengal, India

ABSTRACT
In digital signal processing (DSP), image processing and
performing arithmetic operations in microprocessors
substractor plays an important role. In this paper, a 2-bit
half subtractor circuit has been designed and analyzed. A
comparative study has been done in account of the
silicon area and the power consumption in the designed
circuit using different channel lengths such as 65nm,
45nm and 32nm. The designed circuit has shown a
remarkable reduction in the consumed power of 84.64%
and a reduction of 67.08% in consumed area in 32nm
foundry as compared to 65nm CMOS foundry. The
design and simulation are performed of 2-bit half
subtractor using DSCH and MICROWIND tools.
KEYWORDS:
CMOS, VLSI, Subtractor, Power
consumption, CMOS technology.

I.

INTRODUCTION

In VLSI technology, to either speed up the operation or

reduce the power/energy consumption hardware
implementation of many applications such as multimedia
processing, digital communication can be possible [1].
Arithmetic circuits are important part of Digital circuits.
In the digital circuits, subtractor is one of the most
critical components used in the processor of portable
devices. Hence the area and power efficient design of 1bit Subtractor is necessary for design of small size
portable devices. There are various possible logic styles
that can give better performance as compared to the
basic CMOS logic style. The performance estimation of
1- Bit full Subtractor is based on area, delay and power
consumption. The purpose of this work is:

1. To perform the design, full custom implementation

and simulation of a 1-bit subtractor at the transistor level
by means of CMOS180nm technology.
2. To verify if the circuit can perform with all the
possible combinations of the inputs along with the logic
function.
3. To evaluate the quality of the output signals in terms
of voltage levels.
4. To assess the performance of the circuit in terms of
speed, area and power consumption.
The trend of CMOS technology improvement
continuous driven by the need to integrate more
functions into a given area of silicon. There three are
efficient ways of increasing the transistor current
capabilities:
1.
Increasing the supply voltage VDD, the supply
voltage tends to follow the opposite trend, for low power
consumption purpose.
2.
Reducing the distance L between the drain and
the source, the channel length is scaled with technology.
A scaling factor of 0.7 leads to a 33% increase in the
absolute.
3.
Decreasing the oxide thickness tOX, the gate
oxide leakage is exponentially increased which affect the
parasitic leakage current and consequently consumption
[2].
In the recent years various approaches of CMOS 1-Bit
full Subtractor design using various different logic styles
have been presented and unified into an integrated
design methodology [3].
Subtractor is a combinational circuit which represents
the smallest unit for subtraction in digital systems. It is
not only used for arithmetic calculation in many device
processors but also used in other part of processor for

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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 3, March 2015

calculating address. Stack pointer use subtraction

operation in push-pop logical operation for storage of
address. The simplest combinational circuit which
performs the arithmetic subtraction of two binary digits
is called half- Subtractor [4].

Fig 2: 2-bit Half Subtractor Circuits

Table-1 Truth Table of Half Subtractor
A
0
0
1
1

II. HALF-SUBTRACTOR CIRCUIT

A half- subtractor is a combinational circuit that subtract
One bit from the other and produces the difference. It
also has an output to specify if a 1 has been borrowed. It
is used to subtract the LSB of the subtrahend from the
LSB of the minuend when one binary number is
subtracted
from
the other [6]. The simplest
combinational circuit which performs the arithmetic
subtraction of two binary digits is called half Subtractor.
This is the necessary building block for designing a
VLSI system. Figure 1 shows the logic diagram of half
subtractor. In which, two inputs A and B are applied at
the different Gates and corresponding output are gotted.
These are the two inputs which consists of two 1-bit
numbers A and B, where A represents Minuend and B
represents Subtrahend. From the logic symbol, there are
two outputs corresponding inputs. Those output are the
difference (D) of A and B [4].

B
0
1
0
1

BOut
0
1
1
0

DIFFERENCE
1
1
0
0

The Boolean expression for the two output variables are

given by the equations
Difference =AB +A B =A+B and B(Out)= AB

III. LAYOUT SIMULATION

The layout is stick diagrammatic representation of
CMOS Half subtractor showing NMOS , PMOS,
P- diffusion, Metal Connect, N diffusion Layers
with A ,B as the inputs and Difference, Borrow as the
outputs. These layouts help as a reference model to
construct a complete half subtractor.

Fig 1 : Logic Symbol of half Subtractor [4]

A conventional Half-subtractor circuit is a combinational
circuit that can be used to subtract one binary digit from
another to produce a Difference output and a Borrow
output. The Borrow output here specifies whether a 1
has been borrowed to perform the subtraction. The HalfSubtractor at the gate-level can be shown as follows in
Figure 2 while the Table 2 gives us the truth table of the
Half-Subtractor which is obtained from the binary
arithmetic operations.

Fig 3: MICROWIND Layout design of Half Subtractor.

A simple domino logic circuit consists of a pull down
network, a P-type pull up transistor, an N-type footer
transistor a keeper transistor and an inverter. The clock
signal is connected to the gates of p-type pull up and ntype footer transistors. When clock goes low, the
dynamic node is pre-charged to VDD and the output
goes low in this condition. When the clock signal goes
high the circuit evaluate the logic function [6]. The
proposed 2-bit Half Subtractor circuit shown in figure 4,
uses two 2-bit
X-OR, one 2-bit OR and two 2-bit

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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 3, March 2015

AND logic gates. The schematic diagram of 2-bit half

subtractor as shown in figure 4.

Fig. 6: Output of half subtractor using 45 nm

CMOS Technology

Fig 4: DSCH schematic design of Half Subtractor.

IV. RESULT
A binary Half-Subtractor subtracts two input bits and
gives two output bits with one of them determining the
difference (D) of the two input bits while the other
giving the borrow bit (Bout). The proposed 2-bit Half
Subtractor are compared based on the performance
parameters like surface area and power dissipation. To
achieve better performance, the circuits are designed
using CMOS process by Microwind 3.1 in 65nm ,45nm
and 32nm technology. The timing diagram results of
proposed 1bit half subtractor using 65nm ,45nm and
32nm CMOS fabrication technology shown in Figure 57.

Fig. 7: Output of half subtractor using 65 nm CMOS

Technology
The comparative results for proposed 2-bit Half
Subtractor for 32nm, 45nm and 65 nm CMOS design
technology are given in Table-2.
Table 2. Power and surface area analysis of 2- Half
Subtractor in different CMOS technologies
CMOS
Technology

Parameters
Power
(in W)
Surface Area
(in m2)

.
Fig5: Output of half subtractor using 32 nm CMOS
Technology

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32 nm

45 nm

65 nm

0.276

0.377

1.797

5.3

8.2

16.1

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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 3, March 2015

[5]
A. Anand Kumar, Fundamentals of Digital
Circuits Second Edition, Prentice Hall of India, pp.
234-261, 2006.
[6]
D.Sivaranjani, J.Ajayan, S.Sivasankari, High
Performance Low Leakage Power Full Subtractor
Circuit Design Using Rate Sensing Keeper,
International Journal of Research in Engineering and
Technology (IJRET), eISSN: 2319-1163, pISSN: 23217308, Volume: 03 Special Issue: 07, pp. 648-654, May2014.
AUTHORS
Fig.8 Graphical Comparison of Power and Area

V. CONCLUSION
The performance of the half subtractor was Assessed in
terms of area and power consumption also quality of the
output signals [3]. The proposed 2-bit Half Subtractor
is simulated with 32 nm, 45nmAnd 65nm CMOS
technologies. The performance parameters power and
surface area are compared. The proposed 2-bit Half
Subtractor using the proposed logic in results reduction
in the power and surface area. The power required for
the half subtractor circuit in 32nm, 45nm and 65nm
CMOS technologies are 0.276 W, 0.377 W and 1.797
W respectively. The surface area consumed by the
circuit in 32nm, 45nm and 65nm CMOS technologies
are 5.3 m2, 8.2 m2, and 16.1 m2 respectively.

REFERENCES
[1]
Ruchika Sharma, Rajesh Mehra, Design And
Performance Analysis of CMOS Full Adder With 14
Transistor, International Journal of Computer
Technology and Applications (IJCTA), ISSN:22296093, Volume 5, pp. 1461-1465, July-August 2014.
[2]
Etienne Sicard, Sonia Delmas Benddhia,
Advanced CMOS Cell Design, Tata McGraw-Hill,
Second Edition, pp. 1-5, 2007.
[3]
Monikashree T.S, Usharani .S, Dr.J.S.Baligar,
Design and Implementation of Full Subtractor using
CMOS 180nm Technology, International Journal of
Science, Engineering and Technology Research
(IJSETR), ISSN: 2278 7798, Volume 3, Issue 5,pp.
1421-1426, May 2014.
[4]
Devendra Kumar Gautam, Dr. S R P Sinha, Er.
Yogesh Kumar Verma, Design a Low Power HalfSubtractor Using AVL Technique Based on 65nm
CMOS Technology, International Journal of Advanced
Research in Computer Engineering & Technology
(IJARCET), ISSN: 2278 1323 Volume 2, Issue 11, pp.
2891-2897,November 2013.

Pranay Kumar Rahi received the Bachelors of

Technology
degree
in
Electronics
and
Telecommunication Engi- neering from Government
Engineering College, Guru Gasidas
University,
Bilaspur, Chhattisgarh, India in 2004, and pursuing
Masters of Engineering in Electronics and
Communication Engineering from National Institute of
Technical Teachers Training & Research, Punjab
University, Chandigarh, India. His current research and
teaching interests are in Signal and Communications
Processing, Communication System. He has authored
more than 3 research publications.
Shashi Dewangan received the Bachelors of Science
degree from Agrasen Girls College, Korba, Chhattisgarh,
India in 111112007 and the Masters of Science
degree in Physics from Government Science College,
Guru Ghasidas University, Bilaspur, India in 2010.
She is an Assistant Professor in the Department of
Physics, Kamala Nehru College, Korba, India.

Nishant Yadav received the Bachelors of

Technology degree in Computer Science and
Engineering from Government Engineering College,
Guru Ghasidas University, Bilaspur, India in 2004, and
pursuing Masters
of
Engineering
Computer Science and Engineering
from
Indian
Institute of Technology, Kharagpur, India.

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