Ch05 - Basic Computer Organization and Design

Chap. 5 Basic Computer Org.
and Design
5-1
5-1 Instruction Codes

The user of a computer can control the process by means of a program.
A program is a set of instructions that specify the operations, operand, and
Instruction
Cycle
the sequence (control)

A instruction is a binary code that specifies a sequence of microoperations
Instruction codes together with data are stored in memory (=Stored Program
Concept)
The computer reads each instruction from memory and places it in a
control register. The control then interprets the binary code of the
instruction and proceeds to execute it by issuing a sequence of
microoperations.
Instruction Code :
z
z
A group of bits that instruct the computer to perform a specific operation

It is usually divided into parts(refer to Fig. 5-1 instruction format) Instruction Format
15
12 11
0
Operation Code :
Address
z The most basic part of an instruction code Op. Code
z A group of bits that define such operations as add, subtract, multiply, shift, and
complement(bit 12-15 : 24 = 16 distinct operations)
Computer System Architecture
Chap. 5 Basic Computer Organization and Design
Korea Univ. of Tech. & Edu.

Dept. of Info. & Comm.
5-2
Stored Program Organization : Fig. 5-1

z The simplest way to organize a computer
One processor register : AC (Accumulator)
The operation is performed with the memory operand and the content of AC
Instruction code format with two parts : Op. Code + Address

Exam)
Clear AC, Increment AC,
Complement AC, ...
Op. Code : specify 16 possible operations (4 bit)

Address : specify the address of an operand (12 bit)
If an operation in an instruction code does not need an operand from memory, the rest of the
bits in the instruction(address field) can be used for other purpose ( 16
instruction : Tab. 5-2 , 25 instruction)
Memory : 12 bit = 4096 word(Instruction and Data are stored)
Store each instruction code(program) and operand (data) in 16-bit memory word
Addressing Mode
z Immediate operand :
the second part of an instruction code(address field) specifies an operand
z
Direct address operand : Fig. 5-2(b)

the second part of an instruction code specifies the address of an operand
I=0 : Direct,
I=1 : Indirect
Indirect address operand : Fig. 5-2(c)

the bits in the second part of the instruction designate an address of a memory word
in which the address of the operand is found (Pointer )
One bit of the instruction code is used to distinguish between a direct and an
indirect address : Fig. 5-2(a)

5-3
Effective Address
z The operand address in computation-type instruction or the target address in a
branch-type instruction
5-2 Computer Registers

List of Registers for the Basic Computer : Tab. 5-1
Basic computer registers and memory : Fig. 5-3
z Data Register(DR) : hold the operand(Data) read from memory
z Accumulator Register(AC) : general purpose processing register
z Instruction Register(IR) : hold the instruction read from memory
z Temporary Register(TR) : hold a temporary data during processing
z Address Register(AR) : hold a memory address, 12 bit width
z Program Counter(PC) :
hold the address of the next instruction to be read from memory after the current
instruction is executed
Instruction words are read and executed in sequence unless a branch instruction is
encountered
A branch instruction calls for a transfer to a nonconsecutive instruction in the program
The address part of a branch instruction is transferred to PC to become the address of
the next instruction
To read instruction, memory read cycle is initiated, and PC is incremented by one (next
instruction fetch)

5-4
z
z
Input Register(INPR) : receive an 8-bit character from an input device

Output Register(OUTR) : hold an 8-bit character for an output device
Common Bus System

z The basic computer has eight registers, a memory unit, and a control unit(in Sec.
5-4)
z Paths must be provided to transfer information from one register to another and
between memory and registers
z A more efficient scheme for transferring information in a system with many
registers is to use a common bus(in Sec. 4-3)
z The connection of the registers and memory of the basic computer to a common
bus system : Fig. 5-4
The outputs of 8 registers and memory are connected to the common bus
The specific output is selected by mux (S0, S1, S2) :
Memory (7), AR (1), PC (2), DR (3), AC (4), IR (5), TR (6)

Device AC INPR OUTR
mux memory register bus
When LD (Load Input) is enable, the particular register receives the data from the bus
Control Input : LD, INC, CLR, Write, Read

Address Register : Address bus ( Bus address data )
AC DR memory read (p. 146, LDA )

Memory write AC write (p. 147, STA )

5-5
Accumulator(AC) : 3 Path
s2
s1
s0
1) Register Microoperation : clear AC, shfift

AC,
Memory unit
409616
Write
2) Data Register : add DR to AC, and DR to

AC( AC
End carry bit set/reset), memory READ
(DR )
LD
LD
D2T5 : AC DR, SC 0
CLR
INR
CLR
DR
3) INPR : Device
(Adder & Logic )
Adder
and
logic
INR
3
CLR
E
AC
LD
Note) Two microoperations can be executed

at the same time
INR
4
CLR
INPR
DR AC : s2 s1s0 = 100(4), DR (load )

AC DR : DR Adder & Logic AC (load )
INR
PC
LD
Read
AR
D2T4 : DR M [ AR ]
Address
Bus
IR
TR
LD
LD
INR
CLR
OUTR
LD
Clock
16-bit common bus
Fig. 5-4 Basic computer registers connected to a common bus


5-6
5-3 Computer Instruction

3 Instruction Code Formats : Fig. 5-5
z Memory-reference instruction
Opcode = 000 110
I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx
I=0 : Direct,
I=1 : Indirect
15 14
12 11
Opcode
Address
Register-reference instruction
7xxx (7800 ~ 7001) : CLA, CMA, .
15 14
12 11
Register Operation
Input-Output instruction
Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, .
15 14
12 11
Symbol
AND
ADD
LDA
STA
BUN
BSA
ISZ
CLA
CLE
CMA
CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT
INP
OUT
SKI
SKO
ION
IOF
Hex Code
I=0 I=1
0xxx 8xxx
1xxx 9xxx
2xxx Axxx
3xxx Bxxx
4xxx Cxxx
5xxx Dxxx
6xxx Exxx
7800
7400
7200
7100
7080
7040
7020
7010
7008
7004
7002
7001
F800
F400
F200
F100
F080
F040
Description
And memory word to AC
Add memory word to AC
Load memory word to AC
Store content of AC in memory
Branch unconditionally
Branch and Save return address
Increment and skip if zero
Clear AC
Clear E
Complement AC
Comp
m
e
Circulate right AC and E
Circulate left AC and E
Increment AC
Skip next instruction if AC positive
Skip next instruction if AC negative
Skip next instruction if AC zero
Skip next instruction if E is 0
Halt computer
Input character to AC
Output character from AC
Skip on input flag
Skip on output flag
Interrup
Inter
I/O Operation

5-7
If the computer includes a sufficient number of

Instruction Set Completeness
instructions in each of the following categories
z Arithmetic, Logical, and shift : CMA, INC, ..
z Moving information to and from memory and AC : STA, LDA
z Program control : BUN, BSA, ISZ
z Input/Output : INP, OUT
5-4 Timing and Control

Clock pulses
z A master clock generator controls the timing for all registers in the basic computer
z The clock pulses are applied to all F/Fs and registers in system
z The clock pulses do not change the state of a register unless the register is
enabled by a control signal
z The control signals are generated in the control unit : Fig. 5-6
The control signals provide control inputs for the multiplexers in the common bus,
control inputs in processor registers, and microoperations for the accumulator
Two major types of control organization

z Hardwired Control : Chap. 5
The control logic is implemented with gates, F/Fs, decoders, and other digital circuits
+ Fast operation, - Wiring change(if the design has to be modified)

5-8
Microprogrammed Control : Chap. 7

The control information is stored in a control memory, and the control memory is
programmed to initiate the required sequence of microoperations
+ Any required change can be done by updating the microprogram in control memory,
- Slow operation
Instruction register (IR)
Timing Signal = 4 X 16 Decoder +

4-bit Sequence Counter
11 - 0
38
decoder
7 6 5 4 3 2 1 0
I
Memory R/W cycle time > Clock

cycle time
, wait
cycle .
Other inputs
D0
.
.
D7 .
Exam) Control timing : Fig. 5-7

Sequence Counter is cleared when
D3T4 =1 : D3T4 : SC 0
12
Control
logic
gates
Control
outputs
T15
T0
.
.
.
Control Unit = Control Logic Gate +

3 X 8 Decoder + Instruction Register
+ Timing Signal
13
15 14
.
.
.
14
.
.
.
Control Unit : Fig. 5-6
15
10
416
decoder
4-bit
sequence
counter
(SC)
Increment(INR)
Clear(CLR)
Clock

5-9
Exam) Register transfer statement : T0 : AR PC

z A transfer of the content of PC into AR if timing signal T0 is active
1) During T0 active, the content of PC is placed onto the bus ( S2 S1S0 )

2) LD(load) input of AR is enabled, the actual transfer occurs at the next positive
transition of the clock(T0 rising edge clock)
T0 : Inactive
3) SC(sequence counter) is incremented : 0000(T0 ) 0001(T1 )
T1 : Active
5-5 Instruction Cycle
Instruction Cycle
z 1) Instruction Fetch from Memory
z 2) Instruction Decode
z 3) Read Effective Address(if indirect addressing mode)
z 4) Instruction Execution
z 5) Go to step 1) : Next Instruction[PC + 1]
Continue
indefinitely
unless HALT
instruction is
encountered
Instruction Fetch : T0, T1(Fig. 5-8)

T0 : AR PC
T1 : IR M [ AR ], PC PC + 1
z
T0 = 1
T0 : AR PC
1) Place the content of PC onto the bus by making the bus selection inputs S2S1S0=010
2) Transfer the content of the bus to AR by enabling the LD input of AR

5-10
T1 = 1
T1 : IR M [ AR ], PC PC + 1
1) Enable the read input memory

2) Place the content of memory onto the bus by making S2S1S0= 111
3) Transfer the content of the bus to IR by enable the LD input of IR
4) Increment PC by enabling the INR input of PC
Instruction Decode : T2
T2 : D0 ,...., D7 Decode IR (12 14), AR IR (0 11), I IR (15)
Op.code
T1=1
s2
T0=1
s1
Address Di/Indirect
Memory
Memory unit
unit
>
Bus
s0
IR(12-14) Fig. 5-6 D0 - D7
Address
Read
Instruction Execution : T3, T4, T5, T6

IR(12 14)
= 111
Read effective
Register(I=0)
D7IT3(Execute)
Address
I/O
(I=1)
D7IT3 (Execute)
D7IT3( AR M [ AR ] )
D7=0 : Memory Ref. Indirect(I=1)
Direct (I=0)
nothing in T3
> Register I/O T3 Memory Ref.
T3 Operand effective address
D7=1
>
Memory Ref. T4, T5, T6 :

Fig. 5-11
Flowchart for instruction cycle(Initial

Configuration) : Fig. 5-9
AR
PC
LD
INR
IR
LD
Clock
Common bus

0
1
0
1
1
1
5-11
Register Ref. Instruction

Address
z r = D7IT3 :

z IR(i) = Bi
IR(0 -11)
> B0 - B11 : 12 Register Ref.
Instruction (Tab. 5-3)
Fig. 5-9 Flowchart for instruction cycle(initial)

Start
SC
0
T0
AR
5-6 Memory Ref. Instruction
PC
T1
IR
M[AR], PC
PC+1
IR(12,13,14)
3X8
Decoder
D7 : Register or I/O = 1
= 111
D6 - D0 : 7 Memory Ref.
Instruction(Tab. 5-4)
T2
Decode operation code in IR(12-14)
AR
IR(0-11), I
I(15)
(Register or I/O) = 1
0 = (Memory-reference
I
AND to AC
(I/O) = 1
D0T4 : DR M [ AR ]
0 = (register)
(indirect) = 1
D0T5 : AC AC DR, SC 0
T3
Execute
input-output
instruction
SC
0
ADD to AC
D1T4 : DR M [ AR ]
0 = (direct)
I
T3
Execute
register-reference
instruction
SC
0
D1T5 : AC AC + DR, E Cout , SC 0
T3
AR
M[AR]
T3
Nothing
Execute
memory-reference
instruction
SC
0
LDA : memory read

D2T4 : DR M [ AR ]
D2T5 : AC DR, SC 0

5-12
STA : memory write
Fig. 5-10 Example of BSA
D3T4 : M [ AR ] AC , SC 0
PC = 20
PC = 21
BUN : branch unconditionally
0
BSA 135
next instruction
D4T4 : PC AR, SC 0
BSA : branch and save return address
135 21(return address)

PC = 136
Subroutine
D5T4 : M [ AR ] PC , AR AR + 1
D5T5 : PC AR, SC 0
z
z
BUN 135
Return Address : save return address ( 135

21 )
D5T4 : M [135] 21( PC ), 136( AR ) 135 + 1
Subroutine Call : Fig. 5-10
ISZ : increment and skip if zero
D5T5 : 136( PC ) 136( AR ), SC 0
D6T4 : DR M [ AR ]
D6T5 : DR DR + 1
D6T6 : M [ AR ] DR, if ( DR = 0) then ( PC PC + 1), SC 0
Control Flowchart : Fig. 5-11

z Flowchart for the 7 memory reference instruction
The longest instruction : ISZ(T6)
3 bit Sequence Counter ( 4 )

5-13
5-7 Input-Output and Interrupt

Input-Output Configuration : Fig. 5-12
z Input Register(INPR), Output Register(OUTR)
These two registers communicate with a communication interface serially and with the
AC in parallel
Each quantity of information has eight bits of an alphanumeric code
z
1 : Ready
0 : Not ready
Input Flag(FGI), Output Flag(FGO)

FGI : set when INPR is ready( ), clear when INPR is empty
FGO : set when operation is completed( ), clear when output device is
in the process of printing
Input-Output Instruction : Tab. 5-5

Address
z p = D7IT3 :

z IR(i) = Bi
IR(6 -11)
> B6 - B11 : 6 I/O Instruction
Program Interrupt
z I/O Transfer Modes
1) Programmed I/O, 2) Interrupt-initiated I/O, 3) DMA, 4) IOP
2) Interrupt-initiated I/O (FGI FGO 1 Int. )
Maskable Interrupt ( ION IOF Int. mask )

5-14
Interrupt Cycle : Fig. 5-13
Instruction cycle
During the execute phase, IEN is checked by the control
Interrupt cycle
=1
Fetch and decode

instruction
IEN = 0 : the programmer does not want to use the interrupt,

so control continues with the next instruction cycle
IEN = 1 : the control circuit checks the flag bit, If either flag
set to 1, R F/F is set to 1
Execute
instruction
Store return address

in location 0
M[0]
PC
=0
IEN
=1
=1
Branch to location 1
PC
1
FGI
=0
At the end of the execute phase, control checks the value of R
=0
=1
R = 0 : instruction cycle
R = 1 : Interupt cycle
IEN
R
FGO
0
0
=0
Demonstration of the interrupt cycle : Fig. 5-14

The memory location at address 0 as the place for storing the return address Fig. 5-13
Interrupt Branch to memory location 1
Interrupt cycle IEN=0 ( ISR Interrupt ISR
ION )
0
PC = 1
The condition for R = 1

T0'T1'T2' ( IEN )( FGI + FGO ) : R 1
Modified Fetch Phase

Modified Fetch and Decode Phase
Save Return
Address(PC) at 0
Jump to 1(PC=1)
256(return address)
0
BUN 1120
Main Program
Interrupt
Here!
255
256
Fig. 5-14
RT0 : AR 0, TR PC
RT1 : M [ AR ] TR, PC 0
RT2 : PC PC + 1, IEN 0, R 0, SC 0
Interrupt
1120
Service Routine
1
BUN

5-15
5-8 Complete Computer Description

The final flowchart of the instruction cycle : Fig. 5-15
The control function and microoperation : Tab. 5-6
5-9 Design of Basic Computer
The basic computer consists of the following hardware components

z 1. A memory unit with 4096 words of 16bits
z 2. Nine registers : AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC(Fig. 2-11)
z 3. Seven F/Fs : I, S, E, R, IEN, FGI, and FGO
z 4. Two decoder in control unit : 3 x 8 operation decoder, 4 x 16 timing
Section
decoder(Fig. 5-6)

z 5. A 16-bit common bus(Fig. 5-4)
z 6. Control Logic Gates : Fig. 5-6 Box Control Output
z 7. Adder and Logic circuit connected to the AC input
Control Logic Gates
z 1. Signals to control the inputs of the nine registers
z 2. Signals to control the read and write inputs of memory
z 3. Signals to set, clear, or complement the F/Fs
z 4. Signals for S2 S1 S0 to select a register for the bus
z 5. Signals to control the AC adder and logic circuit

5-16
Register Control : AR
z Control inputs of AR : LD, INR, CLR
AR ? z Find all the statements that change the AR
in Tab. 5-6
R ' T0 : AR PC
z Control functions
R ' T2 : AR IR(0 11)
LD ( AR ) = R ' T0 + R ' T2 + D7 ' IT3 D7 ' IT3 : AR M [ AR ]
CLR ( AR ) = RT0
RT0 : AR 0
INR( AR ) = D5T4
From Bus
12
12
AR
To Bus
Clock
D'7
I
T3
LD
INR
CLR
T2
R
T0
D5
T4
D5T4 : AR AR + 1
Memory Control : READ

M [ AR ] ?
z Control inputs of Memory : READ, WRITE
z Find all the statements that specify a read operation in Tab. 5-6
z Control function
READ = R' T1 + D7 ' IT3 + ( D0 + D1 + D2 + D3 )T4
F/F Control : IEN IEN ?

z Control functions
? M [ AR ]
J
0
1
KQ(t+1)
1
0
0
1
pB7 : IEN 1
pB6 : IEN 0
RT2 : IEN 0

5-17
Bus Control
z Encoder for Bus Selection : Tab. 5-7
S0 = x1 + x3 + x5 + x7
S1 = x2 + x3 + x6 + x7
S2 = x4 + x5 + x5 + x7
z x1 = 1 : Bus AR = Find ? AR
D T : PC AR
4 4
D5T5 : PC AR
Control Function : x1 = D4T4 + D5T5
z
x1
x2
x3
x4
x5
x6
x7
S0
Encoder
S1
S2
Multiplexer
Bus Select
Input
x2 = 1 : Bus PC = Find ? PC
x7 = 1 : Bus Memory = Find ? M [ AR ]

Same as Memory Read
Control Function : x7 = R ' T1 + D7 ' IT3 + ( D0 + D1 + D2 + D3 )T4

5-18
5-10 Design of Accumulator Logic

Circuits associated with AC : Fig. 5-19
Fig. 5-21
Fig. 2-11
16
16
From DR
8
From INPR
Adder and
logic
circuit
Accumulator
register
(AC)
16
LD
Fig. 5-20
INR
16
To Bus
CLR Clock
Control
gates

5-19
Control of AC : Fig. 5-20

z Find the statement that change the AC : AC ?
From adder
and logic
16
16
AC
To Bus
Clock
D0
AND
LD
INR
CLR
T5
D0T5 : AC AC DR
D1
ADD
D2
DR
D1T5 : AC AC + DR
D2T5 : AC DR
pB11 : AC (0 7) INPR
T5
LD
rB9 : AC AC
INPR
B11
r
rB7 : AC shr AC , AC (15) E
COM
B9
rB6 : AC shr AC , AC (0) E
SHR
rB11 : AC 0
CLR
rB5 : AC AC + 1
INR
B7
SHL
B6
INC
B5
CLR
B11

5-20
Adder and Logic Circuit : Fig. 5-21 ( 16 bit = 16 )

DR(i) AC(i)
(Output of OR gate in Fig. 5-20)

AND
Ci
ADD
FA
Ci+1
From
INPR
bit(i)
J
0
1
LD
Ii (Fig.2-11)
DR
KQ(t+1)
1
0
0
1
AC(i)
INPR
Clock
COM
* Fig. 2-11
Increment, Clear,
Count
SHR
AC(i+1)
SHL
AC(i-1)

5-21
Mano Machine
Integration !
Fig. 5-4 : Common Bus (p.130)

Fig. 2-11 : Register (p. 59)
Fig. 5-6 : Control Unit (p. 137)
Fig. 5-16, 17,18 : Control Logic Gate (p.161- 163)
Fig. 5-4 Component Control Input
Register, Memory, F/Fs, Bus Selection
Fig. 5-20 : AC control (p.165)

Fig. 5-21 : Adder and Logic (p.166)
Due Date : 1

5-22
T0
T15
15 14
10
416
decoder
4-bit
sequence
counter
(SC)
Increment(INR)
Clear(CLR)
Clock
D3T4 : SC 0


Ch05 - Basic Computer Organization and Design

Enviado por

Dados do documento

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

Ch05 - Basic Computer Organization and Design

Enviado por

Direitos autorais:

Formatos disponíveis

Chap. 5 Basic Computer Org.

5-1 Instruction Codes

the sequence (control)

A group of bits that instruct the computer to perform a specific operation

Chap. 5 Basic Computer Organization and Design

Korea Univ. of Tech. & Edu.

Stored Program Organization : Fig. 5-1

Instruction code format with two parts : Op. Code + Address

Op. Code : specify 16 possible operations (4 bit)

Memory : 12 bit = 4096 word(Instruction and Data are stored)

Direct address operand : Fig. 5-2(b)

Indirect address operand : Fig. 5-2(c)

Computer System Architecture

Chap. 5 Basic Computer Organization and Design

Korea Univ. of Tech. & Edu.

5-2 Computer Registers

Computer System Architecture

Chap. 5 Basic Computer Organization and Design

Korea Univ. of Tech. & Edu.

Input Register(INPR) : receive an 8-bit character from an input device

Common Bus System

Memory (7), AR (1), PC (2), DR (3), AC (4), IR (5), TR (6)

Control Input : LD, INC, CLR, Write, Read

Computer System Architecture

AC DR memory read (p. 146, LDA )

Korea Univ. of Tech. & Edu.

1) Register Microoperation : clear AC, shfift

2) Data Register : add DR to AC, and DR to

Note) Two microoperations can be executed

DR AC : s2 s1s0 = 100(4), DR (load )

16-bit common bus

Fig. 5-4 Basic computer registers connected to a common bus

Chap. 5 Basic Computer Organization and Design

Korea Univ. of Tech. & Edu.

5-3 Computer Instruction

Computer System Architecture

Chap. 5 Basic Computer Organization and Design

Korea Univ. of Tech. & Edu.

If the computer includes a sufficient number of

5-4 Timing and Control

Two major types of control organization

Computer System Architecture

Chap. 5 Basic Computer Organization and Design

Korea Univ. of Tech. & Edu.

Microprogrammed Control : Chap. 7

Timing Signal = 4 X 16 Decoder +

Memory R/W cycle time > Clock

Computer System Architecture

Exam) Control timing : Fig. 5-7

Control Unit = Control Logic Gate +

Control Unit : Fig. 5-6

Chap. 5 Basic Computer Organization and Design

Korea Univ. of Tech. & Edu.

Exam) Register transfer statement : T0 : AR PC

1) During T0 active, the content of PC is placed onto the bus ( S2 S1S0 )

5-5 Instruction Cycle

Instruction Fetch : T0, T1(Fig. 5-8)

Chap. 5 Basic Computer Organization and Design

Korea Univ. of Tech. & Edu.

1) Enable the read input memory

IR(12-14) Fig. 5-6 D0 - D7

Instruction Execution : T3, T4, T5, T6

Memory Ref. T4, T5, T6 :

Flowchart for instruction cycle(Initial