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2. Origins of SDH
As can be seen from the previous chapter PDH is a workable but flawed system.
At its conception it used the best available technology and was a giant leap forward
in transmission, but with the advent of silicon chips and integrated microprocessors,
customer demand soon provided the need to introduce a new and better system.
This new system needed to solve the existing limitations of PDH, but also provide
for applications of the future.
The first of the working systems to be introduced was the SYNTRAN (Synchronous
Transmission) system from Bellcore. This did not live up to expectations and was
soon replaced with SONET (Synchronous Optical Network).
Initially SONET could only carry the ANSI (American National Standards Institute) bit
rates i.e. 1.5, 6, 45 Mbit/s.
Since the aim of the project was to provide easier international interconnection,
SONET was modified to carry the European standard bit rates of 2, 8, 34 & 140
Mbit/s.
2.1.
SDH permits the mixing of existing European (ETSI) and North American (ANSI)
PDH bit rates.
SDH provides for much simpler extraction/insertion, of a lower order bit rate from
a higher order aggregate stream, without the need to de-multiplex in stages.
SDH provides cross-connection of any low order stream to any other low order
stream without the need to de-multiplex in stages.
SDH provides for a standard optical interface thus allowing the inter-working of
different manufacturers equipment's.
SDH provides for future higher order rates by a simple BYTE interleaving process.
SDH standards have been prepared for future applications such as Asynchronous
Transfer Mode (ATM), High Definition Television (HDTV) and Metropolitan Area
Networks (MAN).
Increase
in
system
equipment/jumpering.
reliability
due
to
reduction
of
necessary
Each side of the ring (known as A and B, or sometimes, East and West), consists of
an individual transmit and receive fibre. These fibres will take diverse physical paths
to the distant end equipment to minimise the risk of both routes failing at the same
time.
The SDH equipment can detect when there is a problem and will automatically
switch to the alternate route.
TX
RX
TX
RX
RX
TX
RX
TX
Customer A
"Ring Normal"
Customer B
Customer A
Customer B
3. SDH Principles
3.1.
Overview
Tributary units are then multiplexed together in stages (Tributary User Group 2
(TUG-2) - Tributary User Group 3 (TUG-3) - Virtual Container 4 (VC-4)), to form
an Administrative Unit 4 (AU-4). Additional stuffing, pointers and overheads are
added during this procedure.
This AU-4 in effect contains 63 x 2 Mbit/s channels and all the control information
that is required.
3.2.
STM-1:
STM-4:
155,520 kbit/s.
622,080 kbit/s.
(155 Mbit/s)
(620 Mbit/s)
(2.5 Gbit/s)
(10 Gbit/s)
SDH allows for various PDH input rates to be mapped into containers as shown
below:
Container
Container
Container
Container
Container
C11:
C12:
C2:
C3:
C4:
1544 kbit/s
2048 kbit/s
6312 kbit/s
49,536 kbit/s
139,264 kbit/s
(1.5 Mbit/s)
(2 Mbit/s)
(6 Mbit/s)
(45 & 34 Mbit/s)
(140 Mbit/s)
As can be seen from this chart, the only PDH rate that is not directly supported by
SDH is 8 Mbit/s. This is not a popular bit rate in Europe and can be achieved by
inverse multiplexing techniques if required although only on a manufacturer specific
basis.
3.3.
The diagram shows the complete SDH multiplexing structure. PDH signals enter on
the right into the relevant container and progress across to the left through the
various processes.
The route via VC-3 and AU-3 (shown with dotted lines) are for SONET applications
(does not include 140 Mbit/s payloads), and are not applicable in Europe.
S T M -n
xN
AUG
x1
A U -4
V C -4
C -4
1 3 9 2 6 4 k b it/s
C -3
4 4 7 3 6 k b it/s
3 4 3 6 8 k b it/s
x3
x3
x1
T U G -3
T U -3
V C -3
x7
A U -3
V C -3
x7
P o in te r
P ro c e s s in g
M u lt ip le x in g
A lig n in g
M a p p in g
T U G -2
x1
T U -2
V C -2
C -2
6 3 1 2 k b it /s
T U -1 2
V C -1 2
C -1 2
2 0 4 8 k b it /s
T U -1 1
V C -1 1
C -1 1
1 5 4 4 k b it /s
x3
x4
3.4.
The above diagram shows the European structure for a 2 Mbit/s circuit. The relative
bit rate and process is shown for each stage
Adds
SO H
(7 2 b y te s )
S T M -n
155520000
T ra n s p a re n t
xN
AUG
x1
150912000
P o in te r
P r o c e s s in g
Adds AU
P o in t e r
(9 b y te s )
M u ltip le x e s
3 T U G 3 's
to fo rm a
V C - 4 w ith 2
c o lu m n s o f
f ix e d s tu f f in g
and a
V C -4 p a th
o v e rh e a d
(2 7 b y te s )
A U -4
V C -4
150912000
150336000
M u ltip le x e s
7 T U G 2 's t o
fo rm a
T U G - 3 w it h
2 c o lu m n s o f
fix e d s tu f fin g
(1 8 b y te s )
x3
M a p p in g
T U G -3
49536000
x7
M u lt ip le x e s
3 T U - 1 2 's
to fo rm a
T U G -2
x3
T U G -2
6912000
Adds
TU
P o in t e r
(1 b y te )
A d d s P a th
O v e rh e a d ,
J u s t if ic a t io n a n d
fix e d S tu f fin g
(3 b y te s )
T U -1 2
V C -1 2
C -1 2
2304000
2240000
2048000
A lig n in g
B it s
M u lt ip le x in g
3.5.
STM -1
Stream
SOH
VC-4
AU Pointers
SOH
AU Pointers
VC-4
VC-4 + AU Pointers
= AUG / AU
3 x TUG-3's + POH
= VC-4
P
O
H
TUG-3 #1
TUG-3 #2
TUG-3 #3
7 x TUG-2's = TUG-3
A
3 x TU-12's = TUG-2
TU
Pointer
T
U
1
2
V5 Path
overhead
V
C
1
2
Stuffing and
Justification
bits
C
1
2
PDH
Bitstream