Nirmal Mtds

NOVEMBER 3, 2015
MTDS ASSIGNMENT-2
NIRMAL SURESH
B120029EC
S7 ECE
V Build a 64 x 8 byte Memory using the first one as a component

(structural mode with generate statements). Write the behavioral
code in another library and bind it using a configuration.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mem164 is
Port ( clk : in STD_LOGIC;
set : in STD_LOGIC;
readdat : in STD_LOGIC;
writedat : in STD_LOGIC;
radd : in integer;
wadd : in integer;
indat : in STD_LOGIC_VECTOR(3 DOWNTO 0);
outdat : out STD_LOGIC_VECTOR(3 DOWNTO 0));
end mem164;
architecture arc of mem164 is
type mem is array(0 to 15) of std_logic_vector( 3 downto 0);
signal sig : mem ;
begin
--read fn
process(clk,readdat)
begin
if(clk'event and clk ='1') then
if set ='1' then
if readdat= '1' then
outdat <= sig(conv_integer(radd));
else
outdat<= (outdat' range => 'Z');
sig( conv_integer(wadd))<= indat;
end if;
end if;
end if;
end process;
-- write fn
process(clk,writedat)
begin
if(clk'event and clk ='1') then
if set ='1' then
if writedat= '1' then
sig( conv_integer(wadd))<= indat;

end if;
end if;
end if;
end process;
end arc;
entity MEM648 is
en : in STD_LOGIC;
rddat : in STD_LOGIC;
wtdat : in STD_LOGIC;
add : in integer;
indata : in STD_LOGIC_vector( 63 downto 0);
outdata : out STD_LOGIC_vector(63 downto 0));
end MEM648;
architecture pros of MEM648 is
component mem164 is
port(
clk : in std_logic;
set : in std_logic;
readdat : in std_logic;
writedat : in std_logic;
radd: in integer;
wadd: in integer;
indat:in std_logic_vector(3 downto 0);
outdat :out std_logic_vector(3 downto 0));
end component;
for all: mem164 use entity memory.mem164(arc);
signal temp : integer := 0;
begin
temp <= add when add<16 else
(add-16) when (add<32 and add>15) else
(add-32) when (add<48 and add>31) else
(add-48) when (add<64 and add>47);
A1: if (add <16) generate
G1 : for i in 0 to 15 generate
H1: mem164 port map( clk , en,rddat , wtdat,temp ,temp ,indata((4*i+3)
downto (4*i)),outdata((4*i+3) downto (4*i)));
end generate G1;
end generate A1;
A2 : if (add<32 and add>15) generate

end generate G2;
end generate A2;
A3 : if (add<48 and add>31) generate
end generate G3;
end generate A3;
A4 : if(add<64 and add>47) generate

end generate G4;
end generate A4;
end pros;
TEST BENCH:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tbmem648 IS
END tbmem648;
ARCHITECTURE behavior OF tbmem648 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MEM648
PORT(
clk : IN std_logic;
en : IN std_logic;
rddat : IN std_logic;
wtdat : IN std_logic;
add : IN integer;
indata : IN std_logic_vector(63 downto 0);
outdata : OUT std_logic_vector(63 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal en : std_logic := '0';
signal rddat : std_logic := '0';
signal wtdat : std_logic := '0';
signal add : integer := 0;
signal indata : std_logic_vector(63 downto 0) := (others => '0');
--Outputs
signal outdata : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MEM648 PORT MAP (
clk => clk,
en => en,
rddat => rddat,
wtdat => wtdat,
add => add,
indata => indata,
outdata => outdata
);
-- Clock process definition
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
en<='1';
rddat<='0';
wtdat<='0';
add<=0;
indata<=(indata'range =>'0');
wait for 20 ns;
wtdat<='1';
add<=6;
indata<= indata + "1011001010111100";
wait for 20 ns;
add<=25;
indata<= indata + "0011010111000011";
wait for 20 ns;
add<=56;
indata<= indata + "1100110011001100";
wait for 20 ns;
add<=63;
indata<= indata + "0101010110101010";
wait for 20 ns;
indata<=(others => '0');
wtdat<='0';
rddat<='1';
add<=6;
wait for 20 ns;
add<=25;
wait for 20 ns;
add<=56;
wait for 20 ns;
add<= 63;
wait for 20 ns;
wtdat<='0';
rddat<='0';
add<=0;
wait;
end process;
END;
VI Use a FF as a component, the design of which is placed in

another library. Bind it using a configuration, and design a 16 bit
counter.
library IEEE;
entity cntr is
Port ( t : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC);
end cntr;
architecture Beh of cntr is
signal temp : std_logic;
begin
process(clk, rst,t)
begin
if rst = '1' then
temp <='1';
elsif ( clk'event and clk = '1') then
temp<= temp xor t;
end if;
end process;
q<= temp;
end Beh;
entity BITCTR16 is
rst : in STD_LOGIC;
o : out STD_LOGIC_VECTOR( 0 to 15));
end BITCTR16;
architecture Behavioral of BITCTR16 is
signal temp : std_logic_vector(16 downto 0) :="00000000000000000" ;
component cntr
port ( t : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : out std_logic );
end component;
for all : cntr use entity counter.cntr(Beh);
begin
temp(0) <= clk;
G1 : for k in 0 to 15 generate
count1 : cntr port map ('1', temp(k) , rst,temp(k+1));
o <= not temp(16 downto 1);
end generate;
end Behavioral;
TEST BENCH:
LIBRARY ieee;
ENTITY tbcntr IS
END tbcntr;
ARCHITECTURE behavior OF tbcntr IS
COMPONENT BITCTR16
PORT(
clk : IN std_logic;
rst : IN std_logic;
o : OUT std_logic_vector(0 to 15)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
--Outputs
signal o : std_logic_vector(0 to 15);
BEGIN

uut: BITCTR16 PORT MAP (
clk => clk,
rst => rst,
o => o
);
-- Clock process definitions
begin
clk <= '0';
clk <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
rst<='0';
wait for 150 ns;
rst<='1';
wait for 150 ns;
rst <='0';
wait;
end process;
END;
VII Write a number of functions and store in a package .Use these functions from a
different design library (find applications to use the functions)
The functions are
a) Conversion from bit vector to integer.
b) Counting the number of zeros (and number of ones) in a 16 bit word.
c) Finding the biggest of 10 integers
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package fns is
TYPE arr IS ARRAY(9 DOWNTO 0) OF INTEGER;
function bittodec ( bit1 : bit_vector ) return integer;
--function dectobit ( dec : in integer) return bit_vector;
function noofzs(bit2 : bit_vector) return integer;
function noofos(bit3 : bit_vector) return integer;
function larger( arr1: arr) return integer;
end fns;
package body fns is
function bittodec ( bit1 : bit_vector) return integer is
variable res : integer:=0;
begin
for i in bit1'range loop
if bit1(i) = '1' then
res := res +(2**i);
end if;
end loop;
return res;
end bittodec;
function dectobit ( signal dec : integer) return bit_vector is
variable temp ,cnt,res1,remn : integer := 0;
temp:= dec ;
cnt:=1;
remn:= 0;
while dec>0 loop
remn := dec mod 2;
res1:= res1 + (cnt*remn);
cnt:=cnt*10;
dec:=dec/2;
end loop;
return res1;
end dectobit;
function noofzs(bit2 : bit_vector) return integer is
variable res2:integer;
begin
for i in bit2' range loop
res2:=res2+1;
end if;
end loop;
return res2;
end noofzs;
function noofos(bit3: bit_vector) return integer is
variable res3:integer;
begin
for i in bit3' range loop
res3:=res3+1;
end if;
end loop;
return res3;
end noofos;
function larger(arr1: arr) return integer is
variable res4: integer := 0;
begin
res4:=arr1(0);
for i in arr1'range loop
if arr1(i) > res4 then
res4:=arr1(i);
end if;
end loop;
return res4;
end larger;
end fns;
library IEEE;
library packagefn;
use packagefn.fns.all;
use IEEE.STD_LOGIC_unsigned.all;
entity pack is
Port ( a : in bit_vector(15 downto 0):="1111111111111110";
b : in bit_vector(7 downto 0):="00000011";
c : in integer:=10;
d : in arr:=(1,3,6,8,9,8,6,4,2,0));
end pack;
architecture Behavioral of pack is
signal bint,large,n,m : integer;
begin
bint <= bittodec(b);
n<=noofzs(a);
m<=noofos(a);
large<=larger(d);
end Behavioral;
VIII Design the following as state machines and write VHDL code.
a) Up/down counter counting from 0 to 5.
library IEEE;
entity stateupdwn is
rst : in STD_LOGIC;
inp : in STD_LOGIC;
o : out STD_LOGIC_VECTOR(2 DOWNTO 0));
end stateupdwn;
architecture Behavioral of stateupdwn is
TYPE state is (s0, s1, s2 ,s3, s4, s5);
signal pstat : state := s0;
begin
process(clk)
begin
if rst ='1' then
pstat <= s0;
o <="000";
elsif clk'event and clk ='1' then
case pstat is
when s0 => o <= "000";
if inp = '1' then
pstat <= s1;
else
pstat <= s5;
end if;
when s1 => o <= "001" ;
if inp = '1' then
pstat <= s2;
else
pstat <= s0;
end if;
when s2 => o <= "010";

if inp = '1' then
pstat <= s3;
else
pstat <= s1;
end if;
when s3 => o <= "011";
if inp = '1' then
pstat <= s4;
else
pstat <= s2;
end if;
when s4 => o <= "100";

if inp = '1' then
pstat <= s5;
else
pstat <= s3;
end if;
when s5 => o <= "101";
if inp = '1' then
pstat <= s0;
else
pstat <= s4;
end if;
end case;
end if;
end process;
end Behavioral;
TEST BENCH:
LIBRARY ieee;
ENTITY tbstate IS
END tbstate;
ARCHITECTURE behavior OF tbstate IS
COMPONENT stateupdwn
PORT(
clk : IN std_logic;
rst : IN std_logic;
inp : IN std_logic;
o : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal inp : std_logic := '0';
--Outputs
signal o : std_logic_vector(2 downto 0);
BEGIN
uut: stateupdwn PORT MAP (
clk => clk,
rst => rst,

inp => inp,
o => o
);
begin
clk <= '0';
clk <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
rst<= '1';
wait for 10 ns;
rst<= '0';
wait for 50 ns;
inp<='1';
wait for 50 ns;
inp<='1';
wait for 50 ns;
inp<='1';
wait for 50 ns;
inp<='0';
wait for 50 ns;
inp<='0';
wait for 50 ns;
inp<='1';
wait;
end process;
END;
b) Serial Adder 4 bits

library IEEE;
entity serl is
Port ( a : in STD_LOGIC_VECTOR(3 DOWNTO 0);
b : in STD_LOGIC_VECTOR(3 DOWNTO 0);
s : out STD_LOGIC_VECTOR(3 DOWNTO 0);
cout : out STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ready : in STD_LOGIC);
end serl;
architecture archi of serl is
type state is ( s0,s1,s2,s3);
signal pst , nst : state := s0;
signal temp : std_logic_vector( 3 downto 0):="0000";
begin
c1: process( clk)
begin
if rst ='1' then
pst<= s0;
elsif (clk'event and clk = '1') then
pst <= nst;
end if;
end process;
process(pst,nst)
begin
--wait on pst,nst;
case pst is
when s0 => --if ((ready = '1')and(clk'event and clk ='1'))then
-- wait until (clk'event and clk ='1');
s(0) <= a(0) xor b(0);
temp(0) <= a(0)and b(0);
nst<= s1;
--end if;
when s1 => s(1) <= a(1) xor b(1) xor temp(0);
temp(1) <= (a(1)and b(1)) xor( a(1) xor b(1) xor
temp(0)) ;
nst<= s2;
temp(2) <= (a(2)and b(2)) or( a(2) xor b(2) xor
temp(1)) ;
nst<= s3;
temp(3) <= (a(3)and b(3)) or( a(3) xor b(3) xor
temp(2)) ;
nst<= s0;
end case;
end process;
cout<= temp(3);
end archi;
TEST BENCH:
LIBRARY ieee;
ENTITY tbserial IS
END tbserial;
ARCHITECTURE behavior OF tbserial IS
COMPONENT serl
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);

s : OUT std_logic_vector(3 downto 0);
cout : OUT std_logic;
rst : IN std_logic;
clk : IN std_logic;
ready : IN std_logic);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
signal ready : std_logic := '0';
--Outputs
signal s : std_logic_vector(3 downto 0):= (others => '0');
signal cout : std_logic:='0';
BEGIN
uut: serl PORT MAP (
a => a,
b => b,
s => s,
cout => cout,
rst => rst,
clk => clk,
ready => ready
);
begin
clk <= '0';
clk <= '1';
end process;
-- Stimulus proces
stim_proc: process
begin
rst<='1';
wait for 50 ns;
rst<= '0';
ready<='1';
a<="0001"; b<="0101";
wait for 50ns;
--ready<='0';
wait;
end process;
END
IX A sequential circuit has an input X and an output Z. The output

is the same as the input was two clock periods previously. For
example,
X=0 1 0 1 1 0 1 0 1 1 0 1 0 0 0 1
Z=0 0 0 1 0 1 1 0 1 0 1 1 0 1 0 0
The first two values of Z are 0. Find a Mealy state graph and table
for the circuit. Write a VHDL code using two processes.
library IEEE;
entity seq is
rst : in STD_LOGIC;
x : in STD_LOGIC;
z : out STD_LOGIC );
end seq;
architecture pro of seq is
type state is (s0,s1,s2,s3);
signal pst,nst : state :=s0;

begin
process(clk, rst)
begin
-- if rst ='1' then
--z<='0';
--pst<=s0;
if (clk'event and clk = '1') then
pst<=nst;
end if;
end process;
process(pst,x)
begin
case pst is
when s0 => if x='1' then
nst<= s1;
else
nst<= s0;
end if;
z<='0';
nst<= s2;
else
nst<=s3;
end if;
z<='0';
nst<= s1;
else
nst<=s0;
end if;
z<='1';
nst<= s2;
else
nst<=s3;
end if;
z<='1';
end case;
end process;
end pro;
TEST BENCH:
LIBRARY ieee;
ENTITY tbseq IS
END tbseq;
ARCHITECTURE behavior OF tbseq IS
COMPONENT seq
PORT(
clk : IN std_logic;
rst : IN std_logic;
x : IN std_logic;
z : OUT std_logic
);
END COMPONENT;
--Inputs
signal x : std_logic := '0';
--Outputs
signal z : std_logic;
constant clk_period : time := 10 ps;
BEGIN
uut: seq PORT MAP (
clk => clk,
rst => rst,
x => x,
z => z
);
begin
clk <= '0';
clk <= '1';
end process;
-- Stimulus process
stim_proc: process
begin
z<='0';
wait for 2*clk_period;
wait for 0.005 ns;
x<='0';
wait for clk_period;
x<='1';
x<='0';
x<='1';
x<='1';
x<='0';
x<='1';
x<='0';
x<='1';
x<='1';
x<='0';
x<='1';
x<='0';
x<='0';
x<='0';
x<='1';
wait;
end process;
END;

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NOVEMBER 3, 2015

V Build a 64 x 8 byte Memory using the first one as a component

sig( conv_integer(wadd))<= indat;

H2: mem164 port map( clk , en,rddat , wtdat,temp ,temp ,indata((4*i+3)

A4 : if(add<64 and add>47) generate

VI Use a FF as a component, the design of which is placed in

-- Instantiate the Unit Under Test (UUT)

when s2 => o <= "010";

when s4 => o <= "100";

rst => rst,

b) Serial Adder 4 bits

b : IN std_logic_vector(3 downto 0);

IX A sequential circuit has an input X and an output Z. The output

signal pst,nst : state :=s0;

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