International Journal of Advanced Engineering Research and Technology (IJAERT) 153

Volume 3 Issue 4, April 2015, ISSN No.: 2348 8190

Design of 4x4 Parity Preserving Reversible Vedic Multiplier

Akansha Sahu*, Anil Kumar Sahu**
*(Department of Electronics & Telecommunication Engineering, CSVTU, Bhilai)
** (Department of Electronics & Telecommunication Engineering, CSVTU, Bhilai)

ABSTRACT
Multiplier play an important role and finds a variety of
application in most of signal processing operations and
processors .In VLSI, Power, Area and Delay are the
three important constraints .
The speed of the
multiplier is depend on the speed of the adder .Here the
Carry Look ahead adder is used for the partial product
addition .This paper presented a designing of novel 4x4
Parity Preserving Reversible Vedic Multiplier . The
most significant aspect of proposed multiplier
architecture is based on Urdhva Tiryakbhayam formula
of an ancient Indian Vedic Mathematics which produce
all partial product and theirs addition in one step and
Parity Preserving reversible gate which performs a
reversible computation which ensures zero internal
power dissipation in a manner that they also detect a
fault in the circuit. The design of architecture is done in
verilog language and simulated using Xilinx9.2i.

is obtained. So the performance of the multiplier depends

on the number of steps involve for the partial product and
the speed of the adder. Vedic mathematic has 16 formula,
for the multiplication Urdhav Tiryakbhayam formula is
used, it means Vertical and Cross-wise multiplication
which enhance the speed of multiplication operation. The
proposed parity preserving reversible vedic multiplier
based on the Urdhav Tiryakbhayam aphorisms and
constructed by using Parity Preserving gate which offer the
best results in terms of delay and also the multiplier exhibit
fault tolerant property.
The paper is organized as follows: Section 2 describes
Importance of Reversible logic, Urdhav Tiryakbhayam
method Section 3 shows literature review Section 4
Proposed 4x4 Parity preserving reversible vedic multiplier.
Section 5 describes the Result and Comparison and Section
6 shows the Conclusion.

II REVERSIBLE LOGIC

Keywords - Reversible Gate, Fault Tolerant Property,

Vedic Multiplier, Delay, Carry Look ahead Adder.
I.
INTRODUCTION
Multiplier is the key component in the computing
systems such as Digital signal processing,
Microprocessor, FIR filter etc. Hence the performance
of these application can be improved by optimizing the
multiplier in the terms of Power, Speed, Area and Fault
tolerance property. .Reversible logic circuit or
information lossless circuit has zero internal power
dissipation and also there are few families of reversible
gate that have inherent fault tolerance property. As
reversible circuit have application in variety of
emerging technology such as quantum computing,
nanotechnology etc. According to the Moores law, by
the 2020 the basic memory components of a computer
will be the size of the individual atoms. At such scales
current theory of computer will be fail and an quantum
computing reinvented the theory of computer science,
Quantum computer can complete task in the
breathtakingly time with no internal power dissipation.
Multiplication process includes generation of partial
product, addition of partial product and finally product

A. Importance of Reversible Logic

According to the Moores law the number of transistor will
be doubled in every 18 months. In VLSI there will be trade
of between the Power and Area , Speed.
Reversible logic has an ability to reduce power dissipation
which is the main requirement for low power devices. In
1961 according to the Landauers research proved that the
during irreversible computation 1 bit of information lost
results in ktln2 Joules of energy dissipation .[1] While In
1973 ,Charles Bennett showed that the energy loss could be
avoided if the computation is carried out with reversible
logic gates.[2] Thus the circuit build from reversible gate (
or called as Information lossless circuit) has zero power
dissipation. The basic concept of Information lossless
circuit is that not only the output vector is recovered from
the input vector, but the input vector will also be recovered
from the output vector.
An reversible logic circuit must be designed using the
minimum number of the reversible logic gates. The
reversible gate has the following characteristics they are
[5]1. It exhibit equal number of inputs and outputs.

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International Journal of Advanced Engineering Research and Technology (IJAERT) 154

Volume 3 Issue 4, April 2015, ISSN No.: 2348 8190

2. The output, which is not used as gate input to the

other gates in the circuit, is called garbage output.
3. The input which is used as control input to the gates
is called garbage input.
4. Each Gate ,fan-out value must be equal to one
There are different types of reversible gates are
available But few of them are parity preserving gates
from reversible logic families which offers fault
tolerance property because this gates exhibits the same
parity at the input side and output side .The Parity
Preserving gate must satisfies these relation
ABC=PQR. Parity checking method is
employed to detect error in VLSI testing. There are
wide class of parity preserving reversible gate are
available. Some are given below
1. Double Feynman gate(F2G)
The double Feynman gate is a 3*3 gate are shown in
the figure1. The input vector is I(A,B,C) and output
vector is O( P,Q,R). The input parity is same as the
output parity. Quantum Cost of F2G is equal to 2.
A
B

Double
Feynman
Gate

P=A
Q=A
B

3. New Fault Tolerant Gate (NFT)

The NFT gate is a 3*3 gate are shown in the figure3. The
input vector is I(A,B,C,D) and output vector is O(
P,Q,R,S). The input parity is same as the output
parity.Quantum Cost of NFT is equal to 5. It can perform
NOT, OR, XOR, NAND, AND, EX-OR function.

A
B

P=AB
NFT
Gate

Q=BCAC
R=BCAC

Figure 3- NFT Gate

B. Urdhva Tiryakbhayam Multiplication Sutra

Urdhva Tiryakbhayam(UT) sutra is the multiplication
formula from the ancient Vedic mathematic which suits for
the multiplication of decimal number, hex as well as for the
binary number, This features of UT algorithm compatible
with the digital systems. The UT provides the fast
computation because the partial product and their sums are
calculated parallel. Urdhva Tiryakbhayam sutra are known
as Vertically and Cross-wise Multiplication The Vedic
multiplication procedure in shown in the figure4.

R=AC
Figure 1- Feynman Gate

2. Islam Gate(IG)
The Islam gate is a 4*4 gate are shown in the figure 2.
The input vector is I(A,B,C,D) and output vector is O(
P,Q,R,S). The input parity is same as the output parity
and
.Quantum Cost of F2G is equal to 7. It can
perform AND,EX-OR function.

Figure 4- Vertically and Crosswise Multiplication

III. LITERATURE REVIEW

A number of research papers of various journals and
conferences were studied and survey of existing literatures
in the proposed area is reported below:Panchal et al.[1] proposed an 4x4 reversible multiplier
circuit which is implemented using Peres and Toffoli
reversible gate and compared with the existing designs ,
The proposed reversible multiplier is better in terms of
hardware complexity, number of gates, garbage output,
constant inputs and total quantum cost.
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International Journal of Advanced Engineering Research and Technology (IJAERT) 155

Volume 3 Issue 4, April 2015, ISSN No.: 2348 8190

Morankar et al. presented an reversible multiplier using

Peres gate and full adder. The proposed reversible
multiplier is better when compared with conventional
multiplier in terms of area, power and delay .
Furthermore it has minimum number of garbage
outputs and garbage inputs as compared to the other
reversible multiplier. A new efficient multiplier is
implemented, simulated and synthesized on Xilinx
13.1. [2]
Saligram et al. proposed a high speed low power
multiplier using reversible gate [3] in 2013. Here 4x4
multiplier involves Urdhav Tiryakbhayam Vedic
algorithm which makes computational speed faster. The
four 2x2 UT multiplier is used to obtain 4x4 multiplier
using Peres gate and Feynman gate. The partial product
of the multiplier is added with ripple carry adder which
is constructed using HNG gate. The proposed multiplier
design is compared with all other designs, It is find that
the quantum cost of the proposed multiplier design is
least. Quantum cost reflects that the delay in the
circuit.[3]
In [4] the multiplier based on Urdhav Tiryakbhayam
Vedic multiplication formula are employed .The two
proposed modified multipliers is design using reversible
gate is implemented using Peres gate, Feynman gate,
NFT gate, BVPPG gate and The partial product is
added with the help of ripple carry adder which is built
using HNG gate are compared in terms of various
parameter like the number of gates, constant inputs,
garbage outputs ,quantum cost and Total Reversible
Logic Implementation Cost. It is found that the TRLIC
is less .Since the proposed modified design has the
smaller delay.
Parween et al. 4x4 Vedic reversible multiplier is
proposed using Peres and Feynman gate which is
efficient in terms of constant inputs, garbage outputs,
quantum cost, area ,speed and area .In this method
ripple carry adder is used to add the partial products
which is formed using HNG gates .The design is
simulated using Verilog. And also a comparative
analysis between 4x4 Array multiplier and 4x4 Vedic
multiplier using Reversible gate is done . Finally the
author proved that Vedic Multiplier using reversible
gate is the best in terms of Area, Speed, Power and
Quantum cost.
Krishnaveni et al. designed a 4x4 multiplier using
Urdhav Tiryakbhayam sutra and also a new 4-bit adder
is proposed which used in multiplier ,reduces the delay
.This designed is simulated using VHDL and The
comparison between the Proposed Vedic Multipler and
Array Multiplier is done. It is seen that performance of

the Proposed Multiplier is higher than Array Multiplier.

Suneel et al. designed a high speed 8x8 Urdhav
Tiryakbhayam multiplier using reversible logic gates by
using four 4x4 UT Multiplier. The coding is done in VHDL
and synthesis, simulation is done using EDA tool in
XilinxISE14.3i. The comparison of 8x8 bit conventional
multiplier, Wallace multiplier and Vedic multiplier in terms
of path delay is demonstrated. The result shows that the UT
multiplier has the less path delay as compared to other
multiplier in terms of execution time.
Harish Kumar implemented and compares architectures of
multiplier they are Array and Vedic multiplier. In this paper
two Vedic formula for multiplication that is Urdhva
Tiryakbhayam and Nikhilam sutras are used. And results
are compared in terms of power, delay and area with array
multiplier. The coding is done using Verilog language and
result is simulated in Xilinx 10.1 ISE. The comparison
results show that the Urdhav Tiryakbhayam multiplier is
the best multiplier as compare to nikhilam multiplier and
array multiplier.
Vengadapathiraj.et al proposed an high speed vedic
multiplier using Carry look ahead adder and also a
pipelined Vedic multiplier using Urdhva Tiryakbhayam
sutra. The coding is done in Verilog and simulation is
performed using Xilinx 12.4 The comparison between
proposed Vedic multiplier using CLA, Non pipelined Vedic
multiplier with RCA and modified booth multiplier is done
.It is find that proposed vedic multiplier using CLA based
on pipelined design is faster.[9].
Aneesh .R and Sarin K Mohan(2014) have presented an
design with Urdhva Tiryakbhayam Vedic formula for
32x32-bit multiply accumulate unit which consume low
power, area efficient and lesser delay, also analysis of
different types of adder, which is used for adding partial
product is done ,Between them carry look-ahead adder is
the best in terms of area, delay and power. The proposed
work is coded using VHDL using Xilinx ISE 13.1.[10]
Jamal et al. proposed a new fault tolerant reversible gate
that is LMH gate, also some of the theorems on the
numbers of gates, garbage outputs and quantum cost of the
fault tolerant reversible is presented which proves the
optimality. The proposed 4x4 multiplier is compared with
the existing fault tolerant reversible multiplier. Finally the
author shows the proposed fault tolerant reversible vedic
multiplier is the best in terms of number of gates, garbage
outputs, constant input and quantum cost.[11]
Somayeh et al. proposed the fault tolerant reversible
multiplier circuit, which is built using fault tolerant gates
they are modified IG gate and Fredkin gates which has the
fault tolerant property , means able to finds the errors in the
circuit. Also the proposed fault tolerant vedic reversible

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International Journal of Advanced Engineering Research and Technology (IJAERT) 156

Volume 3 Issue 4, April 2015, ISSN No.: 2348 8190

4x4 multiplier is compared with the reversible

multiplier. It is finds that the proposed multiplier is
fault tolerant property.[12]
Haghparast et al. presented nano-metric parity
preserving4x4 reversible Vedic multiplier gate . The
Fault tolerant gates like double Feynman, NFT and IG
gates are used. [13]

Number of Slices:

17

out of

4656

0%

Number of 4 input LUTs:

30

out of 9312

0%

Number of IOs:

16

Number of bonded IOBs:

16 out of

332

6%

IV PRORPOSED METHODOLOGY
The 4x4 Parity Preserving Reversible Vedic multiplier
is designed using four 2x2 Parity Preserving Reversible
Vedic
multiplier
which
employed
Urdhva
Tiryagkbhayam formula Here Parity Preserving gates
are used to construct these multiplier they are F2G,
NFT and IG gates .While the output of the four 2x2
multiplier is added with the help of carry look ahead
adder. The block diagram of the proposed 4x4 Parity
Preserving Reversible Vedic multiplier is shown in the
figure 5.

Figure-6 Simulation result of Of Proposed 4x4 Parity

Preserving Reversible Vedic Multiplier with carry
lookahead adder (5x3=15)

Figure 5 - Block Diagram of Proposed 4x4 Parity

Preserving Reversible Vedic gate

V. RESULTS AND COMPARISION

In this paper 4x4 bit Urdhav Tiryakbhayam multiplier
using parity preserving reversible gates are designed in
Verilog and the logic synthesis and simulation was
done using EDA tool in Xilinx9.2i. The synthesis result
obtained for the Proposed Parity Preserving Reversible
Vedic multiplier and simulation results and RTL
synthesis are shown in Figures 6 and 7 respectively.
The device utilization summary of 4x4 parity
preserving reversible vedic multiplier for Xilinx,
Spartan3e family is shown below:
Device Utilization Summary: Selected Device:
3s500efg320-5

Figure 7. RTL Schematic of Proposed 4x4 Parity

Preserving Reversible Vedic multiplier
Table 1 shows the comparisons of 4x4 bit Urdhav
Tiryagbhayam multiplier using Parity Preserving
Reversible gates Vedic multiplier with Array Multiplier
and Vedic Multiplier using reversible gate with ripple carry

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International Journal of Advanced Engineering Research and Technology (IJAERT) 157

Volume 3 Issue 4, April 2015, ISSN No.: 2348 8190

adder Multiplier in terms of computational path delays

(ns) and fault tolerant property.

Proposed 4x4 Parity Preserving Reversible Vedic

Multiplier with carry look ahead adder have minimum path
delay and fault tolerant capability when compared to other
multipliers.
In future, adaptive LMS filter can be designed using
Parity Preserving reversible Vedic multiplier which
provides faster computational speed.

REFERENCES
[1]

Table 1 Comparisons of 4x4 Array Multiplier, Vedic

Multiplier using reversible gate with ripple carry adder
and Proposed parity preserving reversible vedic
multiplier using carry look ahead adder
The figure 8 shows the comparison between the the
Existing Array Multiplier, Vedic Multiplier using
Reversible gate and Proposed Parity Preserving
Reversible Vedic Multiplier in the terms of Path Delay
(ns) and Fault tolerant property.

[2]

[3]

[4]

[5]

[6]

[7]

Figure 8- Comparison between the Existing Array

Multiplier, Vedic Multiplier using Reversible gate and
Proposed Parity Preserving Reversible Vedic Multiplier

V1

[8]

CONCLUSION

This paper presented an efficient method of

multiplication based on Vedic mathematics and the
partial product addition is done by the carry look ahead
adder which offered the computational speed. The

[9]

Vijay K Panchal, Vimal H Nayak, Analysis of

Multiplier Circuit using Reversible Logic,
International Journal for Innovative Resaerch in
Science & Technology, Volume 1, Issue 6,pp-22496010,Nov 2015
Prof. Amol D. Morankar, Prof Vivek M.Sakode,
Reversible Multiplier with Peres Gate and Full
Adder, International Journal of Electronics
Communication and Computer Technology, Volume
4,Issue 4,pp-2249-7838, July 2014.
Rakshith T.R and Rakshith Saligram, Design of High
Speed Low Power Multiplier Using Reversible logic:
A Vedic Mathematical Approach , International
Conference on Circuits, Power and Computing
Technologies, 2013.
Rakshith T.R and Rakshith Saligram, Optimized
Reversible Vedic Multiplier For High Speed Low
Power Operations, IEEE Conference on Information
and Communication Technologies, 2013.
A. Shifana Parween and S. Murugeswari, A Design
of High Speed, Area Efficient, Low Power Vedic
Multiplier using Reversible Logic Gate , International
Journal of Emerging Technology and Advanced
Engineering, Volume 4,Issue 2, February 2014.
Krishnaveni D and Umarani, VLSI Implementation
of Vedic Multiplier with Reduced Delay,
International Journal of Advanced Technology &
Engineering Research, Volume 2,Issue 4, July 2012.
Sadhu Suneel and L.M.L.Narayana Reddy, Design of
a High Speed 8x8 UT Multiplier Using Reversible
Logic Gates, International Journal of Computer
Science information and Engg,Volume 3, Issue4,2014.
Ch. Harish Kumar , Implementation and Analysis of
Power, Area and Delay of Array, Urdhva,Nikhilam
Vedic Multipliers, International Journal of Scientific
and Research Publications, Volume 3, Issue 1, January
2013.
Vengadapathiraj.M,,Rajendhiran.V,Gururaj.M,Vinoth
Kannan.A and Mohamed Nizar.S, Design and FPGA
Implementation of High Speed 128x 128 bits Vedic

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International Journal of Advanced Engineering Research and Technology (IJAERT) 158

Volume 3 Issue 4, April 2015, ISSN No.: 2348 8190

Multiplier Using Carry Look-Ahead Adder,

international journal of advanced research in
electronics and communication engineering
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[10] Aneesh R and Sarin K Mohan, Design and
Analysis of High Speed,Area Optimized 32x32Bit Multiply Accumlate Unit Based on
Vedic Mathematic,International
Journal
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Engineering Research and Technology , Volume
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[11] Lafifa Jamal, Md. Mushfiqur Rahman and Hafiz
Md. Hasan Babu , An Optimal Design of a Fault
Tolerant Reversible Multiplier, IEEE,2013.
[12] Somayeh Babazadeh and Majid Haghparast,
Design of a Nanometric Fault Tolerant Reversible
Multiplier Circuit ,Journal of Basic and Applied
Scientific Research, 2012
[13] Majid Haghparast and Masoumeh Shams, A
Novel Nanometric Parity Preserving Reversible
Vedic Multiplier, Journal of Basic and Applied
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