International Journal of Research in Engineering and Applied Sciences

ENCODING SCHEME FOR POWER REDUCTION IN

NETWORK ON CHIP LINKS
1

Chetan. S. Behere and 2Somulu.Gugulothu

PG Student, Yeshwantrao Chavan College of Engineering,, Nagpur, Maharashtra, India.

Assistant Professor, Yeshwantrao Chavan College of Engineering,, Nagpur, Maharashtra, India
Email:{ 1chetanbehere@gmail.com,2 gugulothusomulu06@gmail.co }

Abstract
As the number of cores in a chip increases, the role played by the communication system becomes more and more central.
Amongst the communication resources, as technology shrinks, the power ratio between NoC links and routers increases making
the links becoming more power hungry than routers. Network on chips structure makes a fitting replacement for system on chip
designs in designs incorporating large number of processing cores. In network on chip the major source of power dissipation is
the network on chip links. If compared the power ratio between the network on chip links and router links are more power
hungry than router. The dynamic power dissipation in links is major contributor to the power consumption in network on chip.
This is due to the self switching and the second factor is cross coupling capacitance. In the proposed encoding technique the
first self switching is reduce by checking the switching transition and then the coupling between the links is checked and
ensured that the power consumption is reduced.
Key Words -Analysis, Crosstalk, Low power, Network on Chip, Self Switching, Uniform power reduction.

1.

Introduction

Network on chip is an emerging approach for the

implementation of on chip communication architecture. The
system on chip designs incorporating large no. of processing
cores and modular structure of Network on chip makes a
fitting replacement for system on chip. Network on chip is
intended to solve the shortcomings of these, by
implementing a communication network of switches, micro
routers and resources.[5] System on chips are not containing
IP cores only and traditional methods for communication
such as bus are not suitable solution for
future System on chips. The Network-on-Chip has emerged
as underlying infrastructure for communication between
Intellectual Property cores. Network on chip is solution for
communication architecture of future System on chips that
are composed of switches and IP cores where communicate
among each other through switches. Between IP cores data
move in the form of packet. As the technology shrinks the
power ratio between link and router increase making link
more power hungry than routers.[8]
A network on chip communication gives flexibility in the
topology, in support to that the flow control, advance
routing algorithms, self switching techniques guarantying
the quality of service. Network on chip is an approach to
design the communication subsystem between intellectual
property cores in a system on chip. The communication
strategy in system on chip uses dedicated buses between
communicating resources. This will not give any flexibility

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since the needs of the communication, in each case, have to

be thought of every time a design is made. Another
possibility is the use of common buses, which have the
problem that it does not scale very well, as the number of
resources grows.[1]
Different encoding techniques are proposed to reduce the
power in reference to the bus based architecture. Bus invert
method can be applied to encode the randomly distributed
patterns. While the [2],[4]and[9] deals with the reduction of
switching activity in the serial link caused due to the
serialization of parallel data. Some encoding technique
considers the contribution of cross talk. [3] Proposed the
partial bus invert coding as link level power encoding
technique. This encoding scheme is developed by taking the
both factor self switching and the cross talk into
consideration. The encoder and decoder are placed in the
network interface of the wormhole routed network. The first
stage rearranges the data stream in such way that the
transition in each link is reduced while in the second stage
the inverting of data of depends upon the contribution of the
cross couple activity in power dissipation of the link, The
proposed encoding scheme can be applied to the wormhole
routed network as the interleaving of flits are not allowed.
The rest of paper organized as follows- In section II the
overview of proposal is discussed. In the Section III
encoding technique incorporated for power reduction is
discussed. The working block of the encoder and decoder is
discussed in the Section IV. In Section V & VI the simulation
and Synthesis result of encoder and decoder is there. Section
VII is Conclusion.
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International Journal of Research in Engineering and Applied Sciences

2.

Overview of Proposal

The general scheme of proposed work is given in Fig 1. The

basic concept is to apply the encoding technique in end-toend links in resource network interface of wormhole routed
network on chip. The most suitable switching technique for
on chip communication is wormhole switching.

Consider an t bit data (t=2 , m>1).

Step-2
t bit parallel data is checked for number of transitions
before serialization.
Step-3
If > ,
B(t)=Bs(t)
Else
B(t)=B(t),
Where
is number of transitions,
refers to threshold
value. Bs(t) is obtained by interchanging odd and even bits
of input data.
Step-4
The threshold was observed to vary as follows:= n/2-1, where n=2 for m=2
= n/2, where n = 2 for m=3
=n/2+2(m-4)+1 where n=2 ,for 4,5,6 (2)
3.2 Cross coupling effect elimination

Figure 1. General Scheme of proposed approach

The pipeline nature is the basic concept for the wormhole

switching. The links of the routing path are cross by the same
sequence of flits, the encoding scheme ensure the same
switching behavior in each routing path. As shown in the Fig.
1 the encoder and decoder blocks are incorporated in the
network interface. The encoder encodes the outgoing flit in
the packet in such a way that the power dissipated is
minimized by inter router point to point links which form the
routing path.
3.

Proposed Scheme

The dynamic power in the link is given by:

= [ ( + )+
]
.
(1)
Where Cs is self capacitance, Cl is the load capacitance, Cc
is the coupling capacitance, T01 and Tc are the average no.
of transition for Cs and Cc, Fclk is clock frequency, Vdd is
supply voltage. T01 counts the 01 consecutive
transition in the bus. Tc counts the correlated switching
between the adjacent links. In the proposed technique the
two techniques are incorporated first the self switching is
reduced and then cross coupling effect is reduced. [5]
3.1 Self Switching Reduction
The equation (1) shows that the dynamic power dissipation in
the link is directly proportional to self switching activity. The
switching transition in the link increases when n bit parallel
data is serialized. To reduce the no. of transition encoding
schemes arrange the data prior to serialization to reduce the
power consumption. The scheme works in the following way:
Step-1
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Time
T-1
T
T-1
T
T-1
T
T-1
T

TABLE I
CHANGE IN TRANSITION [2]
Normal Coding
Inverted Coding
00 00 11 11 Type I 00 00 11 11 Type I
01 10 01 10
01 10 01 10
01 10
Type II
00 11
Type III
10 01
11 00
00 11
Type III
01 10
Type II
11 00
10 01
00 01 10 11 Type IV 00 01 10 11 Type IV
00 01 10 11
00 01 10 11

From the above transition table there are four types. Type I
when one link switches while other remains unchanged. Type
II when one line switches from high to low and other switches
from low to high. Type III is when both lines switches
simultaneously. Type IV when both the links remains
unchanged. Tc is the weighted sum of different type of
coupling transition contribution.
=
+
+
+
(3)
Here the Tj, j = 1, 2, 3, 4, are the average number of transition
for type j and kj are weights. According to [6] it is assumed
k1 =1, k2 =2 and k3 =k4 =0. That is, k1 is assumed as
reference for other types of transition. The effective
capacitance in Type II transition is usually twice that of a
Type I transition. In Type III transition, as both signal switch
simultaneously. Finally, in Type IV transition there is no
dynamic charge distribution over Cc. Based on this, equation
(1) can be expressed as follows:
= [ ( + )+( +2 ) ]
(4)
To eliminate the cross coupling effect link and adjacent link
are considered. Each two bit word represents status of link z
and z+1 respectively at specified time. It can be observed
that if we invert the bits entering link b+1, the type II
transition gets converted to type III and vice versa.
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International Journal of Research in Engineering and Applied Sciences

After inversion equation (3) can be written as:
=
+ , +
+
(5)
Where T2=T3, T3=T2.
Hence in (3) if T2>T3, the data bits of the particular link is
inverted. As k3=0, from (5) and (3) Tc<Tc, as T2<T2. This
scheme can be applied along with the first scheme as
inverting does not alter the effect of shuffling of bits. [2]
4.

(P/Q+1+P/2Q) control bits are converted to (P/Q+P/4Q) bits

by a serializer. Control bits are sent through P/4Q links. First
link consist of P/Q control bits of first stage. The extra bit
P/2Q control bits generated in stage 2 constitute extra link.
[2]
4.

Simulation Results

Architecture

Figure 2. Encoder for proposed scheme [2]

Figure 3. Decoder for proposed scheme[2]

Figure 5.RTL View for proposed Encoding Scheme

Figure 4. Flow graph for proposed Encoder

From the Fig.1 the encoder and decoder is placed in the

network interface level of the network in chip. As shown in
the Fig 2. The P=64 bit data is arranged in the matrix manner
the data from the packet is sent according to the scheme
proposed. Additional P/Q+1 (where Q stands for number of
links, in this design assumed to be 8) bits are added as control
bits and data packet enters stage II. Here alternate links (four
odd links) are inverted or send as they are after comparison
with adjacent links as per encoding scheme. Power reduction
acquired in the first stage remains intact as inverting ensures
same number of switching transition. Data bits (P bits) and
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78

Figure 6.RTL View for Encoder

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International Journal of Research in Engineering and Applied Sciences

5.

Synthesis Result

After testing the functionality of Encoding scheme using

Verilog, simulated using Xilinx Spartan-6 platform.
No
Sr.

Parameter

For
Proposed
Encoder
and
Decoder

For
Data
Encoding
Scheme

No. of LUT

415

720

On Chip Power

0.109W

0.126W

On Chip Delay

7.492ns

5.486ns

On
Chip
Frequency

133.476Mhz

182.285Mhz

Figure 7.RTL View for decoder

6.

The Encoding techniques to reduce power consumption due

to self switching activity and cross coupling in NoC links.
The encoding technique which allows reducing the power
dissipated by the links of a NoC and contributed by both the
self switching activity and the coupling switching activity.
The proposed encoding technique has two stages 1st stage
reduce the self switching and the second stage is designed so
to reduce the cross coupling activity. The encoder and
decoder is simulated for the different data stream .The
significant amount of power reduction is obtained from the
encoding technique; the no. of LUTs required is also less but
the other parameters such as delay is increased.

Figure 8.Waveform for proposed Encoding Scheme

Fig. 8 shows the simulation waveform for the encoder as

proposed in the paper. The input data is given to the input of
the encoder. In Encoder the stage 1 counts the number of 0 to
1 transition, if the number of transition is greater than the
threshold value which is calculated as per the Section III A.
If the transition is greater than threshold than the even and
odd bits are shuffled as per the encoding scheme. The output
of the stage 1 encoder is given to the input of the stage II
encoder along with some extra control bits of stage 1. In
stage II the coupling activity of the data in the links are
checked according to the transition table and data is changed
as per the transition from type II to type III. The output is
then given to the serializer. The in the input data is 39
and at the output of the encoder it get reduced to 25. The
due to Type I is 22 for Type II is 10 for Type III is 12 and for
Type IV is 2, at the output of the encoder it changes to for
Type I is 23 for Type II is 4 for Type III is 9 and for Type IV
is 16

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Conclusions

79

References
[1] Maurizio Palesi, Fabrizio Fazzino Giuseppe Ascia, and
Vincenzo Catania,Data
Encoding for Low-Power in
Wormhole-Switched Networks-on-Chipin 12th Euromicro
Conference on Digital System Design / Architectures,
Methods and Tools,pp. 119 -126,2009
[2] Deepa N.Sharma ,G.Laskhminaryanan and Suryakiran
Chavali K.V.R, A Novel Encoding Scheme for Low Power
in Network on Chip links. VLSID '12 Proceedings of the
2012 25th International Conference on VLSI Design Pages
257-261.
[3] M. R. Stan and W. P. Burleson, Bus invert coding for low
power I/O, IEEE Transactions on Very Large Scale
Integration Systems,vol. 3, pp. 4958, Mar. 1995.
[4] K.lee et al.SILENT: Serialized low energy transmission
coding for on chip interconnection network Computer Aided
Design, 2004. ICCAD-2004,pp.448-451.
[5] Maurizio Palesi, Fabrizio Fazzino Giuseppe Ascia, and
Vincenzo Catania,Data
Encoding Scheme in
Networks-on-Chipin IEEE Transaction on Computer Aided
Design Of Integrated Circuit and System.VOL.30 Nov 2011.

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International Journal of Research in Engineering and Applied Sciences

[6] A.Jantsch, R.Lauter and A.Vitkowski,Power analysis of link
level and end to end protection in network on chipin ISCAS,
vol. 2, May 2005
[7] Morgenshtein, I. Cidon, "Comparative analysis of serial vs
parallel links in NoC,"International Symposium on system on
chip 2004 pp-185-189
[8] K. Lee, S.-J. Lee, and H.-J. Yoo, Low-powernetwork-on-chip
for high-performance soc design , IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, vol. 14, pp.
148160, 2006
[9] Jaesung Lee,On chip serialization method for low power
communicationETRI Journal vol.32 Aug 2010.

Chetan S. Behere is pursuing M.Tech

from Yeshwantrao Chavan College of
Engineering; he has completed his B.E
from Nagpur University in 2011.

Somulu G, currently working as an

Assistant Professor in Department of
Electronics Engineering, YCCE, Nagpur,
he received M.Tech from VNIT, Nagpur
and Bachelors from Sri Venkateswara
Engineering College, Hyderabad.
His area of interest is VLSI for Wireless
Communications and
VLSI
for
Biomedical Applications.

Biographies
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