BYRON LUTZ | CS M51A FINAL | MARCH 23, 2012

BEFORE MIDTERM 1

Prime Implicants (PI) are not fully covered by

any other implicant.

Order bits as x3 x2 x1 x0

Essential Prime Implicants (EPI) contain a 1

not contained by any other implicant.

Load is the number of gates the

output of a gate connects to

AFTER MIDTERM 1
Minimize states:

CH 7

1. Divide the states into partitions determined

by their output bit

Partitions:
ACE and BDF

2. Label each partition with a number 1, 2,

3. Separate each of the partitions by what
partition number their next state is in
4. Repeat step 2 and 3 until no more partitions are made.

Partitions: AC,
E, BD, and F

5. Each state in the same partition is an

equivalent state
Flip-Flops: CH 8
T (toggle) Flip-Flop

D Flip-Flop

JK Flip-Flop

SR Flip-Flop

Analyze flip-flop networks:

CH 8

1. Look at each flip-flop and come

up with an expression for each
input
2. Use the transition function of the
flip-flop (above) to change these
equations into equations for
outputs

Make one type of flip-flop out of another: (SR from T)

CH 8

1. Make a next-state K-Maps for the outer (original) flip-flop

(present state (Q) vs. system inputs (S and R))
2. From this, make internal-inputs (T) k-maps that compare the
same (present state (Q)/system inputs (S and R))
3. Use this to get a formula (T=) for the inputs to the internal
flip-flop. Draw the circuit.

The number of inputs to the AND gates

equals the number of decoders in the
system.

Increases by 15

Coincident Decoder Network: CH 9

Decodes Binary to bits (i.e. an input of
binary 0 outputs the 0th bit)

Increases by 1
15

...

31

...

17

16

47

...

33

32

63

...

49

48

Tree Decoder Network: CH 9

Tree decoder network uses the enable pin
of decoders. Only one of the bottom
decoders is enabled, depending on the
higher bits. The output of the enabled decoder is selected by the lower bits.

Encoders & Priority Encoders:

CH 9

Encoders are the opposite of decoders; they take a single input bit and output the bit number in binary.
Priority encoders output only the binary of the highest-inputted bit. (To make a priority encoder, AND gates

in front of an encoder. The AND gate of input_0 takes NOTs of all the other inputs to output 1 when input_0 is the only input.
Same with higher inputs.)

Multiplexer (MUX) & Multiplexer Trees:

CH 9

The output of a multiplexer is one of its

inputs, selected by the selection bits (in
binary). Xs are the inputs and Ss are the
selection bits.
In a MUX tree, the lower-order bits select a bit from each MUX.
The higher-order bits select the appropriate one of these.
De-Multiplexer (DMUX):
A DMUX takes in
one input (x). All the
outputs (ys)
are 0 except
for one: the
output chosen by the
selection bits (ss).
This output is the
same as the input.

CH 9

Make a MUX from an Expression:

CH 9

1. Determine the select bits for the MUX and where the
MUX will output to
2. Reduce the k-map to only the MUX select bits (by adding variables into the map where needed)
3. Number the k-map squares with the MUX select bits
(that you made the same as the k-map labels)
4. Each of the squares is an input to the MUX.

BYRON LUTZ | CS M51A FINAL | PAGE 2

Shifters:

CH 9

Shifters can rotate, pad with 1s, pad with 0s, or take new input.
p-Shifters take an input as a distance to shift (in additition to the shift
direction).

Carry-Ripple Adders:

CH 10

The output of an adder is (x+y+cin)

as well as a cout. (c=carry).
Half & Full Adders:

CH 10

Half-Adders add 2 bits. When you put together more than 1

half-adder, it makes a full adder that adds all bits. Networks of
full adders make complete adders.
Carry-Lookahead Adders:

A carry-ripple adder allows the

carry to propagate through the adder naturally. Its slow.

CH 10

This type of adder is almost the same as a carry-ripple adder, except it has a carry-lookahead module for each full adder that determines if there will be a carry or if it will propagate. Use the formula to
get the carry for 1, 2, up to the maximum bits each full adder. Get the formula in terms of c0, the
input carry.

P: Propagate (XOR the two bits) G: Generate (AND the two bits)

Representations of Signed Numbers:

CH 10

Sign-And-Magnitude: most significant bit (MSB) is the sign

bit. Range: -(2n-1-1) x 2n-1-1
2s Complement: the most significant bit is negative and has a
magnitude. Range: -(2n-1) x 2n-1-1

negative: complement plus 1 i.e. -x = (~x)+1

addition: normal adder module, discard carryout

subtraction: add a negative

1s Complement: the negative is the exact complement. negaALU (Arithmetic Logic Unit):
tive if MSB is 1

negative: complement i.e. -x = ~x

Comparators:

CH 10

Compares numbers to Greater,

Equal, or Smaller

CH 10

Multipliers:

Registers:

CH 10

CH 11

Multiplication Bit
Matrix

Shift Registers:

Register stores a value. If

CH 11

LD is active, the contents of the register

become the input (x) on clock.

Two types of input: parallel or serial.

CTRL: takes 4 possible
inputs: None, Load, Left,
and Right.

If CLR is 1, register gets reset to 0

on clock.

Load: loads parallel data.

Left/Right: shifts the bits to the left or right and
fills the new bit with the serial data input.

Otherwise, on clock, the register

outputs its content.
Counters:

CH 11

Other types of shift registers may only input/output serial or parallel. If the output is serial, it outpts the least
significtn bit.

Stores a state. On an input of 1, advances to the next state. On an input

of 0 outputs the current state.

Carry-Lookahead Adder Network:

When the counter is clocked too

much, it loops back to the beginning
and outputs TC (Terminal Count) as 1

CH 10

Inputs: when Load Inputs is 1, the

inputs are loaded (i.e. sets the counter to a different number)

Network Timing:

CH 8

Setup time: time before clock that the signal must be held
Hold time: time after clock that the signal must be held

hold time of a cell is the hold time of the entire network
Propagation time: for combinational system. Syntax: d1x