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VCC
OE 1 28 A10
A12
WE
DC
NC
A7
A11 2 27 CE
A9 3 26 I/O7
4
3
2
1
32
31
30
A8 4 25 I/O6 A6 5 29 A8
A5 6 28 A9
NC 5 24 I/O5
A4 7 27 A11
WE 6 23 I/O4
A3 8 26 NC
VCC 7 22 I/O3 A2 9 25 OE
RDY/BUSY (or NC) 8 21 GND A1 10 24 A10
A12 9 20 I/O2 A0 11 23 CE
A7 10 19 I/O1 NC 12 22 I/O7
A6 11 18 I/O0 I/O0 13 21 I/O6
14
15
16
17
18
19
20
A5 12 17 A0
A4 13
I/O1
I/O2
VSS
DC
I/O3
I/O4
I/O5
16 A1
A3 14 15 A2 Rev. 0001H–12/99
Note: PLCC package pins 1 and 17 are
DON’T CONNECT.
1
The AT28C64 is accessed like a Static RAM for the read or cycle has been detected, a new access for a read or write
write cycles without the need for external components. Dur- can begin.
ing a byte write, the address and data are latched inter- The CMOS technology offers fast access times of 120 ns at
nally, freeing the microprocessor address and data bus for low power dissipation. When the chip is deselected the
other operations. Following the initiation of a write cycle, standby current is less than 100 µA.
the device will go to a busy state and automatically clear
Atmel’s AT28C64 has additional features to ensure high
and write the latched data using an internal control timer.
quality and manufacturability. The device utilizes error cor-
The device includes two methods for detecting the end of a
rection internally for extended endurance and for improved
write cycle, level detection of RDY/BUSY (unless pin 1 is
data retention characteristics. An extra 32 bytes of
N.C.) and DATA Polling of I/O7 . Once the end of a write
EEPROM are available for device identification or tracking.
Block Diagram
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
2 AT28C64(X)
AT28C64(X)
Device Operation
READ: The AT28C64 is accessed like a Static RAM. same RDY/BUSY line. The RDY/BUSY pin is not con-
When CE and OE are low and WE is high, the data stored nected for the AT28C64X.
at the memory location determined by the address pins is DATA POLLING: The AT28C64 provides DATA Polling to
asserted on the outputs. The outputs are put in a high signal the completion of a write cycle. During a write cycle,
impedance state whenever CE or OE is high. This dual line an attempted read of the data being written results in the
control gives designers increased flexibility in preventing complement of that data for I/O 7 (the other outputs are
bus contention. indeterminate). When the write cycle is finished, true data
BYTE WRITE: Writing data into the AT28C64 is similar to appears on all outputs.
writing into a Static RAM. A low pulse on the WE or CE WRITE PROTECTION: Inadvertent writes to the device
input with OE high and CE or WE low (respectively) ini- are protected against in the following ways: (a) VCC sense –
tiates a byte write. The address location is latched on the if VCC is below 3.8V (typical) the write function is inhibited;
falling edge of WE (or CE); the new data is latched on the (b) VCC power on delay – once VCC has reached 3.8V the
rising edge. Internally, the device performs a self-clear device will automatically time out 5 ms (typical) before
before write. Once a byte write has been started, it will allowing a byte write; and (c) write inhibit – holding any one
automatically time itself to completion. Once a program- of OE low, CE high or WE high inhibits byte write cycles.
ming operation has been initiated and for the duration of
CHIP CLEAR: The contents of the entire memory of the
tWC, a read operation will effectively be a polling operation.
AT28C64 may be set to the high state by the CHIP CLEAR
FAST BYTE WRITE: The AT28C64E offers a byte write operation. By setting CE low and OE to 12 volts, the chip is
time of 200 µs maximum. This feature allows the entire cleared when a 10 msec low pulse is applied to WE.
device to be rewritten in 1.6 seconds.
D E V I C E I DE NT I FI C A TI O N : A n e x t r a 3 2 b y t e s o f
READY/BUSY: Pin 1 is an open drain RDY/BUSY output EEPROM memory are available to the user for device iden-
that can be used to detect the end of a write cycle. tification. By raising A9 to 12 ± 0.5V and using address
RDY/BUSY is actively pulled low during the write cycle and locations 1FE0H to 1FFFH the additional bytes may be
is released at the completion of the write. The open drain written to or read from in the same manner as the regular
connection allows for OR-tying of several devices to the memory array.
3
DC and AC Operating Range
AT28C64-12 AT28C64-15 AT28C64-20 AT28C64-25
Operating Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C
Temperature (Case) Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%
Operating Modes
Mode CE OE WE I/O
Read VIL VIL VIH DOUT
(2)
Write VIL VIH VIL DIN
(1)
Standby/Write Inhibit VIH X X High Z
Write Inhibit X X VIH
Write Inhibit X VIL X
Output Disable X VIH X High Z
(3)
Chip Erase VIL VH VIL High Z
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
3. VH = 12.0V ± 0.5V.
DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC + 1V 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1.0V 100 µA
Com. 2 mA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC + 1.0V
Ind. 3 mA
4 AT28C64(X)
AT28C64(X)
AC Read Characteristics
AT28C64-12 AT28C64-15 AT28C64-20 AT28C64-25
Symbol Parameter Min Max Min Max Min Max Min Max Units
tACC Address to Output Delay 120 150 200 250 ns
(1)
tCE CE to Output Delay 120 150 200 250 ns
(2)
tOE OE to Output Delay 10 60 10 70 10 80 10 100 ns
tDF(3)(4) CE or OE High to Output Float 0 45 0 50 0 55 0 60 ns
Output Hold from OE, CE or
tOH 0 0 0 0 ns
Address, whichever occurred first
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
tR, tF < 20 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 4 6 pF VIN = 0V
COUT 8 12 pF VOUT = 0V
Note: 1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Setup Time 10 ns
tAH Address Hold Time 50 ns
tWP Write Pulse Width (WE or CE) 100 1000 ns
tDS Data Setup Time 50 ns
tDH, tOEH Data, OE Hold Time 10 ns
tCS, tCH CE to WE and WE to CE Setup and Hold Time 0 ns
tDB Time to Device Busy 50 ns
AT28C64 1 ms
tWC Write Cycle Time (option available)
AT28C64E 200 µs
AC Write Waveforms
WE Controlled
CE Controlled
6 AT28C64(X)
AT28C64(X)
tS = tH = 1 µsec (min.)
tW = 10 msec (min.)
VH = 12.0 ± 0.5V
7
8 AT28C64(X)
AT28C64(X)
Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6 28-lead, 0.600" Wide, Plastic Dull Inline Package (PDIP)
28S 28-lead, 0.300" Wide, Plastic Gull Wing, Small Outline (SOIC)
28T 28-lead, Plastic Thin Small Outline Package (TSOP)
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 1 ms
E High Endurance Option: Endurance = 100K Write Cycles; Write Time = 200 µs
9
AT28C64X Ordering Information
tACC ICC (mA)
(ns) Active Standby Ordering Code Package Operation Range
150 30 0.1 AT28C64X-15JC 32J Commercial
AT28C64X-15PC 28P6 (0°C to 70°C)
AT28C64X-15SC 28S
AT28C64X-15TC 28T
45 0.1 AT28C64X-15JI 32J Industrial
AT28C64X-15PI 28P6 (-40°C to 85°C)
AT28C64X-15SI 28S
AT28C64X-15TI 28T
200 30 0.1 AT28C64X-20JC 32J Commercial
AT28C64X-20PC 28P6 (0°C to 70°C)
AT28C64X-20SC 28S
AT28C64X-20TC 28T
45 0.1 AT28C64X-20JI 32J Industrial
AT28C64X-20PI 28P6 (-40°C to 85°C)
AT28C64X-20SI 28S
AT28C64X-20TI 28T
250 30 0.1 AT28C64X-25JC 32J Commercial
AT28C64X-25PC 28P6 (0°C to 70°C)
AT28C64X-25SC 28S
AT28C64X-25TC 28T
45 0.1 AT28C64X-25JI 32J Industrial
AT28C64X-25PI 28P6 (-40°C to 85°C)
AT28C64X-25SI 28S
AT28C64X-25TI 28T
Die Products
Reference Section: Parallel EEPROM Die Products
Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6 28-lead, 0.600" Wide, Plastic Dull Inline Package (PDIP)
28S 28-lead, 0.300" Wide, Plastic Gull Wing, Small Outline (SOIC)
28T 28-lead, Plastic Thin Small Outline Package (TSOP)
10 AT28C64(X)
AT28C64(X)
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28P6, 28-lead, 0.600" Wide, Plastic Dual Inline
Dimensions in Inches and (Millimeters) Package (PDIP)
JEDEC STANDARD MS-016 AE Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AB
.530(13.5) .566(14.4)
.553(14.0)
.490(12.4) .530(13.5)
.032(.813) .547(13.9)
.595(15.1) .021(.533)
.026(.660)
.585(14.9) .013(.330)
.090(2.29)
1.300(33.02) REF MAX
.050(1.27) TYP .030(.762) .220(5.59) .005(.127)
.300(7.62) REF .015(.381) MAX MIN
.430(10.9) .095(2.41)
.390(9.90) .060(1.52) SEATING
AT CONTACT PLANE
.140(3.56) .065(1.65)
POINTS .161(4.09) .015(.381)
.120(3.05)
.125(3.18)
.022(.559)
.065(1.65) .014(.356)
.110(2.79) .041(1.04)
.090(2.29)
.022(.559) X 45˚ MAX (3X) .630(16.0)
.590(15.0)
.453(11.5) 0 REF
.012(.305) 15
.447(11.4)
.008(.203)
.495(12.6) .690(17.5)
.485(12.3) .610(15.5)
28S, 28-lead, 0.300" Wide, Plastic Gull Wing Small 28T, 28-lead, Plastic Thin Small Outline Package
Outline (SOIC) (TSOP)
Dimensions in Inches and (Millimeters) Dimensions in Millimeters and (Inches)*
INDEX
MARK
AREA
11.9 (0.469) 13.7 (0.539)
11.7 (0.461) 13.1 (0.516)
7.15 (0.281)
REF
0.20 (0.008)
0.10 (0.004)
0
5 REF 0.20 (0.008)
0.15 (0.006)
0.70 (0.028)
0.30 (0.012)
11
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