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CyMOS Process Final Report

CyMOS Process Final Report


EE 432: Semiconductor Fabrication Process
5/10/2013
Iowa State University
Group 5: Latif Masud, Yin Huang, Yue Zhang, Yueyi Jaio
Lab Instructor: Andrew Hoyt

CyMOS Process Final Report

Table of Contents
1. Overview
2. Starting wafer
3. Field oxide
4. Lithography for p well
5. Boron diffusion for p well
6. Lithography for PMOS source and drain

7. Boron diffusion for PMOS source and drain


8. Lithography for NMOS source and drain

9. Phosphorous diffusion for NMOS source and drain


10.Lithography for gate
11.Oxidation for gate
12.Lithography for contact vias/ metallization
13.Lithography for contacts
14.Testing
15.Appendix

CyMOS Process Final Report

Overview
The first step that we took in the fabrication process is a field oxide. The purpose of the field
oxide step of the fabrication is to create a protective layer of oxide before any of the actual
fabrication steps are taken. Before the oxidation could take place, we performed a standard
clean to avoid any undesirable chemical reactions. After the field oxide, we performed the
PWELL lithography and diffusion step of fabrication, which consisted of a photolithography step,
boron deposition step, and a boron drive step. The goal of the PWELL lithography and diffusion
portion of the fabrication was to transfer patterns onto the wafers, introduce a dose of boron on
the wafer surface in the deposition step and then drive it deeper into the wafer in the drive step.
After the PWELL lithography and diffusion steps of the process, we performed the PMOS
lithography and diffusion steps of fabrication. Like the PWELL portion, we first performed a
lithography step to transfer patterns and create openings needed for the PMOS source and
drain regions. After that, we performed a boron diffusion to create the source and drain regions
of the PMOS transistors. When this was done, we started the NMOS lithography and diffusion
step of fabrication. To form the NMOS source and drain regions, we again performed a
photolithography step, followed by a deposition and then a drive step. The last portion of
fabrication was to form gate and metal contacts during which the gates for PMOS and NMOS
were made by via a dry oxidation step.

CyMOS Process Final Report

Fabrication Process Details


Starting Wafers
Before starting filed oxidation, resistance of wafers was measured by four point measure
system. Since the wafers types were told by producer, the doping concentration was calculated.
Number of wafers: 6 device wafers, 4 test wafers
Resistivity: 1.289 cm
Dopant: N-Phosphorus
Doping Concentration: 3.63 x 1015 cm-3
Diameter: 3 inch
Thickness: 380 m

Field Oxide
Process Overview
For the wet oxidation, it was a process that at a high temperature, silicon wafer had a reaction
with vaporing water. Before the oxidation, a standard clean was required for avoiding
undesirable chemical reactance with other chemical elements. After standard clean, the
oxidation should be put in a tube with high temperature. During the oxidation, the tube was filled
with nitrogen to protect the oxidation reaction. There was a bubbler outside of tube which can
provide the continuously flow of deionized water vapor. For this part, the main topic was to
interpret the process of oxidation.

Standard Clean
In order to avoid impurities getting into wafer in growth of silicon doxide, the standard clean is
removing imperities that we do not reside on wafer.

Initially, heater of tanks was turned on. After that, 2500 ml DI water was poured into SC 1
with measuring cylinder. Then, I measured 500 ml NH4OH and poured into SC 1. When
o

temperature monitor showed value to 78 C, I measured 500 ml H2O2 and poured into SC 1
o

and wait temperature for getting 78 C again. When the temperature got 78 C, wafer boat
was placed into SC 1 for 15 minutes
After 15 minutes, I moved wafer boat out and put into cascade rinse tank for 3 minutes. At
same time, valve of nitrogen was turned on.
Once time was up, the wafer boat was taken out and put into tub of HF for 15 seconds.
Then, the wafer boat was rinsed in cascade rinse tank for 1 minute.
o
When I waited the temperature of SC 1 to increase to 78 C, I cleaned measuring cylinder
and 3000 ml DI water was measured and poured into SC 2. In addition, I measured 500 ml
HCl and poured into SC 2.
o
At the time of cascade rinse, the temperature of SC 2 got to 78 C, 500 ml H2O2 was
measured and filled into SC 2.

CyMOS Process Final Report

Once the time for cascade rinse was up, wafer boat was placed into SC 2 for another 15
minutes
After 15 minutes, I moved wafer boat out and put into cascade rinse tank for 3 minutes.
The wafer boat was put in dryer for DI water rinsing and spin-drying.

SC-1

Cascade
rinse

SC-2

Cascade
rinse

Spinner

Wet Oxidation

Si 2H 2O

SiO2 2H 2 (Basic chemical reaction)

Before the oxidation:


At first, when the group did the standard clean, the oven was set to about 800oC. Meanwhile,
the ambient air inside furnace tube should be filled with nitrogen. The rate of N2 flow into oven is
adjusted to 1 slpm.
Next, the cap of tube was removed to get quartz boat. During fetching the boat, the wafer boat
was pulled out at rate of 1 inch per 12 seconds. Besides, the heat-resistant glove is very
important tool for this procedure
Then, cleaned wafers were transferred to quartz boat. We placed wafers facing to same
direction between guard wafers.
Finally, the quartz boat was put back into the tube. By using glass rod, the boat was pushed to
middle of oven at rate of 1 inch per 12 seconds. Then, the heat-resistant glove was put on to get
tube cap back.

CyMOS Process Final Report

During the oxidation:


Temperature in tube was ramped up to 1100oC by using temperature controller to set each zone
of tube to have a same temperature.

Figure 1.1: Oxidation time vs. thickness of oxide

We remove the clamp and stopper of bubbler and refill it with deionized water.
The volume of water cannot exceed the black line in bubbler. Then, clamp and stopper were
replaced back.
Water in bubbler was heated up. Bubble temperature controller was set to 980C. After that,
nitrogen gas flowed into bubbler but still not to tube yet.
When the temperature of bubbler got to within 2 oC, the vent for dry nitrogen gas flow was
turned off. The vent between bubbler and tube was turned on. The rate of gas flow was set to 1
slpm. At meanwhile, time counter started to count time. According to formulation of calculating
oxidation time, it needed about 12 to 13 minutes to get expected oxide thickness.

CyMOS Process Final Report

Tube

N 2 H 2O

boat
o
Figure 2: the basic structure of oxidation

After oxidation:
After time was up, vent between bubbler and tube was stopped. Then, vent of dry nitrogen was
turned on again. The rate was set to 0.3 slpm at an idle state. The boat was put in the tube in
whole night until the next group to fetch our wafer out.

Results
The Filmetrics system uses a white light to measure the thickness of particular layer in silicon
wafer. Basically, wafer was placed under a cylinder which can emit a white light. At first, a
silicon sample was measured to obtain reference. After that, our wafers were put on to measure
thickness. This time we used Filmetric system to measure the thickness of oxide layer grew in
the silicon wafer.
Below table indicates the thickness of each of the oxide test wafer:
Wafer number
TW1
TW2
TW3
TW4

Thickness
293.0 m
289.9 m
289.2 m
289.9 m

CyMOS Process Final Report

And we also get the thickness map of one of the wafer.


All the numbers represent the thickness of oxide in the particular location. Unit in m.

291.7

290.9

287.2

283.2

290.6

287.0

284.2

281.5

289.4

287.3

284.7

280.6

286.5

283.7

282.1

280.8

CyMOS Process Final Report

Lithography for PWELL


Purpose

Figure 3: Pictures taken of three different wafers that had were successfully patterned.

The purpose of the PWELL lithography was to create the required openings needed for the
PWELL regions. To form these regions, we needed to etch the patterns of the regions onto the
wafer. This portion could be broken down into several steps, which include barrier layer
formation, photoresist application, mask alignment, development, baking and etching and
photoresist strip.

Lithography Process Summary


To form a barrier layer on the wafer, we place each wafer on a specialized spinner that
automatically drains out any excess liquids or chemicals used in the process. While on this
spinner, we add three to four drops of HMDS (hexamethyldisilazane) to the center of the wafer.
The wafer is then spun for 25 seconds at 4000 revolutions per minute to create an even layer of
HDMS on the surface of the wafer.
For the photoresist application, we simply added drops of photoresist much like the barrier layer
formation step and spun the wafer to create an even layer of the chemical. After the layers of
chemicals were laid down, we baked the wafers in the oven for a short period of time. When the
baking was done, we loaded the wafer under a microscope with a photomask, which is a piece
of glass that consists of the pattern that is to be transferred onto the wafer.
When the photomask and wafer were properly aligned, we started the exposure process to
transfer the patterns onto the wafer. After the exposure was done, we placed the wafers into a
deep dish consisting of MIF-300 develop and then rinsed them. The wafers were then dried with
N2 gas and then observed under the microscope for pattern quality. If the pattern quality
sufficed, we baked the patterns in via post bake step, and then rinsed them, and washed them
with two different types of Acetones and then spun, rinsed and dried to complete the lithography
step.

CyMOS Process Final Report

Result and Problems

Figure 4: Photos of two wafers that had leftover photoresist.

Overall, the lithography process for PWELL formation was successful for all wafers. However,
we did run into the following problems:
-

One of the most common problems that we faced all throughout the fabrication process is
that the chemicalsboth HMDMS (hexamethyldisilazane) and the photoresistwould not
spread evenly when spun on the spinner. We never came up a with a sure-fire solution to
this problem. When the chemicals did not spread evenly, we simply performed a quick clean
by introducing an acid to remove the layer and then introducing a base on top of the acid to
perform a neutralization reaction.

For some of the wafers, we had to repeat the photolithography steps again since the mask
was not properly aligned with the wafer.

After exposure, the wafer is developed with photoresist and needs to use developer to
dissolve photoresist. Since the time that we put wafer into developer is not long enough,
photoresist in the exposure area is not removed completely as seen in Figure 2.

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Boron Diffusion for PWELL


Process Overview and Purpose

Figure 5: Graph of the boron diffusion profile

The purpose of the PWELL diffusion step of fabrication is to form the PWELL regions where the
NMOS transistors will be located. We designed our process to yield a total dosage value of 7.58
x 1013 cm-2. Also, the surface concentration was calculated to be 3.42 x 1017 cm-3 and the
junction depth to be 5.40 m. To form these regions, we performed a boron deposition and drive
step.

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Figure 6: Shows initial boron depositon in the p-well regions. Image reproduced from:
http://archive.nanofab.utah.edu/TechnologyLibrary/MetalGateCMOS/Process/Process2.htm

The purpose of the deposition step is to introduce source boron onto the surface of the silicon
so that it can be driven in further in the drive step (see Figure 2 above for deposition step). For
our fabrication, we performed p+ dopant diffusion. In our case, the p-type is the boron, which
doped the p-well regions of our wafers. The source wafer was a ceramic wafer of boron nitride
(BN) that had been oxidized to form surface layers of B2O3 glass. When heated, this B2O3 glass
evaporated and condensed on the wafer, leading to the following chemical reaction:
2B2O3 + 3Si 4B + 3SiO2
After the right amount of boron has been deposited onto our wafers, we remove the source
wafers and continue onto the boron drive step to diffuse the boron deeper into the silicon wafer.
To perform the boron deposition, we first performed a standard clean as described in section 2b
of this report. After that, we put the wafers into the oven with source wafers placed adjacently so
that the boron would diffuse onto the wafer surface. The oven is preset to provide the right
concentrations of hydrogen and nitrogen gasses to create the optimal environment for the
diffusion to take place.
When the source step is completed, we perform the main soak step of the deposition. According
to our calculations (shown in the appendix) we found that the soak time should be about one
hour. To finish the deposition steps, we deglazed the wafers and finally spin drying the wafers.
After this, the wafers were ready for the drive step.

Figure 3: Shows the boron drive step. Image taken from:


http://archive.nanofab.utah.edu/TechnologyLibrary/MetalGateCMOS/Process/Process2.htm

The purpose of a boron drive step is to make the boron on the surface of the p-well regions
diffuse further into the silicon. In the figure above (Figure 3), we see that the drive in has caused
the boron to diffuse into the silicon much farther than compared with the deposition phase.
Before a drive step was performed, all wafers went through a standard clean process as
described previously. After that, a low temperature oxidation takes place for a short period of
time, after which the wafers are deglazed, rinsed, and spin dried.

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A high temperature oxidation then takes place with an initial ramp up of about half hour and a
wet oxide growth of 10 minutes. After that, the main drive step of close to 18 hours was
performed. Once the drive step was completed, we removed the wafers from the oven,
deglazed, rinsed and dried them.

Results
We felt that the boron diffusion steps went smoothly and that our results were accurate
with what was expected. We were able to attain the values we calculated, which can be
seen in Figure 1.

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Lithography for PMOS Source and Drain


Process Overview and Purpose
The purpose of the second lithography step to create the openings needed for the PMOS
source and drain regions. The second mask provided the PMOS diffusion pattern that could be
used for our final device. It created the highly doped p-type region in silicon wafer.
There were mainly four parts of doing photolithography process.
First was the preparation and setup for exposure machine. We first started the vacuum pumping
and turned on the nitrogen and air switches of the aligner. Then, we opened the aligner match
and pre heat the light bulb which means that it could provide the even intensity UV light
from the lamp. Then, we placed the mask on the holder by pushing the vacuum mask bottom.
When we check the mask that was settled on the holder correctly, we put our cleaned wafer into
tray.
The second step was spinning photoresist on the top of our wafers. We put our wafer in the
spinning machine, and dropped some HDMS onto the center of the wafer. We spun our wafer,
and after the machine stopped by itself for 25 seconds. After inspection on wafer, the AZ 5214
photoresist was sprayed on. Once we finished all of our wafers, we put them in oven for prebake and set 88 degree for 25 min.
As for UV exposure, the wafers firstly were placed on photolithography tray. Then, the tray was
slid into aligner directly under mask. By counterclockwise rotating lever on the left side of
aligner, the wafer made contact with mask. Pulling another lever at left side outward led to
separation mode for wafer and mask. The X, Y direction controllers were adjusted until cross
marks matched with mark in mask. After that, wafers was contacted with mask again and
exposed for 90 seconds at UV light
Once we finished the exposure, the following step was developing photo resister and post bake.
We put some AZ 5214 developing solution in the glass pan and put the exposured wafers into
pan for about 50 seconds. After the developing was finished, we put the wafer in plastic boat
and put it in water for at least three minutes. We also took pictures of those wafers.

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Results
Overall, the lithography process for PMOS formation was successful for all wafers. Below are
pictures we took during the lab.

Figure 1: pictures of the PMOS source and drain lithography step

While most of the process was good, we did run into the following problems:
1) During this lab process, the most difficult problem was to how match cross mark in mask and
with alignment mark in wafer perfectly. Since, we were not familiar with structure of pattern,
sometimes we didnt know where our wafer was. Even though we found the edge of a die in
wafer, it was still a little of difficult to find a right direction to move the wafer.
2) Another problem, which was not so critical, is that during the BOE etch, Observing
whether the surface of wafer was hydrophobic or not was an important signal for us to stop
etching. Sometimes, people forgot to observe this and follow standard operating procedure.

CyMOS Process Final Report

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Boron diffusion for PMOS source and drain


Process Overview and Purpose
Boron Deposition Step

Figure 1: Shows the initial boron deposition in the p-well regions. Image taken from:
http://archive.nanofab.utah.edu/TechnologyLibrary/MetalGateCMOS/Process/Process2.htm

The purpose of this portion is to introduce source boron onto the surface of the silicon so that
it can be driven in further in the latter drive step (see figure above). For this part of the lab, we
essentially performed a P+ dopant diffusion. In our case, the p- type dopant was the Boron.
The source wafer was in this case, a ceramic wafer of boron nitride (BN), which had been
oxidized to form surface layers of B2O3 glass on wafers. When heated, this B2O3 glass
evaporated and condensed on the wafer, leading to the following chemical reaction:

After the expected amount of Boron was deposited onto our wafers, we removed the source
wafers and continued onto the Boron Drive step to diffuse the boron deeper into the silicon
wafer.
To perform the Boron Deposition, we first performed a Standard Clean. In the next step, we
inserted our wafers adjacent to BN source wafers on the wafer boat. The wafer boat was then
pushed into the furnace at a rate of about 1 inch per 12 seconds. Before pushing the wafers
into the furnace, we set the furnace temperature to and the N2 gas flow to be 2 slpm.
After the wafers have been inserted into the oven, we bring down the N 2 gas flow to 1
slpm and introduce 1 slpm of O2 gas. This mixed gas flow is continued for 20 minutes. When
the 20 minute had passed, we introduced 40 sccm of hydrogen gas into the chamber to
begin sourcing step of the deposition, which took 2 minutes.
When the source step was completed, we performed the main soak step of the deposition.
According to our calculations shown in the appendix we found that the soak time should
be 70 minutes at a constant temperature of 850oC. For this step, we turned off vent of O2 and
H2 and introduced 2 lpm of N2. After the 70 minutes had passed, we pulled out the wafers at
a rate of 1 inch per 12 seconds.
To finish the deposition steps, we deglazed the wafers in the BOE tub for 30 seconds,
followed by rinsing in the cascade rinse tub for 3 minutes and finally spin drying the
wafers.

The boron drive process, including the LTO

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Mainly, there were three steps to do boron drive process. By using LTO to remove the
boron skin, wet oxidation grows the oxide on silicon wafer and drove dopant deeper into the
wafer.
After we cleaned the wafers, we checked the temperature condition of tube 3.
When the temperature got to 800oC, the vent of nitrogen was turned on at rate of 1 slpm. Then
we filled the DI water into bubbler and checked the bubble goes correctly inside. Then we
started the nitrogen gas flow through the bubbler with 200 sccm.
Then we turned on the power to bubbler temperature controller and we set temperature of
98C. We wait for about 15 mins for the heating. We put boron wafers in between our silicon
wafers, and load them into the tube. We pushed the boat into the center of furnace by using
glass rod with the rate of 1 inch every 12 seconds for 5 minutes.
We checked the bubbler temperature to make sure that the temperature was 98C, and
then we turned off the dry N 2 flow. Then we turned on vent between bubbler and nitrogen.
After that, the vent between bubbler and tube was turned on. The oxidation process went
about a half hour. We turned off the vent and restarted to let dry N2 gas flow into the furnace.
This was low temperature oxidation (LTO) process.
After the LTO process, we were ready to unload our wafers. By using rod with the rate of one
inch 12 seconds, we took out our silicon wafers. We put them in the plate and waited them
to become cool. We etched the wafers in the BOE tub for 30 seconds and rinse for 3 mins.
Then, the wafers were put into spinner machine for drying wafers.
After we dried those wafers, we reload those wafers again into tube #3.
We checked bubbler as before and then we turned off the bubbler power and we shut off the
flow of nitrogen and turned the flow of dry nitrogen to the tube as 1slpm. We checked the
temperature again. Then we left our wafers in the furnace overnight at 600C and set the
nitrogen flow to 0.3 slpm.

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Results

Figure 2: a profile of P source and drain

According to the notes, first step was one hour at 850 oC. When we did this lab, we used
o
one hour at 1100 C. Be careful, in this lab, the time for oxidation should be also taken into
account for calculating depth.
N (0) =1.77 x1018 cm -3
(Dt) = 7.054 x10-13 cm 2
1

(Dt )2 = 6.134 x10 -10 cm -2


Dose = 7.7712 x1013 cm -2
Depth = 1.243 m

Overall, the diffusion process for PMOS formation was successful for all wafers. While most of
the process was good, we did run into the following problems:.
1) During the photolithography, we got a bad result for spinning photoresist, we used
acetone and methanol to clean wafer and repeated spinning process

Lithography for NMOS Source and Drain

CyMOS Process Final Report

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Figure 7: Pictures of three wafers taken after the lithography was completed. The first wafer shows the pattern has
displaced and overlaps with the border of the die. The second and third wafers show good alignment between the wafer
and the mask.

Process Purpose and Overview


The purpose for performing NMOS lithography is that it creates the openings needed for the
NMOS source and drain regions. The mask used in this lab provides the NMOS diffusion. It
creates the highly doped n-type region in silicon wafer. For this part, we used a level 3 mast to
create the N-type source and drain in the P-type wells formed in previous part of the
fabrication process. A more complete description of the photolithography process can be
found in Section 3b of this report.

Figure 8: The first wafer is another example of a misalignment. The second and third wafer show good alignment.

Result
Overall, the lithography process for NMOS formation was successful for all wafers. Please
refer to Figures 1 and 2 for picture from the process. While most of the process was good, we
did run into the following problems:
-

During lithography process for NMOS source and drain formation, the biggest problem is
that one of our wafers had a misalignment between mask and wafer. In the third picture of
Figure 2, it shows that cross marks were seemly located the correct place. However, as
the first picture of Figure 2 shows, there was a misalignment on the wafer when we
checked a different location in the same die. We had a discussion with TA and we
concluded that it may be a problem with over etching. The cross mark was overly etched
by the developer. Thus, the cross marked we found was not a mark for die.

During SiO2 etch and photoresist strip parts, it took a longer time than what we had
estimated since our time for wet oxidation was slightly longer in the previous lab.

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Phosphorus Diffusion for NMOS Source and Drain


Purpose and Process Overview
For this portion of the fabrication process, we performed a phosphorus diffusion that formed
the NMOS source and drain regions. Much like previous steps in fabrication, this included a
phosphorus deposition and drive step. We designed this portion of the fabrication to yield a
surface concentration of 5.32 x 1019 cm-3, a junction depth of 7.52 m, and an oxide thickness
of 0.29 m. Before any oxide could be deposited on the wafer itself, a standard clean needed
to be performed. A description of the standard clean can be found in section 2 of this report.
After a standard clean has been performed, we can begin the deposition step by putting our
wafers into the oven adjacent to phosphorus source wafer, which will cause the phosphorus to
diffuse onto the wafers at high temperatures. We leave the wafers in the oven for an hour and
a half to complete the source step. After this, we took the wafers out of the oven and
performed a Buffered Oxide Edge (BOE), a cascade rinse, and spun dried the wafers.
After the deposition process, a phosphorus drive is done in the oxidation furnace. This
process is very similar to other drive steps taken throughout the fabrication process, except
the low temperature oxidation was skipped in our case. To start the drive step, we put the
wafers back into the oven with a specified gas mixture per the SOPs. We left the wafers in the
oven for about 1.5 hours to complete the drive step. Once we took out the wafers from the
oven, we perform a standard buffered oxide edge clean, followed by cascade rinse, and then
spin dried the wafer to complete the process.

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Boron and Phosphorus Profiles

For this part, basically, we combined the two steps, deposition and drive, together. Since our
wafers have been doped by boron deposition, we cannot use the background concentration
which we found in the Field Oxide portion of fabrication.
Mechanism of finding junction depth
Considering the time for phosphorous drive, the profile of P-Well doped by boron has a little
bit of change. According to Dr. Tuttles note, the driving time for Boron is 18 hours at T=1125o
C. The time for Phosphorous drive is about one hour, including time for oxidation, Ramp up
and down.
Boron:
D1 = D0exp(-EA/kBT1) (D0 =3.5, EA =1, T1 =1125)
D2 = D0exp(-EA/kBT2) (D0 =3.5, EA =1, T1 =1050)
D1*t1=D2*t2 (t2=1hr)

t1 0.2hr

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Phosphorous:
D1 = D0exp(-EA/kBT1) (D0 =3.68, EA =4.7, T1 =1080)

For the phosphorous profile, we set 3.11E+17 as background. It shows that xj = 0.752um and
N=3.11E+17 which is very close to same concentration at depth 0.754 um.

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22

Lithography for the Gate


Purpose and Process Overview
For this portion of fabrication, it was aimed to grow a thin oxide as a gate for
MOSFET. During the process, the mask 4 was used to make a pattern for the gate.
For the specific detail, it can be found in Section 3b of this report.
Result:
This part was done by our TA. We do not have results for this part.

Oxidation for the Gate


Purpose and Process Overview
The purpose this part was to grow a thin silicon oxide as the gate by using dry
oxidation. The goal of thickness for gate was in the range of 30 nmtox60nm. For
such thin thickness, it was hard to achieve by doing wet oxidation. The better way to
do was done by dry oxidation since the dry oxidation has a slow growth rate.
In order to avoid impurities getting into wafer in growth of silicon doxide, the standard
clean was usd to remove imperities that we do not reside on wafer. For the sepecific
detail, it can found in section 2-b.
As for process of dry oxidation, the following steps show how to do it. Quartz wafer
boat was placed on ceramic plate and loaded into oven. In control panel at back side
of oven, I manually turned on valve of nitrogen and set flowing rate at 1 slpm.After
that, the boat was pushed into middle of oven at rate of 1 inch per 12 seconds for 5
o
minutes.The temperature was set up to 1050 C by manipulating temperature
controller of oven.We waited about 16 minutes and 16 seconds.When the temperature
got to what we want, I turned on valve of oxygen and set flowing rate at 1 slpm.We
waited about 33 minutes for oxidation.When the oxidation was done, the oven was set
o
back to 600 C for overnight
Result

a. Thickness of oxide:
Measurement 1

Measurement 2

Measurement 3

TW 1

0.2461 nm

0.2466 nm

0.2462 nm

TW 2

99.97 nm

99.21 nm

99.56 nm

TW 3

75.70 nm

77.56 nm

76.28 nm

CyMOS Process Final Report

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Lithography for Contact Vias/Metalization


Purpose and Process Overview
For this portion of fabrication, the goal was to create contacts for all kinds of devices.
The mask 5 was used to pattern contact vias. In order to make contacts with other
electronic devices, there must be a metal connection. In our wafers, aluminum
contacts were made. We used the e-beam evaporation to deposit aluminum on
wafers.we can uniformly coat a certain thickness of aluminum at surface of wafers
The steps for lithography were to make a pattern for contact vias. For the specific
details, it can found in section 3-b.
After steps of lithography, a metallization was done to grow a thin layer of aluminum
on the wafer. The following steps show how to do it. To begin with evaporation, the
mechanical pump was turned on first. We vented nitrogen into chamber. Before the
nitrogen flowed into chamber, all other components except pump were in state of
close. After about 3 minutes, the pressure in chamber was equal to outside pressure.
The valve of nitrogen was turned off. The lid of chamber was open. Next, once the
chamber was open, the shutter on source material was removed and the source
material was checked to see whether there was sufficient metal or not for evaporation.
If the source material was low, the aluminum was added. After these were checked,
the wafers were ready to load to wafer holder. Each wafer was turned to face down to
bottom of chamber and clipped safely. Then, the inside wall and bottom of chamber
were clean by using a wipe to move aluminum particles out of chamber. Once these
jobs in above were done, the lid was closed and ready to pump down. The process of
pumping down from 760 Torr pressure to about 5 micro Torr took about 2 hours.
When the chamber was completely pumped, the system started to generate electrons.
The shooting electrons were guided by magnetic field to hit aluminum. Some of
aluminum atoms would depart form source aluminum and flied straightly to wafers due
to low pressure. There was a sensor inside of chamber to measure the thickness of
aluminum deposited on wafers.

Nitrogen
pumped in

load
wafers

Clean and
check
chamber

Air
pumped
out

Evaporation

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Result

In the process of developing, when the wafer was taken out developer, and the
tweezer had slipped on wafer. When wafer was under microscope, there was an
obvious scratch on wafer. It is better to make sure that tweezer does not slip on
wafers. Otherwise some of devices might be damaged. Overall, the processes were
done successfully. There was not serious problem we met in lab.

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25

Lithography for Contacts


Purpose and Process Overview
In This portion of fabrication, the process of pattern in this step was same as pattern
for contact vias. Only difference was that during the alignment, masks were different.
In this alignment, the mask 6 was used. The purpose of doing this lab was that after
metallization, the redundant aluminum was necessary to removed. By doing
photography for contacts, the unnecessary parts were marked and then put into etch
pan to be moved away.
The steps for lithography were to make a pattern for contact vias. For the specific
details, it can found in section 3-b. the differences on this part were that at first, the
mask 6 was used to create pattern and the pattern was to used locate the area for
areas which were not used as metal contacts.
After steps of lithography, the redundant aluminum was needed to move away. The
following steps show how to do it. The wafers were dipped in PAN etch solution (80 ml
H3PO4+80 ml CH3COOH + 20 ml HNO3+20 ml H2O). At time of etching, the edge of
wafer changed color from silver to brown. This phenomenon started from edge and
moved toward the center of wafers. Once the aluminum was etched completely, the
wafers were removed from etch pan. This process took about 6 minutes on average.

Result

CyMOS Process Final Report

Etch time for our wafers:

time

Latif Masud

5 min 20 sec

Yue Zhang

5 min 23 sec

Yueyi Jiao

6 min 52 sec

Yin Huang

6 min 30 sec

26

Basically, the whole processes were done well. We did not meet any problems in this
part. By doing this lab, we completely make our wafers.

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27

Testing
TLM Summary

Figure 1: Cross section of the TLM.

Source: http://www.cleanroom.byu.edu/contact_resistance.phtml

In the reality of TLM measurement, it is unbelievable to measure the resistance of contact


since it is hard to narrow distance between contacts down to zero. However, there is other
way to solve this problem. It is easy to measure resistance between contacts with different
distances. Then, the distance-R curve can be plotted. Based on this curve, the interception of
curve and y axis can be found. The corresponding resistance is two times of contacts
resistance totally. Besides, the interception of curve with x axis is transfer length LT As
following, the pictures show the result of TLM measurement.

TLM Results

Figure 2: TLM1

CyMOS Process Final Report

Figure 2: TLM2

Figure 3: TLM3

28

CyMOS Process Final Report


0.05
X: 1
Y: 0.05

0.04
0.03
0.02

current

0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
-5

X: -1
Y: -0.04993

-4

-3

-2

-1

0
voltage

Figure 4: TLM I-V curve

TLM Resistance
TLM1

TLM2

TLM3

Distance: 10 um (c1-c2) 20um(c2-c3) 40um(c3-c4) 80um(c4-c5) 160um(c5-c6) c means contact


R1 = 87.8

R1=474.75

R1 = no dat

R2 = 172.2

R2=112.54

R2 = 11.2

R3 = 245.8

R3=759.13

R3 = 12.2

R3 = 379.3

R4=1049.1

R4 = 16.1

R5 = 632.6

R5=1681.4

R5 = 23.0

TLM calculations (unit of height: um)


RS=173.4/sq

RS =397.03/sq

RS = 4.315 /sq

RC =44.24

RC = 207.7

RC = 4.58

29

CyMOS Process Final Report


C = 5.31+E(-3) /cm2

C= 0.025 /cm2

LT= 12.75um

30

C= 5.5+E(-4) /cm2

LT= 26.15um

LT= 53.03um

PMOS/NMOS measurement
In the measurement of MOSFET, there are two factors which are necessary to measure,
threshold voltage and K value (uCox). Three probes were used to do measurement. For source,
gate, and drain, each had corresponding probe to be connected to get voltage. In term of NMOS,
gate voltage and drain voltage were positive. On contrast, for PMOS, the gate voltage and drain
voltage were negative. This model was on basis of square model. \
-4

1.8

x 10

vgs=5V
vgs=4V
vgs=3V
vgs=2V
vgs=1V
vgs=0V

1.6
1.4

IDS current

1.2
1
0.8
0.6
0.4
0.2
0
0

0.5

1.5
VDS voltage

2.5

Figure 5: die 44 noms32 no sintering

-4

x 10

vgs=-5V
vgs=-4V
vgs=-3V
vgs=-2V
vgs=-1V

-0.2
-0.4

IDS current

-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-5

-4.5

-4

-3.5

-3

-2.5
-2
VDS voltage

Figure 6: pmos32 no sintering

-1.5

-1

-0.5

CyMOS Process Final Report


NMOS (Vgs=2.5V)

PMOS (Vgs=-1V)

11: VT = 1.5 V (Vds=1V) , I =141.4 ,


K=9998.4uA/V2

VT =

failed , I =

, K=

12: VT = 2V (Vds=0.5V) , I =6.43 ,


K=110.25uA/V2

VT =

failed , I =

, K=

13: VT = 2.1 V (Vds=0.4V) , I =3.491 ,


K=50.8uA/V2

VT = 0.25V(Vds=-1.25V) , I =3.75 , K=
5.986uA/V2

21: VT = 2.1 V (Vds=0.4V) , I =141.41 ,


K=41654.1uA/V2

VT =

failed , I =

, K=

22: VT = 2 V (Vds=0.5V) , I =8.876 ,


K=105uA/V2

VT =

failed , I =

, K=

23: VT = 2 V (Vds=0.5V) , I =5.15 ,


K=35.36uA/V2

VT =

failed , I =

, K=

31: VT = 2.2 V (Vds=0.3V) , I =141.42 ,


K=49381.8uA/V2

VT =

failed , I =

, K=

32: VT = 2 V (Vds=0.5V) , I =10.5 ,


K=98uA/V2

VT =

failed , I =

, K=

33: VT = 2.1 V (Vds=0.4V) , I =6.307 ,


K=55.23uA/V2

VT = 0.15V(Vds=-1.15V) , I =6.92 , K=
8.05uA/V2

31

CyMOS Process Final Report


Wafer Map
Voltage: 10 V
Cox:
11:

21: 79.14 pf 22:78.57 pf

12:

13:

23:78.18 pf

24: 77.32 pf 25: 77.47 pf

31: 79.24 pf 32: 79.34 pf 33: 79.16 pf 34: 78.66 pf

35: 78.11 pf 36: 77.88 pf 37:

41:

42: 79.31 pf 43: 79.33 pf 44: 79.04 pf

45: 78.66 pf 46: 78.56 pf 47:

51:

52: 79.46 pf 53: 79.46 pf 54: 79.41 pf

55: 79.05 pf 56: 79.14 pf 57:

61: 79.63 pf 62: 79.62 pf 63: 79.74 pf

64: 79.82 pf 65: 80.15 pf

71:

72:

73:

32

CyMOS Process Final Report


Boron drive (lab 5 )
P well Low temperature oxidation:

Measured
wafer
Test wafer
1
Test wafer
2
Test wafer
3
Test wafer
4

thickness

thickness

thickness

393.1 nm

399.2 nm

401.2 nm

Average
thickness
397.8 nm

234.2 nm

234.1 nm

234.5 nm

234.3 nm

433.0 nm

442.0 nm

442.5 nm

439.2 nm

403.2 nm

403.1 nm

404.0 nm

404.3 nm

Test wafer 2
289.9 nm

Test wafer 3
289.2 nm

Test wafer 4
289.9 nm

Field Oxide (lab 1):


Measured wafer
thickness

Test wafer 1
293.0 nm

Measure sheet resistance (lab 8:Test wafer 1)

58.45 / sq 57.88 / sq 56.70 / sq 56.84 / sq


56.64 / sq 56.48 / sq 56.21 / sq 56.12 / sq
56.37 / sq 56.73 / sq 56.22 / sq 56.02 / sq
56.41 / sq

57.41 / sq 57.24 / sq 56.02 / sq

33

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34

Phosphorus drive: (lab 7)


Measure oxide thickness:
Measured wafer

thickness

thickness

Average thickness

Test wafer 1

332.9 nm

333.1 nm

333 nm

Test wafer 2

407.2 nm

402.0 nm

404.6 nm

Test wafer 4

400.2 nm

403.4 nm

401.8 nm

Gate oxidation: (lab 9)


Thickness of oxide:
Measurement 1

Measurement 2

Measurement 3

TW 1

0.2461 nm

0.2466 nm

0.2462 nm

TW 2

99.97 nm

99.21 nm

99.56 nm

TW 3

75.70 nm

77.56 nm

76.28 nm

Contact via lithography and metallization: (lab 10)


Sheet resistance of phosphorous diffusion
Table 1
Measurement on TW 1

Measurement result

Measurement 1

6.78 /sq

Measurement 2
Average

7.09 /sq
6.935 /sq

CyMOS Process Final Report


Sheet resistance of boron diffusion:
Table 2
Measurement on TW 2

Measurement result

Measurement 1

31.68 /sq

Measurement 2

36.70 /sq

Average

34.19 /sq

Metal contact lithography: (lab 11)


Sheet resistance of aluminum layer:
Table 3
Measurement on Device wafer

Measurement result

Measurement 1

0.134 /sq

Measurement 2

0.126 /sq

Average

0.13 /sq

35

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36

Appendix A:
Calculation:
Field Oxide
In the experimental process, we put the bare wafer into the 1100C furnace for12 min 20 sec with wet
oxidation process.
Our desired thickness is 0.25 m, therefore we want to setup our time for wet oxidation as 12.27min.

When T = 1100oC, to = 0 m:

from the equation above, we got our


B/A = 2.8952 m/hr
B = 0.5289 m^2/hr
Then, we can caculate the time from equation:

if we put tox = 250 m, and tau = 0, and B/A and A into the equation, we get tome 12.27min.

Lithography for PWELL


No appendix information needs to be provided for this section.

Boron Diffusion for PWELL


Calculations
Constants for boron Diffusion:
EA = 3.50 eV
D0 = 1.0 cm2/s
NB = 3.25 x 1015 cm-3
kB = 8.617 x 10-5 eV/K
T1 = 850 or 1123
T2 = 1125 C or 1398 K

CyMOS Process Final Report

Diffusion Constants

Finding boron Deposition Time

(Dt)1 = D1t1

t1 = 4200s or 70 min

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CyMOS Process Final Report

Finding Junction Depth for boron Drive

xj = 5.394 um

Lithography for PMOS Source and Drain


No appendix information needs to be provided for this section.

Diffusion for PMOS Source and Drain


Constants for Boron Diffusion:
EA = 3.50 eV, D0 = 1.0 cm2/s
NB = 3.25 x 1015 cm-3
-5
kB = 8.617 x 10 eV/K
T1 = 850 C or 1123 K
T2 = 1100 C or 1375 K
Diffusion Constants
t1=3600s t2=4320s
D = D0exp(-EA/kBT)
D1 = (1.0)exp(-3.50/(8.617 x 10-5)(1123))
= 1.9596 x 10-16 um2
D2 = (1.0)exp(-3.50/(8.617 x 10-5)(1375))
= 1.4824 x 10-13 um2

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CyMOS Process Final Report

Lithography for NMOS Source and Drain


No appendix information needs to be provided for this section.

Diffusion for NMOS Source and Drain


Constants for Boron Diffusion:
EA = 3.50 eV
2
D0 = 1.0 cm /s
NB = 3.25 x 1015 cm-3
kB = 8.617 x 10-5 eV/K
T1 = 850 C or 1123 K
T2 = 1125 C or 1398 K
Ns=8.0x 1019 cm-3

D = D0exp(-EA/kBT)
D1 = (1.0)exp(-3.50/(8.617 x 10-5)(1123))
-16
2
= 1.9596 x 10
um
-5
D2 = (1.0)exp(-3.50/(8.617 x 10 )(1398))
-13
2
= 2.41 x 10
um
t1=3600s t2=65520s

Q 2 Ns /
Dt1 7.77 1013 cm 2
N 0 Q / Dt2 /
3.404 1017 cm 3
xj
4Dt2 In( N (0) / N B ) 5.42 m

Constants for Phosphorous Diffusion:


EA = 3.68 eV
D0 = 4.7 cm2/s
17 -3
NB = 3.11 x 10 cm
kB = 8.617 x 10-5 eV/K
T1 = 900 C or 1173 K

39

CyMOS Process Final Report


T2 = 1080 C or 1353 K
20 -3
Ns=7.0x 10 cm
D = D0exp(-EA/kBT)
D1 = (4.7)exp(-3.68/(8.617 x 10-5)(1173))
-16
2
= 7.25x 10
um
D2 = (4.7)exp(-3.68/(8.617 x 10-5)(1353))
-14
2
= 9.204 x 10
um
t1=5400s t2=2988s

Q 2Ns /
Dt1 1.563 1015 cm 2
N 0 Q / Dt2 /
5.318 1019 cm 3
xj
4Dt2 In( N (0) / N B ) 0.752 m

Wet Oxidation
0

T 1080 C
t 19 min s
Bwet

17

9.7 10

B / Awet
t ox

exp( 2.05 / KT ) 0.4798um / hr

386 exp( 0.78 / KT )2.241um / hr


2

B / 2 / ( B / Awet ) ( 1 4 ( B / Awet ) / Bwet (t ) 1) 0.29um

40

CyMOS Process Final Report


Calculation of thickness of gate
T 1323K
B
um
2.0eV
um
( ) dry (3.71 106
) exp(
) 0.0892
eV
A
hr
hr
8.617 10 5
1323K
K
um 2
1.23eV
um2
Bdry (772
) exp(
) 0.0159
eV
hr
hr
8.617 10 5
1323
K
t 0.55 hr
B
4 ( )2
B
A
tox
[ 1
(t ) 1] 0.04um
B
B
2 ( )
A

TLM measurement
RT
RC
Rsemi

Rsemi 2 RC
C

LT W
RS
L
W

MOSFET measurement
ID= 0

Vgs VT

ID= uCox

V
W
(Vgs VT DS )VDS
L
2

ID= uCox

W
(Vgs VT )2 Vgs VT VDS
2L

Vgs VT VDS < Vgs - VT

Vgs -

VT

41

CyMOS Process Final Report


Appendix B:
Process Traveler

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