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DRV8840
SLVSAB7D MAY 2010 REVISED DECEMBER 2015
3 Description
2 Applications
Printers
Scanners
Office Automation Machines
Gaming Machines
Factory Automation
Robotics
PACKAGE
HTSSOP (28)
Simplified Schematic
8.2 to 45 V
ENBL
DRV8840
Controller
PHASE
Current Control
Decay Mode
H-Bridge
5A
Motor Driver
-
nFAULT
Current
Control
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8840
SLVSAB7D MAY 2010 REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
6
7
Overview ................................................................... 8
Functional Block Diagram ......................................... 9
Feature Description................................................... 9
Device Functional Modes........................................ 13
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
10.3 Thermal Considerations ........................................ 19
20
20
20
20
20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2013) to Revision D
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Added MIN value for ISENSEx row from 0.3 V to 0.8 V ................................................................................................... 4
DRV8840
www.ti.com
CP1
CP2
VCP
VM
OUT1
ISEN
OUT2
OUT2
ISEN
OUT1
VM
VREF
VREF
GND
1
2
3
28
25
24
27
26
5
6
23
GND
(PPAD)
7
8
22
21
20
10
19
11
18
12
17
13
16
14
15
GND
I4
I3
I2
I1
I0
NC
ENBL
PHASE
DECAY
nFAULT
nSLEEP
nRESET
V3P3OUT
Pin Functions
PIN
NAME
NO.
I/O (1)
EXTERNAL COMPONENTS
OR CONNECTIONS
DESCRIPTION
14, 28
Device ground
VM
4, 11
V3P3OUT
15
CP1
IO
CP2
IO
VCP
IO
PHASE
20
ENBL
21
Bridge enable
I0
23
I1
24
I2
25
I3
26
I4
27
DECAY
19
nRESET
16
Reset input
nSLEEP
17
12,13
CONTROL
VREF
(1)
DRV8840
SLVSAB7D MAY 2010 REVISED DECEMBER 2015
www.ti.com
NO.
I/O (1)
DESCRIPTION
EXTERNAL COMPONENTS
OR CONNECTIONS
STATUS
18
OD
Fault
ISEN
6, 9
IO
OUT1
5, 10
Bridge output 1
OUT2
7, 8
Bridge output 2
nFAULT
OUTPUT
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
VMx
VREF
MIN
MAX
UNIT
0.3
47
0.5
Input voltage
0.3
0.8
0.8
Internally limited
(4)
40
TA
Tstg
Storage temperature
(1)
(2)
(3)
(4)
40
85
60
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolutemaximumrated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground pin.
Transients of 1 V for less than 25 ns are acceptable.
Power dissipation and thermal limits must be observed.
Electrostatic discharge
(1)
UNIT
2000
500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
VM
(2)
MIN
MAX
8.2
45
UNIT
V
VREF
3.5
IV3P3
mA
fPWM
100
kHz
(1)
(2)
4
DRV8840
www.ti.com
PWP (HTSSOP)
UNIT
28 PINS
RJA
31.6
C/W
RJC(top)
15.9
C/W
RJB
5.6
C/W
JT
0.2
C/W
JB
5.5
C/W
RJC(bot)
1.4
C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
DRV8840
SLVSAB7D MAY 2010 REVISED DECEMBER 2015
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES
IVM
mA
IVMQ
VM = 24 V
10
20
VUVLO
VM rising
7.8
8.2
3.3
3.4
V3P3OUT REGULATOR
V3P3
V3P3OUT voltage
IOUT = 0 to 1 mA
3.2
LOGIC-LEVEL INPUTS
VIL
VIH
2.2
0.6
VHYS
Input hysteresis
0.3
IIL
VIN = 0
IIH
VIN = 3.3 V
RPD
0.7
5.25
0.45
0.6
20
33
100
20
100
IO = 5 mA
IOH
VO = 3.3 V
0.5
0.8
40
DECAY INPUT
VIL
VIH
IIN
Input current
RPU
RPD
V
130
80
H-BRIDGE FETS
RDS(ON)
HS FET on resistance
RDS(ON)
LS FET on resistance
IOFF
VM = 24 V, IO = 1 A, TJ = 25C
0.1
VM = 24 V, IO = 1 A, TJ = 85C
0.13
VM = 24 V, IO = 1 A, TJ = 25C
0.1
VM = 24 V, IO = 1 A, TJ = 85C
0.13
40
0.16
0.16
40
MOTOR DRIVER
fPWM
tBLANK
tR
Rise time
30
200
ns
tF
Fall time
30
200
ns
160
180
660
685
mV
50
kHz
s
3.75
PROTECTION CIRCUITS
IOCP
tTSD
6
Die temperature
150
CURRENT CONTROL
IREF
VREF = 3.3 V
VTRIP
ITRIP
3
635
25%
25%
15%
15%
10%
10%
5%
5%
Reference only
V/V
DRV8840
www.ti.com
14
6.5
12
IVMQ (PA)
IVM (mA)
6
5.5
10
5
8
-40qC
25qC
85qC
125qC
4.5
4
10
15
20
25
30
V(VMx) (V)
35
40
45
-40qC
25qC
85qC
125qC
6
10
15
20
35
40
45
D002
400
-40C
25C
85C
125C
325
RDS(ON) HS + LS (m)
350
RDS(ON) HS + LS (m)
25
30
V(VMx) (V)
D001
300
250
300
275
250
225
200
200
8V
24 V
45 V
175
150
150
8
13
18
23
28
33
V(VMx) (V)
38
43
50
C001
25
25
50
75
100
TA (C)
125
C002
DRV8840
SLVSAB7D MAY 2010 REVISED DECEMBER 2015
www.ti.com
7 Detailed Description
7.1 Overview
The DRV8840 is an integrated motor driver solution for printers, scanners, and other automated equipment
applications. The device integrates a single NMOS H-bridge, charge pump, current sense, current regulation, and
device protection circuitry. The DRV8828 can be powered from a single voltage supply from 8.2 V to 45 V, and is
capable of providing a continuous output current up to 5 A.
A simple PHASE/ENBL interface allows for easy interfacing to an external controller. A 5 bit current control
scheme allows for up to 32 discrete current levels. The current regulation method is adjustable between slow and
fast decay.
Integrated protection circuits allows the device to monitor and protect against overcurrent, undervoltage, and
overtemperature faults which are all reported through a fault indication pin (nFAULT). A low power sleep mode is
integrated which allows the system to lower power consumption when not driving the motor.
DRV8840
www.ti.com
LS Gate
Drive
CP1
V3P3OUT
Internal
VCC
Charge
Pump
Low Side
Gate
Drive
CP2
HS Gate
Drive
VM
VCP
3.3V
VM
VREF
VM
VM
+
VREF
Additional
Bulk Cap
VM
PHASE
OUT1
ENBL
OUT1
I0
I1
+
I2
Stepper
Motor
BDC
I4
Motor Driver
DECAY
OUT2
nRESET
OUT2
Control
Logic/
Indexer
I3
nSLEEP
ISEN
Thermal
Shut
Down
nFAULT
GND
PPAD
ISEN
GND
DRV8840
SLVSAB7D MAY 2010 REVISED DECEMBER 2015
www.ti.com
OCP
VM
VCP, VGD
OUT1
Predrive
DCM
OUT2
ENBL
PHASE
PWM
DECAY
OCP
ISEN
+
I[4:0]
A =5
DAC
5
VREF
ENBL
PHASE
OUT1
OUT2
DRV8840
www.ti.com
(1)
Example:
If a 0.25- sense resistor is used and the VREFx pin is 2.5 V, the full-scale (100%) chopping current will be
2.5 V / (5 0.25 ) = 2 A.
Five input pins (I0 - I4) are used to scale the current in the bridge as a percentage of the full-scale current set by
the VREF input pin and sense resistance. The I0 - I4 pins have internal pulldown resistors of approximately
100 k. The function of the pins is shown in Table 2.
Table 2. Pin Functions
I[4..0]
RELATIVE CURRENT
(% FULL-SCALE CHOPPING CURRENT)
0x00h
0%
0x01h
5%
0x02h
10%
0x03h
15%
0x04h
20%
0x05h
24%
0x06h
29%
0x07h
34%
0x08h
38%
0x09h
43%
0x0Ah
47%
0x0Bh
51%
0x0Ch
56%
0x0Dh
60%
0x0Eh
63%
0x0Fh
67%
0x10h
71%
0x11h
74%
0x12h
77%
0x13h
80%
0x14h
83%
0x15h
86%
0x16h
88%
0x17h
90%
0x18h
92%
0x19h
94%
0x1Ah
96%
0x1Bh
97%
0x1Ch
98%
0x1Dh
99%
0x1Eh
100%
0x1Fh
100%
11
DRV8840
SLVSAB7D MAY 2010 REVISED DECEMBER 2015
www.ti.com
12
DRV8840
www.ti.com
13
DRV8840
SLVSAB7D MAY 2010 REVISED DECEMBER 2015
www.ti.com
CP1
GND
DRV8840
28
0.01 F
2
CP2
I4
VCP
I3
VM
I2
OUT1
I1
ISEN
I0
27
VM
3
0.1 F
0.1 F
26
1M
4
25
24
100 m
6
BDC
10
OUT2
NC
OUT2
ENBL
ISEN
PHASE
OUT1
DECAY
VM
nFAULT
VREF
nSLEEP
VREF
nRESET
23
22
21
20
19
VM
11
100 F
18
0.1 F
12
17
14
GND
PPAD
10 k
13
V3P3OUT
16
15
0.47 F
R1
R2
DRV8840
www.ti.com
REFERENCE
EXAMPLE VALUE
Supply Voltage
VM
24 V
RM
3.9 V
LM
2.9 mH
ITRIP
1.5 A
Sense Resistor
RSENSE
100 m
VREF Voltage
VREF
0.75 V
(2)
15
DRV8840
SLVSAB7D MAY 2010 REVISED DECEMBER 2015
www.ti.com
16
DRV8840
www.ti.com
Power Supply
Parasitic Wire
Inductance
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 10. Setup of Motor Drive System With External Power Supply
17
DRV8840
SLVSAB7D MAY 2010 REVISED DECEMBER 2015
www.ti.com
10 Layout
10.1 Layout Guidelines
Each VM terminal must be bypassed to GND using a low-ESR ceramic bypass capacitors with recommended
values of 0.1 F rated for VM. These capacitors should be placed as close to the VM pins as possible with a
thick trace or ground plane connection to the device GND pin.
The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component may be an
electrolytic.
A low-ESR ceramic capacitor must be placed in between the CP1 and CP2 pins. TI recommends a value of 0.1
F rated for VM . Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. TI recommends a value of 0.47
F rated for 16 V. Place this component as close to the pins as possible. In addition, place a 1 M between VM
and VCP.
Bypass V3P3OUT to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the
pin as possible.
The current sense resistor should be placed as close as possible to the device pins to minimize trace inductance
between the pin and resistor.
+
0.1 F
CP1
GND
CP2
I4
VCP
I3
VM
I2
OUT1
I1
0.1 F
1 M
RISEN
0.47 F
0.1 F
ISEN
I0
OUT2
NC
OUT2
ENBL
ISEN
PHASE
OUT1
DECAY
VM
nFAULT
VREF
nSLEEP
VREF
nRESET
GND
V3P3OUT
0.1 F
18
DRV8840
www.ti.com
2 u RDS(ON) u IOUT
where
(3)
IOUT is equal to the average current drawn by the DC motor. Note that at start-up and fault conditions this current
is much higher than normal running current; these peak currents and their duration also need to be taken into
consideration. The factor of 2 comes from the fact that at any instant two FETs are conducting winding current
(one high-side and one low-side).
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
10.3.2 Heatsinking
The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multilayer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, see the TI application report, PowerPAD Thermally Enhanced
Package (SLMA002), and the TI application brief, PowerPAD Made Easy (SLMA004), available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
19
DRV8840
SLVSAB7D MAY 2010 REVISED DECEMBER 2015
www.ti.com
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
20
www.ti.com
16-Oct-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
DRV8840PWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8840
DRV8840PWPR
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8840
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
www.ti.com
16-Oct-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
16-Oct-2014
Device
DRV8840PWPR
SPQ
HTSSOP
2000
PWP
28
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
16-Oct-2014
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8840PWPR
HTSSOP
PWP
28
2000
367.0
367.0
38.0
Pack Materials-Page 2
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