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Complex
PLA
Both AND and OR arrays are
is programmable.
Costliest and complex
than PROMs.
Programmable ASICs , for which all of the logic cells are predesigned and none of the
mask layers are customized.
Programmable Logic Devices
Field-Programmable Gate Arrays
10. What is Anti fuse?
Anti fuse is an open circuit until forcing a programming current through it
Actel calls its antifuse a programmable low-impedance circuit element (PLICE)
It is an One Time Programming (OTP) technology
Programming current controls the antifuse resistance (typically for 5mA it is 500 Ohms)
11. What is Burning of PROM?
The process of entering data into the PROM by burning internal fuses is called programming or
burning a PROM.
12. What is Full custom ASIC? or What are the features of full custom ASIC? (April15)
To modify according to a customer's individual requirements
All mask layers are customized in a full-custom ASIC
a. Generally, the designer lays out all cells by hand
b. Some automatic placement and routing may be done
c. Critical (timing) paths are usually laid out completely by hand
Full-custom design offers the highest performance and lowest part cost (smallest die size) for a
given design
The manufacturing lead time (the time it takes just to make an ICnot including design time) is
typically eight weeks for a full-custom IC.
13. What is GAL? Give example?
GAL is the Generic Array Logic device
The GAL devices gave them significant advantages over their bipolar PAL counterparts; not only
could GAL devices be programmed quickly and efficiently, but they could also be erased and
reprogrammed. Example: GAL16V8
14. What is Hot electron effect in FAMOS?
Altera MAX 5000 EPLDs and Xilinx EPLDs both use UV-erasable electrically programmable
read-only memory ( EPROM ) cells as their programming technology. The EPROM cell is almost
as small as an antifuse. An EPROM transistor looks like a normal MOS transistor except it has a
second, floating, gate. Applying a programming voltage V PP (usually greater than 12 V) to the
drain of the n- channel EPROM transistor programs the EPROM cell. A high electric field causes
electrons flowing toward the drain to move so fast they jump across the insulating gate
oxide where they are trapped on the bottom, floating, gate. We say these energetic electrons are
Personality matrix:
17. List the CAD tools used in different stages of ASIC Design.
Task
Designer
Architect
Logic
Designer
Circuit Designer
Define
overall
chip
C/RTL
Model
Initial floor
Behavioural Simulation
Logical Simulation
Synthesis Datapath
Cell libraries
Schematics
Circuit Schematics
Tools
Text Editor C Compiler
RTL Simulator
Synthesis Tools
Timing Analyzer Power Estimator
Circuit Simulation
Megacell blocks
Physical Design
Schematic Editor
Circuit Simulator Router
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PART-B
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R =
|A||B|
In this equation | A | and | B | are the sizes of partitions A and B. The size of a partition is
equal to the number of nodes it contains.
2. Distinguish between Global and Detailed routing
Global routing allocates routing resources that are used for connections. Detailed
routing assigns routes to specific metal layers and routing tracks within the global
routing resources.
The goal of global routing is to provide complete instructions to the detailed router on
where to route every net.
The global routing step determines the channels to be used for each interconnect.
Using this information the detailed router decides the exact location and layers for
each interconnect.
The goal of detailed routing is to complete all the connections between logic cells.
3. Distinguish between system partitioning and floor planning.
system partitioning
floor planning Gate array logic
Divide a large system into ASIC-sized pieces
Arrange the blocks of the netlist on the
chip
4. Expand the terms DRC, SPF, RSPF and DSPF
SPF: Standard Parasitic
Format RSPF: Reduced SPF
DSPF: Detailed
SPF DRC:
Design-Rule
Check
5. List out the different types of partitioning methods.
A Simple Partitioning
Constructive Partitioning
Iterative Partitioning
Improvement The
KernighanLin
Algorithm The Ratio-Cut
Algorithm
The Look-ahead
Algorithm Simulated
Annealing
6. List the factors that are to be considered during floor planning.
The parasitics associated with interconnect: the interconnect capacitance (wiring
capacitance or routing capacitance) as well as the interconnect resistance.
7. What are the objectives and goals of detailed routing?
The goal of detailed routing is to complete all the connections between logic cells. The
most common objective is to minimize one or more of the following:
The total interconnect length and area
The number of layer changes that the connections have to make
The delay of critical paths
8. What are the objectives and goals of placement? (April 15)
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The goal of a placement tool is to arrange all the logic cells within the flexible blocks on a
chip. Ideally, the objectives of the placement step are to
Guarantee the router can complete the routing step
Minimize all the critical net delays
Make the chip as dense as possible
Minimize power dissipation
Minimize cross talk between signals
What are the steps involved in min-cut placement algorithm?
1. Cut the placement area into two pieces.
2. Swap the logic cells to minimize the cut cost.
3. Repeat the process from step 1, cutting smaller pieces until all the logic cells are placed
What are the steps involved in the physical design of ASICs?
Design Netlist (after synthesis)
Floorplanning
Partitioning
Placement
Clock-tree Synthesis (CTS)
Routing
Physical Verification
What is channel definition?
During the floorplanning step we assign the areas between blocks that are to be used
for interconnect. This process is known as channel definition or channel allocation .
What is power routing?
Power routing is the process of distributing two stacked layer of metals one for Vdd and
one for Gnd on a chip in various ways.
Power routing is performed after cell placement, allowing more knowledgeable
placement of power structures in the physical layout. Each of the power buses has to be
sized according to the current it will carry. Too much current in a power bus can lead to a
failure through a mechanism known as electro-migration. The required power-bus widths
can be estimated automatically from library information, from a separate power simulation
tool, or by entering the power-bus widths to the routing software by hand. Many routers
use a default power-bus width so that it is quite easy to complete routing of an ASIC.
What is the need for DRC in ASIC design?
ASIC designers perform a design-rule check (DRC) before fabrication to ensure that nothing
has gone wrong in the process of assembling the logic cells and routing. The DRC may be
performed at two levels. The first level of DRC is a phantom-level DRC, which checks for
shorts, spacing violations, or other design-rule problems between logic cells. This is
principally a check of the detailed router. A second-level DRC is performed at the
transistor level. This is principally a check of the correctness of the library cells.
Write the objectives and goals of floor planning.
The goals of floorplanning are to:
arrange the blocks on a chip,
decide the location of the I/O pads,
decide the location and number of the power pads,
decide the type of power distribution, and
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Global routing allocates routing resources that are used for connections.
The global routing is used to provide complete instructions to the detailed router on where
to route every net.
The global routing step determines the channels to be used for each interconnect. Using this
information the detailed router decides the exact location and layers for each interconnect.
It Minimize the total interconnect length and the critical path delay.
16. State the governing equation for RC interconnect delay model.
Power constraints
Technology constraints
Cost constraints
Test constraints
20. What is Simulated annealing?
A different approach to solving large graph problems that arise in VLSI layout, including
system partitioning uses the simulated annealing algorithm.
It takes an existing solution and then makes successive changes in a series of random moves.
Each move is accepted or rejected based on an energy function, calculated for each new trail
configuration.
The minimums of the energy function correspond to the possible.
The best solution is the global minimum.
21. What is meant by half perimeter measure?
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The half perimeter measure is one-half the perimeter of the bounding box. For nets with two or
three terminals, the half perimeter measure is same as the minimum steiner tree. The bounding
box is the smallest rectangle that encloses all the terminals.
PART-B
1. (a) Explain in detail Iterative Partitioning improvement algorithm.
(b) Explain the various steps involved in Floor Planning.
2. (a) Describe the Kernighan-Lin Algorithm.
(b) Differentiate between Global and special routing
3. Discuss in detail circuit extraction and DRC. (April15)
4. Explain the following in the context of floor planning and placement
(a) Cyclic constraints
(b) Channel routing
(c) Clock planning
5. Briefly explain left edge and area routing algorithms.
6. (a) Explain the ASIC physical design flow.
(b) Describe the algorithms used for placement and routing.
7. Write short notes on:
(a) Floor planning tools
(b) Global routing between blocks
(c) Clock routing
8. Explain any one type of partitioning method with example.(April15)
Equivalence collapsing: It is possible that two or more faults, produce same faulty
behavior for all input patterns. These faults are called equivalent faults. Any
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4.
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single fault from the set of equivalent faults can represent the whole set. In this
case, much less than kn fault tests are required for a circuit with n signal line.
Removing equivalent faults from entire set of faults is called fault collapsing. Fault
collapsing significantly decreases the number of faults to check.Dominance
collapsing: Fault F is called dominant to F' if all tests of F' detects F. In this case, F
can be removed from the fault list. If F dominates F' and F' dominates F, then these
two faults are equivalent.
Functional collapsing: Two faults are functionally equivalent if they produce
identical faulty functions or we can say, two faults are functionally equivalent if we
cannot distinguish them at primary outputs (PO) with any input test vector.
Define the term behavioral simulation.
There are several ways to create an imaginary simulation model of a system. One
method models large pieces of a system as black boxes with inputs and outputs.
This type of simulation (often using VHDL or Verilog) is called behavioral
simulation.
Define the terms fault equivalence and fault dominance.
Fault Equivalence: Two faults of a Boolean circuit are called equivalent iff they
transform the circuit such that the two faulty circuits have identical output functions.
Equivalent faults are also called indistinguishable and have exactly the same set of
tests.
Example: An input line s-a-0 and output line s-a-0 in an AND gate.
Fault Dominance: If all tests of fault F1 detect another fault F2, then F2 is said to
dominate F1. The two faults are also called conditionally equivalent with respect
to the test set of F1. When two faults F1 and F2 dominate each other, then they are
equivalent.
State the objectives of prelayout and postlayout simulation.
Prelayout simulation: Check to see if the design functions correctly.
Postlayout simulation: To check the design still works with the added loads of the
interconnect after physical layout is made and then sent to fabrication.
What are the data formats supported in verilog?
Net: Physical connection between structural elements declared with keyword wire.
Register: Registers represent data storage elements. Registers retain value until another
value is placed onto them. It is declared with keyword reg.
What are the types of simulation?
Behavioral simulation
Functional simulation
Static timing analysis
Gate-level simulation
Switch-level simulation
Transistor-level or circuit-level simulation
Procedures in VHDL
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Parallel fault simulation takes advantage of multiple bits of the words in computer memory.
In the simplest case we need only one bit to represent either a '1' or '0' for each node in the
circuit. In a computer that uses a 32-bit word memory we can simulate a set of 32 copies of
the circuit at the same time. One copy is the good circuit, and we insert different faults into
the other copies. When we need to perform a logic operation, to model an AND gate for
example, we can perform the operation across all bits in the word simultaneously. In this
case, using one bit per node on a 32- bit machine, we would expect parallel fault
simulation to be about 32 times faster than serial simulation. The number of bits per node
that we need in order to simulate each circuit depends on the number of states in the logic
system we are using. Thus, if we use a four-state system with '1', '0' , 'X' (unknown), and 'Z'
(high-impedance) states, we need two bits per node.
14. Write the syntax of loop statement used in VHDL.
Basic Loop statement: This loop has no iteration scheme. It will be executed continuously
until it encounters an exit or next statement.
[ loop_label :] loop
sequential statements
[next [label] [when
condition]; [exit [label] [when
condition];
end loop [ loop_label];
While-Loop statement: The while loop evaluates a Boolean iteration condition. When
the condition is TRUE, the loop repeats, otherwise the loop is skipped and the execution
will halt. The syntax for the whileloop is as follows,
[ loop_label :] while condition loop
sequential statements
[next [label] [when
condition]; [exit [label] [when
condition];
end loop[ loop_label ];
The condition of the loop is tested before each iteration, including the first iteration. If it is
false, the loop is terminated.
For-Loop statement: The for-loop uses an integer iteration scheme that determines the
number of iterations. The syntax is as follows,
[ loop_label :] for identifier in range loop
sequential statements
[next [label] [when
condition]; [exit [label] [when
condition];
end loop[ loop_label ];
The identifier (index) is automatically declared by the loop itself, so one does not
need to declare it separately. The value of the identifier can only be read inside
the loop and is not available outside its loop. One cannot assign or change the
value of the index. This is in contrast to the while-loop whose condition can
involve variables that are modified inside the loop.
The range must be a computable integer range in one of the following
forms, in which integer_expression must evaluate to an integer:
integer_expression to integer_expression
integer_expression downto integer_expression
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Detect a fault by first activating (or exciting the fault) in the selected node
using D- calculus
By using Path sensitized method the activated faulty node is controlled and
observed through Primary inputs and outputs.
This basic algorithm of justifying and then propagating a fault works for the
nodes without interference from other nodes.
17. Define PODEM algorithm and its advantages
The path-orianted decision making algorithm solves problem of reconvergent fanout and
allows multipath sensitization. The mathed is similar to the basic algorithm.
18. What are the signals used in BST
TDI-test data input
TDO-test data output
TCK-test clock
TMS-test mode select
19. Define transistor-level simulation
The most accurate but also the most complex & time consuming form of simulation is
transistor level simulation.
20. Write the program for half adder in VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hadd is
port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end hadd;
architecture dataflow of hadd is
begin
sum <= a xor b;
carry <= a and
b;
end dataflow;
PART-B
1. (a) Write a VHDL program for the Full adder and 4-bit serial in serial out register.
(b) Write briefly about the different types of simulation carried out for Logic synthesis.
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2. Discuss in detail about the various combinational and sequential statements used in VHDL
using suitable example.
3. (a) Explain the four basic parts of boundary scan controller.
(b) Describe the deterministic and non deterministic fault simulation algorithms.
4. (a) Discuss the different delay statements available in Verilog HDL and describe how a
sequential circuit can be modeled using Verilog HDL.
(b) Explain any three simulation modes of a simulator.
5. (a) How priority encoder and 8:1 MUX is modeled using behavioral and data flow modeling?
(b) Discuss inertia and transport delay used in signal assignments in VHDL.
6. (a) Compare and contrast ATPG and BIST schemes.
(b) Write notes on CFI Design Representation
7. Describe the following:
(a) Boundary Scan Test
(b) Automatic Test pattern generator.
UNIT IV: FPGA
PART-A
1. Expand FLEX and MAX.
Flexible Logic Element MatriX (FLEX)
Multiple Array Matrix (MAX)
2. Differentiate fine-grain and coarse-grain architecture of FPGA
Fine-grained Architecture
Manipulate data at the bit level
Designers can implement bit manipulation
tasks without wasting reconfigurable
For large and complex calculations numerous
fine- grained PEs are required to implement a
basic computation
Much slower clock rates
Extremely costly relative to coarsegrained architectures
Supports partial array configuration and is
dynamically reconfigurable during
application execution.
Coarse-grained Architecture
Manipulate groups of bits via complex functional
units such as ALUs (arithmetic logic units) and
multipliers
Reconfigurable
resources are wasted during
data manipulation
Fewer coarse-grained PEs are required to
implement a basic computation
Faster
Less Expensive
Both partially and dynamically reconfigurable
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ASIC
Full custom capability for design since
device is manufactured to design specs
Design cycle is not simple.
Field reprogramability is not possible
Two days to two weeks
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Bluetooth was standardized as IEEE 802.15.1, but the standard is no longer maintained.
17. List the components in Digital color camera SoC.
Pixel array, ADC, ASP, Timing & Control block and smart function digital block
18. What are the important factors contributed to the emergence of CMOS image sensor
over the CCD camera?
Recent demand for portable, low-power, miniaturized digital imaging systems.
Present-day CMOS offers submicron feature sizes and low defect and contamination
levels, permitting cost-effective pixel sizes and low junction leakage (or dark) current.
Threshold voltage control and uniformity is stable and reproducible.
New circuit techniques that have been invented or adopted from CCD signal processing,
permits both low noise and high dynamic-range imaging that is competitive with the best
CCDs.
9.What is USB, USB 3.0 Features and List the applications of USB?
Universal Serial Bus
USB 3.0 Features Two primary enhancements defined in the USB 3.0 protocol address
the PC and mobile market demands for higher performance and energy efficiency:
adding a second physical datapath and replacing continuous polling with an interruptdriven protocol.
Applications
PC Human Interface Devices (HID)
Mice
Keyboards
Joysticks
Peripheral Gaming Devices
Game Controllers
Console Keyboards
General
Presenter Tools
Remote Controls
Consumer Electronics
Barcode Scanners
POS Peripherals
Toys
10. List the features of SDRAM controller subsystem.
The SDRAM controller subsystem offers the following features:
Support for double data rate 2 (DDR2), DDR3, and low-power DDR2 (LPDDR2) SDRAM
User-configurable timing parameters
Up to 4 Gb density parts
Two chip selects
Integrated error correction code (ECC), 24- and 40-bit widths
User-configurable memory width of 8, 16, 16+ECC, 32, 32+ECC
Command reordering (look-ahead bank management)
Data reordering (out of order transactions)
User-controllable bank policy on a per port basis for either closed page or conditional open
page accesses
User-configurable priority support with both absolute and relative priority scheduling
Flexible FPGA fabric interface configuration with up to 6 ports and data widths up to 256
bits wide using Avalon-MM and AXI interfaces.
Power management supporting self refresh, partial array self-refresh (PASR), power down,
and LPDDR2 deep power down
PART-B
1. Explain Embedded software development for SoC.
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