OBJECTIVES:

1.
2.
3.
4.

To understand the operation theory of the Bit Splitter.

To understand the operation theory of the balanced modulator.
To design the balanced modulator by using MC1496.
To understand the methods of measuring and adjusting the balanced modulator circuit.

EQUIPMENTS:
1.
2.
3.
4.

ETEK DA-2000-09 module

Function Generator
Multi-meter
Oscilloscope

PROCEDURE:
1. Refer to the figure 17-5 or ETEK DA-2000-09 module.
2. At the input terminal of data signal (Data I/P), input 2.5 V amplitude, 2.5 V offset (i.e. high is 5 V, low is 0 V),
100 Hz frequency and square wave with 22% duty cycle, i.e. a serial input data streams signal with 100.
3. At the input terminal of clock signal (CLK I/P), input 2.5 V amplitude 2.5 V offset (i.e. high is 5 V, low is 0 V),
300 Hz square wave frequency.
4. By using oscilloscope, observe on the I-data output terminal and Q-Data output terminal of bit splitter, then record
the measured results in table 5-1.
5. Change the frequency of data signal to 1 kHz and the frequency of clock signal to 3 kHz, the others remain the
same. By using oscilloscope, observe on the I-data output terminal and Q-data output terminal of bit splitter then
recornd the measured results in 5-1.
6. Change the duty cycle of data signal to 66%, i.e. a serial input data streams signal with 110 and the others
remain the same. Repeat steps 2 to 5. Then record the measured results in table 5-2
Experiment 2: QPSK Modulator
1. Refer to the circuit block diagram of QPSK modulator in figure 17-3, then by using the detail circuit diagrams of
each circuit block diagram from figure 17-5 to figure 17-9, construct the QPSK modulator or ETEK DA-2000-09
module.
2. At the input terminal of data signal (Data I/P), input 2.5 V amplitude and 2.5 V offset (i.e. high is 5 V and low is 0
V) and 100 Hz frequency, square wave with 33% duty cycle, i.e. a serial input data streams signal with 100.
3. At the input terminal of data signal (CLK I/P), input 2.5 V amplitude and 2.5 V offset (i.e. high is 5 V and low is 0
V) and 300 Hz square wave frequency.
4. By using oscilloscope, observe on the I- data output terminal and Q-Data output terminal of bit splitter, and also
the output terminal T1 and T2 of unipolar to bipolar converter. Then records the measured results in table 5-3. Let
Fdata = 1 kHz, fCLK 3 kHz, repeat the above steps and record the measured results in table 5-3.
5. At the carrier signal input terminal (Carrier I/P), input a 500 mV amplitude and 20 kHz sine wave frequency.
6. By using oscilloscope, observe on the output terminal of I-Carrier and Q-Carrier of phase shifter, then adjust the
variable resistor VR1 (or the Phase Adjust of ETEK DA-2000-09 module), so that the phase difference between
I-Carrier and Q-Carrier is 90, then record the measured results in table 5-4
7. By using oscilloscope, observe on the output terminal of balanced modulator 1 (T 3), adjust VR1 (or BMR1 of
ETEK DA-2000-09 module), until the waveform without occurring distortion. Then slightly adjust VR 2 (or BMR2
of ETEK DA-2000-09 module) to avoid the asymmetry of the waveform. Finally record the output signal
waveform of the balanced modulator in table 5-4, which is the I-BPSK modulated signal.
8. By using oscilloscope, observe on the output terminal of balanced modulator 2 (T 4), adjust VR1 (or BMR3 of
ETEK DA-2000-09 module), until the waveform without occurring distortion. Then slightly adjust VR 2 (or BMR4
of ETEK DA-2000-09 module) to avoid the asymmetry of the waveform. Finally record the output signal
waveform of the balanced modulator in table 5-4, which is the I-BPSK modulated signal.
9. By using oscilloscope, observe on the output terminal of Linear summer, which is the combination of I-BPSK and
Q-BPSK modulation signals, then record the measured results in table 5-4, which is QPSK modulated signal.
10. Let Fdata = 1 kHz, fCLK 3 kHz, repeat steps 7 to step 9, then record the measured results in table 5-4.
11. Change the duty cycle of data signal to 66% i.e. a serial input data streams signal with 110 and the others remain
the same. Repeat steps 1 to 10 and by using oscilloscope, observe on the waveform of each signal output terminal,
then record the measured results in table 5-5 and table 5-6.

RESULT AND DISCUSSION:

In this activity, we have performed another Modulation technique called the Quadrature Phase-Shift
Keying. Just a short description, Quadrature Phase-Shift Keying or QPSK is a digital modulation scheme
that conveys data by changing (modulating) the phase of a reference signal (the carrier wave).QPSK is an Mary encoding scheme where N=2 and M= 4. This means that there are 4 output phases for a single carrier
frequency.
This activity is split in to 2 parts, the bit splitter and the Balanced Modulator. The tables below shows
the results of the experiment. The only thing that has been modified in the signal is the phase of the waveform
where it shifts to 45& 135
TABLE 5-1

Data Signal
Frequencies
Clock Signal
Frequencies

100 Hz

1 kHz

300 Hz

3 kHz

Data Signal
Waveforms

I-Data output
Terminal of
Bit Splitter

Q-Data
output
Terminal of
Bit Splitter

TABLE 5-2

Data Signal
Frequencies
Clock Signal
Frequencies

100 Hz

1 kHz

300 Hz

3 kHz

Data Signal
Waveforms

I-Data output
Terminal of
Bit Splitter

Q-Data
output
Terminal of
Bit Splitter

TABLE 5-3

Data Signal
Frequencies
Clock Signal
Frequencies

Data Signal
Waveforms

100 Hz

1 kHz

300 Hz

3 kHz

I-Data output
Terminal of
Bit Splitter

Q-Data
output
Terminal of
Bit Splitter

I-Data output
Terminal T1
of Unipolar
to Bipolar
Converter

Q-Data
output
Terminal T2
of Unipolar
to Bipolar
Converter

TABLE 5-4

Data Signal
Frequencies
Clock Signal
Frequencies

100 Hz

1 kHz

300 Hz

3 kHz

I-Carrier
Output
Terminal of
Phase Shifter

Q-Carrier
Output
Terminal of
Phase Shifter

Output
Terminal of
T3 of
Balanced
Modulator 1
(I-BPSK)

Output
Terminal of
T4 of
Balanced
Modulator 2
(Q-BPSK)

Output
Terminal of
Linear
Summer
(QPSK O/P)

TABLE 5-5

Data Signal
Frequencies
Clock Signal
Frequencies

Data Signal
Waveforms

I-Data output
Terminal of
Bit Splitter

Q-Data
output
Terminal of
Bit Splitter

100 Hz

1 kHz

300 Hz

3 kHz

I-Data output
Terminal T1
of Unipolar
to Bipolar
Converter

Q-Data
output
Terminal T1
of Unipolar
to Bipolar
Converter

TABLE 5-5

Data Signal
Frequencies
Clock Signal
Frequencies

I-Carrier
Output
Terminal of
Phase Shifter

Q-Carrier
Output
Terminal of
Phase Shifter

100 Hz

1 kHz

300 Hz

3 kHz

Output
Terminal of
T3 of
Balanced
Modulator 1
(I-BPSK)

Output
Terminal of
T4 of
Balanced
Modulator 2
(Q-BPSK)

Output
Terminal of
Linear
Summer
(QPSK O/P)

QUESTION AND ANSWER:

1. What are the basic circuit structures of QPSK modulator and also explain its operation theory?
Answer:

The
QPSK
operated with the
ON/OFF timing
and Q channels are alternately gated off

modulator
is
control of the
such that the I

2. What is the operation theory of bit splitter?

Answer: Bit splitter, hence the name, splits the signal input into 2 and directs both into 2 channels, the I and Q.

3. If the data input of bit splitter is 50% duty cycle, what are the output signals of I-Data output terminal and Q-data
output terminal of bit splitter?
Answer:
4. If we need the input phase to be 90 phase difference, then what are the values for R i and Ci in figure 17-8?
(assume the carrier frequency is 100 kHz)
Answer:

DOCUMENTATION:

Somethings not
Confused ECE group
experiment.

right here?
while performing the

SMILE! A nice selfie

operation of the
(Lanuza, Pedrosa,
Nodalo)

after a successful
QPSK modulation
Moneza, Jutba &

CONCLUSION:
In this experiment or activity QPSK splits every signal that is inputted on the Circuit. It uses bit
splitter to divide the signal into 2 and process it. It always has a constant amplitude and only modifies the
Phase of the signal by 45to 135. By using a Balanced modulator, it takes the original signal that has
both sidebands and a carrier signal, and then modulates it so that only the sideband signals come through the
output modulator. This creates a balanced signal, as there is less noise because the carrier signal has been
removed.