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Powerline Communications
Analog Front-End
Check for Samples: AFE031
FEATURES
DESCRIPTION
234
APPLICATIONS
eMetering
Lighting
Solar
Pilot Wire
E_Rx_OUT
PA_OUT
E_Rx_IN
PA_GND
TSENSE
PA_VS
ZC_IN1
ZC_IN2
PA_ISET
REF2
REF1
DVDD
DGND
AGND1
AVDD1
AGND2
AVDD2
ZC_OUT2
ZC_OUT1
E_Tx_CLK
ZC1
Bias
E_Tx_IN
ZC2
E_Tx_OUT
Two-Wire Rx/Tx
RxPGA_1
SCLK
DI
DO
Digital Interface
(SPI)
Rx_PGA1_IN
Power
Amplifier
CS
Rx_PGA1_OUT
Rx_F_IN
DAC
SD
Tx_FLAG
Rx_FLAG
Rx_C1
Control
Register
Rx_C2
INT
Rx Filter
Rx_F_OUT
RxPGA_2
Digital-to-Analog
Converter
TxPGA
Tx Filter
Rx_PGA2_IN
Rx_PGA2_OUT
Tx_F_OUT
PA_IN
Tx_F_IN2
TX_PGA_OUT
Tx_F_IN1
Tx_PGA_IN
AFE031
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD, C2000 are trademarks of Texas Instruments.
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR
PACKAGE MARKING
AFE031AIRGZT
QFN-48 PowerPAD
RGZ
AFE031A
AFE031AIRGZR
QFN-48 PowerPAD
RGZ
AFE031A
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
VALUE
UNIT
+26
Voltage (2)
Current (2)
10
mA
+5.5
10
mA
Voltage limit
10
Current limit
10
mA
+5.5
Voltage
(2)
10
mA
Current (2)
Current (2)
Continuous
Continuous
40 to +150
Storage temperature, TA
55 to +150
Junction temperature, TJ
+150
3000
200
500
ESD ratings
(1)
(2)
(3)
(4)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.4 V beyond the supply rails should
be current limited to 10 mA or less. Output terminals are diode-clamped to the power-supply rails. Output signals that can swing more
than 0.4 V beyond the supply rails should be current limited to 10 mA or less.
Short-circuit to ground.
The AFE031 automatically goes into shutdown at junction temperatures that exceed +150C.
AFE031
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CONDITIONS
MIN
TYP
MAX
UNIT
Tx_DAC
Output range
GND + 0.1
Resolution
AVDD 0.1
3.2
mV
73
dB
56
dB
94
dB
1.5
MSPS
Data rate
Tx_PGA
Input
Input voltage range
Input resistance
GND 0.1
RI
AVDD + 0.1
G = 1 V/V
58
G = 0.707 V/V
68
G = 0.5 V/V
77
G = 0.25 V/V
92
Frequency Response
DAC mode enabled
Bandwidth
BW
G = 1 V/V
MHz
G = 0.707 V/V
MHz
G = 0.5 V/V
10
MHz
G = 0.25 V/V
12
MHz
10
Sourcing
25
mA
Sinking
25
mA
f = 100 kHz
Output
Voltage output swing from
AGND or AVDD
Maximum continuous
current, dc
Output resistance
VO
IO
RO
100
mV
Gain
Gain error
Gain error drift
(1)
0.1
6
+1
%
ppm/C
Total harmonic distortion measured at output of Tx_PGA configured in a gain of 1 V/V with an amplitude of 3 VPP, at a 1-MHz sample
rate.
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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CONDITIONS
MIN
TYP
MAX
UNIT
Tx_FILTER
Input
Input voltage range
Input resistance
(Tx_F_IN1 and Tx_F_IN2)
GND 0.1
RI
AVDD + 0.1
43
95
kHz
Frequency Response
CENELEC A Mode
Passband frequency
3 dB
50
60
dB
910
kHz
dB
145
kHz
3 dB
50
60
dB
870
kHz
dB
Output
Voltage output swing from
AGND or AVDD
Maximum continuous
current, dc
Output resistance
VO
IO
RO
10
100
mV
Sourcing
25
mA
Sinking
25
mA
f = 100 kHz
Transmitter Noise
Integrated noise at PA output (2)
(2)
CENELEC Band A
(40 kHz to 90 kHz)
435
VRMS
460
VRMS
AFE031
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CONDITIONS
MIN
TYP
MAX
UNIT
Input
Input voltage range
Input resistance
PA_VS +
0.1
GND 0.1
RI
20
670
kHz
Frequency Response
Bandwidth
BW
Slew rate
SR
ILOAD = 0
Full-power bandwidth
AC PSRR
10-V step
19
V/s
VOUT = 10 VPP
300
kHz
f = 50 kHz
14
dB
0.3
IO = 1.5 A, sourcing
1.7
0.3
1.3
Output
Voltage output swing from
PA_VS
Voltage output swing from
PA_Gnd
Maximum continuous current, dc
VO
VO
IO = 1.5 A, sinking
IO
1.5
1.7
IO = 1.5 A
0.1
RO
PA disabled
Output impedance
145 ll 120
Gain
Nominal gain
k ll pF
0.4 to 1.5
RLOAD = 1 k
G
6.5
Gain error
TJ = 40C to +125C
0.1
1
V/V
+1
%
ppm/C
TSENSE Diode
Diode ideality factor
1.033
Thermal Shutdown
Junction temperature at shutdown
Hysteresis
Return to normal operation
+160
15
+145
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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CONDITIONS
MIN
TYP
MAX
UNIT
Rx PGA1
Input
Input voltage range
Input resistance
RI
10
VPP
G = 2 V/V
10
G = 1 V/V
15
G = 0.5 V/V
20
G = 0.25 V/V
24
G = 2 V/V
MHz
Frequency Response
Bandwidth
BW
G = 1 V/V
10
MHz
G = 0.5 V/V
13
MHz
G = 0.25 V/V
15
MHz
10
Sourcing
25
mA
Sinking
25
mA
G = 1, f = 100 kHz
Output
Voltage output swing from
AGND or AVDD
Maximum continuous current, dc
Output resistance
VO
IO
RO
100
mV
Gain
Gain error
G = 0.25 V/V
0.1
+1
G = 0.5 V/V
0.1
+1
G = 1 V/V
0.1
+1
G = 2 V/V
0.2
+2
TJ = 40C to +125C
ppm/C
Rx Filter
Input
Input voltage range
Input resistance
GND 0.1
RIN
AVDD + 0.1
90
kHz
Frequency Response
CENELEC A Mode
Passband frequency
3 dB
25
33
dB
270
kHz
dB
145
kHz
Passband frequency
3 dB
23
27
dB
350
kHz
dB
Output
Voltage output swing from
AGND or AVDD
Maximum continuous current, dc
Output resistance
VO
IO
RO
10
Sourcing
25
mA
Sinking
25
mA
f = 100 kHz
100
mV
AFE031
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CONDITIONS
MIN
TYP
MAX
UNIT
Rx PGA2
Input
Input voltage range
Input impedance
GND 0.1
AVDD + 0.1
G = 64 V/V
1.7
G = 16 V/V
6.3
G = 4 V/V
21
G = 1 V/V
53
G = 64 V/V
300
kHz
G = 16 V/V
800
kHz
G = 4 V/V
1.4
MHz
G = 1 V/V
MHz
10
Sourcing
25
mA
Sinking
25
mA
G = 1, f = 100 kHz
RI
Frequency Response
Bandwidth
BW
Output
Voltage output swing from
AGND or AVDD
Maximum continuous current, dc
Output impedance
VO
IO
RO
100
mV
Gain
Gain error
G = 1 V/V
G = 4 V/V
G = 16 V/V
G = 64 V/V
TJ = 40C to +125C
ppm/C
CENELEC Band A
(40 kHz to 90 kHz)
14
VRMS
11
VRMS
Rx Sensitivity
Integrated noise, RTI (1)
(1)
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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CONDITIONS
MIN
TYP
MAX
UNIT
0.01
VIH
VIL
SD pin high
0.7 DVDD
SD > 0.7 DVDD
SD pin low
V
0.3 DVDD
AFE031 in shutdown
VO
H
VOL
IOH = 3 mA
DVDD 0.4
DVDD
IOL = 3 mA
GND
GND + 0.4
IOH
VOH = 3.3 V
VOL
IOL = 4 mA
IOL
VOL = 400 mV
0.4
4
Normal operation
V
mA
DIGITAL TIMING
Gain Timing
0.2
Enable time
4.0
Disable time
2.0
50
POR Timing
Power-On Reset power-up time
(1)
DVDD 2 V
When an interrupt is detected (INT pin low), the contents of the I_Flag and T_Flag Registers can be read to determine the reason for the
interrupt.
AFE031
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CONDITIONS
MIN
TYP
MAX
UNIT
TWO-WIRE TRANSMITTER
Frequency range (1)
50
0 VIN DVDD
kHz
0.01
VIH
VIL
0.7 DVDD
V
0.3 DVDD
VOL
IOH = 3 mA
AVDD 0.4
AVDD
IOL = 3 mA
GND
GND + 0.4
TWO-WIRE RECEIVER
Gain
4.5
dB
Frequency range
300
kHz
25
mA
25
mA
Referenced to VAVDD/2
100
10
Input impedance
100
78
mV
k
AVDD 0.4
10
AVDD + 0.4
+10
Input capacitance
V
mA
pF
Rising threshold
0.45
0.9
1.35
Falling threshold
0.25
0.5
0.75
Hysteresis
0.20
0.4
0.60
Jitter
(1)
10
V
ns
CONDITIONS
MIN
TYP
MAX
UNIT
RI
PA_VS/2
Turn-on time
20
ms
Turn-off time
20
ms
RI
VAVDD/2
Turn-on time
20
ms
Turn-off time
20
ms
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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CONDITIONS
MIN
TYP
MAX
UNIT
PA_VS
+7
+24
DVDD
+3.0
+3.6
AVDD
+3.0
+3.6
Quiescent Current
Power amplifier current
SD pin low
IO = 0, PA = On (1)
IQPA_VS
mA
10
1.2
mA
Rx configuration (4)
61
Tx configuration (3)
IO = 0, PA = Off
IQDVDD
49
(2)
(5)
Tx configuration (3)
2.8
3.7
mA
Rx configuration (4)
3.6
5.3
mA
30
IQAVDD
Shutdown (SD)
PA_VS
SD pin high
75
150
DVDD
SD pin high
10
AVDD
SD pin high
15
40
+125
Temperature
Specified range
(1)
(2)
(3)
(4)
(5)
40
THERMAL INFORMATION
AFE031
THERMAL METRIC (1)
RGZ (QFN)
UNITS
48 PINS
JA
27.8
JCtop
12.1
JB
7.5
JT
0.4
JB
7.4
JCbot
1.7
(1)
C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
10
AFE031
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CONDITION
MIN
TYP
Input capacitance
MAX
UNIT
pF
tRFI
ns
tRFO
DOUT
10
ns
CS high time
tCSH
CS
20
ns
tCS0
10
ns
tCSSC
10
ns
SCLK frequency
fSCLK
20
MHz
tHI
20
ns
tLO
20
ns
tSCCS
10
ns
tCS1
10
ns
tSU
10
ns
tHD
ns
tDO
20
ns
tsoz
20
ns
TIMING DIAGRAMS
tCSH
CS
tCSSC
tSCCS
tLO
tCS1
tCS0
tHI
SCLK
tSU
tHD
1/fSCLK
DIN
tDO
tSOZ
Hi-Z
Hi-Z
DOUT
11
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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tCSH
CS
tCSSC
tSCCS
tHI
tCS1
tCS0
tLO
SCLK
tSU
tHD
1/fSCLK
DIN
tSOZ
tDO
Hi-Z
Hi-Z
DOUT
CS
W0
SDI
SDO
W1
XX
W3
W2
XX
XX
XX
CS
SDI
SDO
R0
R1
D0
XX
R2
D1
R3
D2
Any Command
D3
12
AFE031
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DEVICE INFORMATION
PIN ASSIGNMENTS
Rx_FLAG
Tx_FLAG
PA_ISET
PA_VS1
PA_VS2
PA_OUT1
PA_OUT2
PA_GND1
PA_GND2
ZC_IN1
ZC_IN2
ZC_OUT1
48
47
46
45
44
43
42
41
40
39
38
37
RGZ PACKAGE
QFN-48
(TOP VIEW)
DGND
36
ZC_OUT2
DVDD
35
E_Tx_CLK
SCLK
34
E_Tx_IN
DIN
33
E_Tx_OUT
DOUT
32
E_Rx_IN
CS
31
E_Rx_OUT
Thermal Pad
24
Rx_C1
Rx_F_IN
23
25
Rx_C2
12
22
AGND1
Rx_F_OUT
Rx_PGA1_OUT
21
26
Rx_PGA2_IN
11
20
AVDD1
Rx_PGA2_OUT
Rx_PGA1_IN
19
27
REF1
TSENSE
18
REF2
PA_IN
28
10
17
Tx_F_OUT
INT
16
AGND2
Tx_F_IN2
29
15
Tx_F_IN1
SD
14
AVDD2
Tx_PGA_OUT
30
13
Tx_PGA_IN
DAC
13
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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PIN DESCRIPTIONS
AFE031
PIN NO.
NAME
DGND
Digital ground
DESCRIPTION
DVDD
Digital supply
SCLK
DIN
DOUT
CS
DAC
SD
System shutdown
INT
10
TSENSE
11
AVDD1
Analog lupply
12
AGND1
Analog ground
13
Tx_PGA_IN
14
Tx_PGA_OUT
15
Tx_F_IN1
16
Tx_F_IN2
17
Tx_F_OUT
18
PA_IN
19
REF1
20
Rx PGA2_OUT
21
Rx PGA2_IN
22
Rx_F_OUT
23
Rx_C2
24
Rx_C1
25
Rx_F_IN
26
Rx PGA1_OUT
27
Rx PGA1_IN
28
REF2
29
AGND2
30
AVDD2
Analog supply
31
E_Rx_OUT
32
E_Rx_IN
33
E_Tx_OUT
34
E_Tx_IN
35
E_Tx_CLK
36
ZC_OUT2
37
ZC_OUT1
38
ZC_IN2
39
ZC_IN1
40
PA_GND2
41
PA_GND1
42
PA_OUT2
43
PA_OUT1
44
PA_VS2
45
PA_VS1
46
PA_ISET
47
Tx_FLAG
48
Rx_FLAG
14
AFE031
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DVDD
DGND
AGND1
AVDD1
AGND2
AVDD2
E_Rx_OUT
E_Rx_IN
PA_OUT
TSENSE
PA_GND
PA_VS
PA_ISET
ZC_IN1
ZC_IN2
ZC_OUT2
ZC_OUT1
REF2
REF1
E_Tx_CLK
ZC1
Bias
E_Tx_IN
ZC2
E_Tx_OUT
Two-Wire Rx/Tx
RxPGA_1
SCLK
DI
DO
Digital Interface
(SPI)
Rx_PGA1_IN
Power
Amplifier
CS
Rx_PGA1_OUT
Rx_F_IN
DAC
SD
Tx_FLAG
Rx_FLAG
Rx_C1
Control
Register
Rx_C2
INT
Rx Filter
Rx_F_OUT
RxPGA_2
Digital-to-Analog
Converter
TxPGA
Tx Filter
Rx_PGA2_IN
Rx_PGA2_OUT
Tx_F_OUT
PA_IN
Tx_F_IN2
TX_PGA_OUT
Tx_F_IN1
Tx_PGA_IN
AFE031
15
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTICS
At TJ = +25C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 k connected to PA_ISET (pin 46), unless otherwise noted.
Tx Filter GAIN vs FREQUENCY
20
20
CENELEC A
CENELEC B,C,D
10
10
20
30
20
30
40
40
50
50
60
10k
100k
Frequency (Hz)
CENELEC A
CENELEC B,C,D
10
Gain (dB)
Gain (dB)
10
60
10k
1M
100k
Frequency (Hz)
G001
Figure 5.
PA GAIN vs FREQUENCY
50
40
Gain (dB)
30
20
10
0
10
20
30
100k
1M
Frequency (Hz)
20
15
10
10M
PA Supply = 24V
PA Supply = 15V
PA Supply = 12V
1k
10k
G003
Figure 7.
Tx PGA GAIN vs FREQUENCY
1M
10M
G004
Gain = 1 V/V
Gain = 0.707 V/V
Gain = 0.5 V/V
Gain = 0.25 V/V
30
20
20
10
0
10
10
0
10
20
20
30
30
100k
1M
Frequency (Hz)
Gain = 2 V/V
Gain = 1 V/V
Gain = 0.5 V/V
Gain = 0.25 V/V
30
Gain (dB)
Gain (dB)
100k
Frequency (Hz)
Figure 8.
40
40
10k
G002
Figure 6.
60
40
10k
1M
10M 20M
40
10k
G005
Figure 9.
100k
1M
Frequency (Hz)
10M
100M
G006
Figure 10.
16
AFE031
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60
Gain = 64 V/V
Gain = 16 V/V
Gain = 4 V/V
Gain = 1 V/V
50
40
20
Gain (dB)
Gain (dB)
30
10
10
0
10
20
10
20
30
30
40
10k
100k
1M
Frequency (Hz)
10M
40
10k
100M
100k
Frequency (Hz)
G007
Figure 11.
FILTER CUTOFF vs TEMPERATURE
175
0.3
0.2
150
G008
Figure 12.
200
125
100
0.1
0
0.1
0.2
75
0.3
50
40 25 10
5
20 35 50 65 80
Junction Temperature (C)
95
0.4
40 25 10
110 125
G009
Figure 13.
0.3
0.3
0.2
0.2
Gain Error (%)
0.4
0.1
0
0.1
110 125
G010
0.1
0
0.1
0.2
0.2
0.3
0.3
5
20 35 50 65 80
Junction Temperature (C)
95
0.4
0.4
40 25 10
5
20 35 50 65 80
Junction Temperature (C)
Figure 14.
1M
95
110 125
0.4
40 25 10
G011
Figure 15.
5
20 35 50 65 80
Junction Temperature (C)
95
110 125
G012
Figure 16.
17
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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0.4
60
0.3
Supply Current (mA)
0.2
Gain Error (%)
50
0.1
0
0.1
0.2
40
30
20
10
0.3
0.4
40 25 10
5
20 35 50 65 80
Junction Temperature (C)
95
0
40 25 10
110 125
5
20 35 50 65 80
Junction Temperature (C)
G013
Figure 17.
95
G014
Figure 18.
100
3
+3
Typical
3
60
80
PA Current
AVDD Current
DVDD Current
40
20
2
1.5
1
0.5
0
40 25 10
5
20 35 50 65 80
Junction Temperature (C)
95
110 125
G015
Figure 19.
Tx Filter PULSE RESPONSE
15
20
25
30
RSET (k)
35
40
45
50
G016
PA PULSE RESPONSE
0.2
Tx Filter CENELEC A
Tx Filter CENELEC B
0.15
0.15
0.1
0.1
0.05
0.05
Voltage (V)
Voltage (V)
10
Figure 20.
0.2
0
0.05
0
0.05
0.1
0.1
0.15
0.15
0.2
110 125
0.2
0
10 s/div (dB)
G017
Figure 21.
1 s/div (dB)
G018
Figure 22.
18
AFE031
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0.15
Voltage (V)
0.1
0.05
0
0.05
0.1
0.15
0.2
0
10 s/div (dB)
G019
Figure 23.
19
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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APPLICATION INFORMATION
GENERAL DESCRIPTION
The AFE031 is an integrated powerline communication analog front-end (AFE) device built from a variety of
functional blocks that work in conjunction with a microcontroller. The AFE031 provides the interface between the
microcontroller and a line coupling circuit. The AFE031 delivers high performance and is designed to work with a
minimum number of external components. Consisting of a variety of functional and configurable blocks, the
AFE031 simplifies design efforts and reduces the time to market of many applications.
The AFE031 includes three primary functional blocks:
Power Amplifier (PA)
Transmitter (Tx)
Receiver (Rx)
The AFE031 also consists of other support circuitry blocks that provide zero crossing detection, an additional
two-wire communications channel, and power-saving biasing blocks (see the Functional Block Diagram). All of
these functional blocks are digitally controlled by the microcontroller through the serial interface (SPI).
Figure 24 shows a typical powerline communications application system diagram. Table 1 is a complete list of
the sections within the AFE031.
C2000 MCU
AFE031
DAC
PGA
PA
+
N1
LPF
+
N2
Phase
Neutral
Serial
Interface
Serial
Interface
Bandpass Filter
PGA
PGA
LPF
DESCRIPTION
PA
The PA block includes the power amplifier and associated pedestal biasing circuitry
Tx
Rx
The Rx block includes the Rx PGA1, the Rx Filter, and the Rx PGA2
ERx
ETx
DAC
ZC
REF1
The REF1 block includes the internal bias generator for the PA block
REF2
The REF2 block includes the internal bias generators for the Tx, Rx, ERx, and ETx
blocks
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AFE031
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BLOCK DESCRIPTIONS
PA Block
The Power Amplifier (PA) block consists of a high slew rate, high-voltage, and high-current operational amplifier.
The PA is configured with an inverting gain of 6.5 V/V, has a low-pass filter response, and maintains excellent
linearity and low distortion. The PA is specified to operate from 7 V to 24 V and can deliver up to 1.5 A of
continuous output current over the specified junction temperature range of 40C to +125C. Figure 25 illustrates
the PA block.
PA_VS1
PA_VS2
T_SENSE
PA_OUT1
Power
Amplifier
PA_IN
PA_OUT2
PA_GND1
PA_GND1
PA_ISET
47 mF
100 nF
PA_VS1
PA_VS2
T_SENSE
PA_OUT1
CIN
Power
Amplifier
PA_IN
PA_OUT2
PA_GND1
PA_GND1
PA_ISET
RSET
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AFE031
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The external capacitor, CIN, introduces a single-pole, high-pass characteristic to the PA transfer function;
combined with the inherent low-pass transfer function, this characteristic results in a passband response. The
value of the high-pass cutoff frequency is determined by CIN reacting with the input resistance of the PA circuit,
and can be found from Equation 1:
1
CIN =
(2 p 20 kW fHP)
(1)
Where:
CIN = external input capacitor
fHP = desired high-pass cutoff frequency
For example, setting CIN to 3.3 nF results in a high-pass cutoff frequency of 2.4 kHz. The voltage rating for CIN
should be determined to withstand operation up to the PA power-supply voltage.
When the transmitter is not in use, the output can be disabled and placed into a high-impedance state by writing
a '0' to the PA-OUT bit in the Enable2 Register. Additional power savings can be realized by shutting down the
PA when not in use. Shutting down the PA for power savings is accomplished by writing a '0' to the PA bit in the
Enable1 Register. Shutting down the PA also results in the PA output entering a high-impedance state. When the
PA shuts down, it consumes only 2 mW of power.
The PA_ISET pin (pin 46) provides a resistor-programmable output current limit for the PA block. Equation 2
determines the value of the external RSET resistor attached to this pin.
1.2 V
- 5 kW
RSET = 20 kW I
(2)
LIM
Where:
RSET = the value of the external resistor connected between pin 46 and ground.
ILIM = the value of the desired current limit for the PA.
Note that to ensure proper design margin with respect to manufacturing and temperature variations, a 30%
decrease of the value used in Equation 2 for ILIM over the nominal value of ILIM is recommended. See Figure 20,
PA Current Limit vs RSET.
Tx Block
The Tx block consists of the Tx PGA and Tx Filter. The Tx PGA is a low-noise, high-performance, programmable
gain amplifier. In DAC mode (where pin 7 is a logical '1' and Enable1 Register bit location 5 is a logical '1'), the
Tx PGA operates as the internal digital-to-analog converter (DAC) output buffer with programmable gain. In
PWM mode (where pin 7 is a logical '0' and Enable1 Register bit location 5 is a logical '0'), the Tx PGA operates
as a stand-alone programmable gain amplifier. The Tx PGA gain is programmed through the serial interface. The
Tx PGA gain settings are 0.25 V/V, 0.5 V/V, 0.707 V/V, and 1 V/V.
The Tx Filter is a unity-gain, fourth-order low-pass filter. The Tx Filter cutoff frequency is selectable between
CENELEC A or CENELEC B, C, and D modes. The Control1 Register bit location 3 setting (CA CBCD)
determines the cutoff frequency. Setting Control1 Register bit location 3 to '0' selects the CENELEC A band;
setting Control1 Register bit location 3 to '1' selects CENELEC B, C, and D bands.
The AFE031 supports both DAC inputs or PWM inputs for the Tx signal path. DAC mode is recommended for
best performance. In DAC mode, no external components in the Tx signal path are required to meet regulatory
signal emissions requirements. When in DAC mode, the AFE031 accepts serial data from the microprocessor
and writes that data to the internal DAC registers. When in DAC mode (where pin 7 is a logical '1' and Enable1
Register bit location 5 is a logical '1'), the Tx PGA output must be directly coupled to the Tx_FIN1 input and the
unused Tx_FIN2 input must be grounded.
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AFE031
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The proper connections for the Tx signal path for DAC mode operation are shown in Figure 27. Operating in
DAC mode results in the lowest distortion signal injected onto the ac mains. No additional external filtering
components are required to meet CENELEC requirements for A, B, C or D bands when operating in DAC mode.
Inside the AFE031
MCU
SCLK
PA_OUT1
DIN
SPI
DOUT
DAC
PGA
PA
LPF
PA_OUT2
CS
Tx_PGA_
OUT
Tx_F_
IN1
Tx_F_
IN2
Tx_F_
OUT
PA_IN
Tx_PGA_IN
C
C=
(1)
1
Note (1)
2pf22 kW
For capacitor value C, f is the desired lower cutoff frequency and 22 k is the PA input resistance.
GPIO
Tx_F_IN2
PGA
LPF
PA
PA_OUT2
Note (1)
Tx_F_OUT
Tx_PGA_ Tx_PGA_
IN
OUT
PA_IN
C=
(1)
(2)
For capacitor value C, f is the desired lower cutoff frequency and 22 k is the PA input resistance.
1
Note (2)
2pf22 kW
Figure 28. Recommended Tx Signal Chain Connections in PWM Mode Using One PWM Signal
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AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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Note (1)
Inside the AFE031
MCU
43 kW
Tx_F_IN1
PA_OUT1
GPIO
PGA
LPF
Tx_F_IN2
PA
GPIO
PA_OUT2
43 kW
Tx_F_OUT
Tx_PGA_ Tx_PGA_
IN
OUT
PA_IN
C=
1
Note (2)
2pf22 kW
(1)
When using both Tx Filter inputs, use 43-k resistors to match the input resistance for best frequency response.
(2)
For capacitor value C, f is the desired lower cutoff frequency and 22 k is the PA input resistance.
Figure 29. Recommended Tx Signal Chain Connections in PWM Mode Using Two PWM Signals
In PWM mode, there is inherently more distortion from the PWM signal than from the internal DAC. To achieve
the best results in PWM mode, add passive RC filters to increase the low-pass filtering. Figure 30 and Figure 31
illustrate the recommended locations of these RC filters.
Inside the AFE031
MCU
Tx_F_IN1
PA_OUT1
GPIO
Tx_F_IN2
PGA
LPF
PA
PA_OUT2
Note (1)
Tx_F_OUT
510 W
Tx_PGA_ Tx_PGA_
OUT
IN
PA_IN
510 W
C
C=
1
Note (3)
2pf22 kW
Note (2)
(1)
(2)
Refer to Table 2.
(3)
For capacitor value C, f is the desired lower cutoff frequency and 22 k is the PA input resistance.
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AFE031
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Note (1)
Inside the AFE031
MCU
43 kW
Tx_F_IN1
PA_OUT1
GPIO
Tx_F_IN2
PGA
LPF
PA
GPIO
PA_OUT2
43 kW
Tx_F_OUT
510 W
Tx_PGA_ Tx_PGA_
OUT
IN
PA_IN
510 W
C
C=
1
Note (3)
2pf22 kW
Note (2)
(1)
When using both Tx Filter inputs, use 43-k resistors to match the input resistance for best frequency response.
(2)
Refer to Table 2.
(3)
For capacitor value C, f is the desired lower cutoff frequency and 22 k is the PA input resistance.
R ()
C (nF)
510
2.7
CENELEC A
510
1.5
CENELEC B, C, D
510
The Tx PGA and Tx Filter each have the inputs and outputs externally available in order to provide maximum
system design flexibility. Care should be taken when laying out the PCB traces from the inputs or outputs to
avoid excessive capacitive loading. Keeping the PCB capacitance from the inputs to ground, or from the outputs
to ground, less than 100 pF is recommended.
Rx Block
The Rx block consists of Rx PGA1, the Rx Filter, and Rx PGA2. Both Rx PGA1 and Rx PGA2 are highperformance programmable gain amplifiers. Rx PGA1 can be configured through the SPI to operate as either an
attenuator or in gain. The gain steps of the Rx PGA1 are 0.25 V/V, 0.5 V/V, 1 V/V, and 2 V/V. The gain steps of
the Rx PGA2 are 1 V/V, 4 V/V, 16 V/V, and 64 V/V. Configuring the Rx PGA1 as an attenuator (at gains less
than 1 V/V) is useful for applications where the presence of large interference signals are present within the
signal band. Attenuating the large interference allows these signals to pass through the analog Rx signal chain
without causing an overload; the interference signal can then be processed and removed within the
microprocessor as necessary.
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AFE031
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The Rx Filter is a very low noise, unity-gain, fourth-order low-pass filter. The Rx Filter cutoff frequency is
selectable between CENELEC A or CENELEC B, C, and D modes. The Control1 Register bit location 3 setting
(CA CBCD) determines the cutoff frequency. Setting Control1 Register bit location 3 to '0' selects the CENELEC
A band; setting Control1 Register bit location 3 to '1' selects the CENELEC B, C, and D bands. Because the Rx
Filter is a very low noise analog filter, two external capacitors are required to properly configure the Rx Filter.
Table 3 shows the proper capacitance values for CENELEC A, B, C, and D bands. Capacitor Rx C1 is connected
between pin 24 and ground, and Rx C2 is connected between pin 23 and ground. For the capacitors shown, it is
recommended that these components be rated to withstand the full AVDD power-supply voltage
Table 3. Recommended External Capacitors Required for Rx Filter
FREQUENCY BAND
Rx C1, PIN 24
Rx C2, PIN 23
CENELEC A
680 pF
680 pF
90
CENELEC B, C, D
270 pF
560 pF
145
330 W
PGA
PGA
LPF
Rx_PGA1_
IN
C1 =
Rx_PGA2_
OUT
1
Note (1)
2pfRIN,PGA1
Rx_C1
Rx_C2
Rx_F_
OUT
Rx_F_IN
Rx_PGA1_OUT
Rx C1
RX_PGA2_IN
Rx C2
C2 =
C2
1
2pfRIN,PGA2
Note (2)
(1)
For capacitor value C1, f is the desired lower cutoff frequency and RIN,PGA1 is the input resistance of Rx PGA1.
(2)
For capacitor value C2, f is the desired lower cutoff frequency and RIN,PGA2 is the input resistance of Rx PGA2.
(3)
Refer to Table 3.
C1
L1
To Rx PGA1
R2
C2
L2
C=
(1)
1
See Note (1)
2pfRIN,PGA1
For capacitor value C, f is the desired lower cutoff frequency and RIN,PGA1 is the input resistance of Rx PGA1. Refer
to Table 3.
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AFE031
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The following steps can be used to quickly design the passive passband filter. (Note that these steps produce an
approximate result.)
1. Choose the filter characteristic impedance, ZC:
For 6-db passband attenuation: R1 = R2 = ZC
For 0-db passband attenuation: R1 = ZC, R2 = 10 ZC
2. Calculate values for C1, C2, L1, and L2 using the following equations:
1
C1 = (2 p f Z )
1
C
1
C2 = (2 p f Z )
2
C
L1 =
ZC
(2 p f2)
L2 =
ZC
(2 p f1)
CHARACTERISTIC
IMPEDANCE
()
R1
()
R2
()
C1
(nF)
C2
(nF)
L1
(H)
L2
(H)
CENELEC A
35 to 95
1k
1k
10k
4.7
1.5
1500
4700
CENELEC B, C, D
95 to 150
1k
1k
10k
1.7
1200
1500
SFSK
63 to 74
1k
1k
10k
2.7
2.2
2200
2200
FREQUENCY BAND
Table 5. Recommended Component Values for Fourth-Order Passive Bandpass Filter (6-db Passband
Attenuation)
FREQUENCY
RANGE
(kHz)
CHARACTERISTIC
IMPEDANCE
()
R1
()
R2
()
C1
(nF)
C2
(nF)
L1
(H)
L2
(H)
CENELEC A
35 to 95
1k
1k
1k
4.7
1.5
1500
4700
CENELEC B, C, D
95 to 150
1k
1k
1k
1.7
1200
1500
SFSK
63 to 74
1k
1k
1k
2.7
2.2
2200
2200
FREQUENCY BAND
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AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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The Rx PGA1, Rx Filter, and Rx PGA2 components have all inputs and outputs externally available to provide
maximum system design flexibility. Care should be taken when laying out the PCB traces from the inputs or
outputs to avoid excessive capacitive loading. Keeping the PCB capacitance from the inputs to ground, or
outputs to ground, below 100 pF is recommended.
Figure 34 shows the complete Rx signal path, including the optional passive passband filter.
C1 =
1
2pfRIN,PGA1
Inside the AFE031
Note (1)
R2
C3
C1
L1
330 W
PGA
R3
C4
L2
LPF
PGA
Rx_PGA1_
IN
To ADC
input on MCU
Rx_PGA2_
OUT
Rx_C1
Rx_PGA1_OUT
Rx_C2
Rx_F_
OUT
Rx_F_IN
Rx C1
RX_PGA2_IN
Rx C2
C2
C2 =
1
2pfRIN,PGA2
Note (2)
(1)
For capacitor value C1,f is the desired lower cutoff frequency and RIN,PGA1 is the input resistance of Rx PGA1.
(2)
For capacitor value C2,f is the desired lower cutoff frequency and RIN,PGA2 is the input resistance of Rx PGA2.
(3)
Refer to Table 3.
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AFE031
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CS
DAC
DIN
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
Time
NOTE: Dashed lines indicate optional additional clocks (data are ignored).
LOCATION
(0 = LSB)
DEFAULT
R/W
FUNCTION
DAC<0>
--
Truncated
DAC<1>
--
Truncated
DAC<2>
--
Truncated
DAC<3>
--
Truncated
DAC<4>
--
Truncated
DAC<5>
--
Truncated
DAC<6>
--
DAC<7>
--
DAC bit 1
DAC<8>
--
DAC bit 2
DAC<9>
--
DAC bit 3
DAC<10>
10
--
DAC bit 4
DAC<11>
11
--
DAC bit 5
DAC<12>
12
--
DAC bit 6
DAC<13>
13
--
DAC bit 7
DAC<14>
14
--
DAC bit 8
DAC<15>
15
--
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AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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External 1-mF
noise reduction capacitor
PA_VS
bias
2
PA_GND
External 1-nF
noise reduction capacitor
AVDD
bias
2
AGND
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AFE031
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AVDD
3.3 V
ZLLS410 or
equivalent
330 kW
330 kW
120 VAC
to 240 VAC
50/60 Hz
AVDD
330 kW
ZCIN
ZCOUT
Zero
Crossing
ZLLS410 or
equivalent
AGND
Inside the AFE031
-350
ZCOUT
3.3
0.0
0
50
100
Time (5 ms/div)
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AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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For maximum protection of the AFE031 against line transients, it is recommended to use Schottky diodes as
indicated in Figure 38. These diodes should limit the ZC_IN pins (pins 38 and 39) to within the maximum rating
of (AVDD + 0.4 V) and (AGND 0.4 V). Some applications may require an isolated zero crossing detection circuit.
With a minimal amount of components, the AFE031 can be configured for isolated zero crossing detection, as
Figure 40 shows.
+
AVDD
3.3 V
AVDD
ZCIN
ZCOUT
Zero
Crossing
120 VAC
to 240 VAC
50/60 Hz
AGND
Inside the AFE031
PS2505-1A Opto Isolator
or equivalent
-350
ZCOUT
3.3
0.0
0
50
100
Time (5 ms/div)
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AFE031
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Gain (dB)
-20
fHP =
1
2pRINCEXT
where:
RIN = Input resistance of ERx = 78 kW
CEXT = External capacitance
-40
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
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AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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The E_Rx_Out pin can be directly connected to either an available analog-to-digital converter (ADC) input or
GPIO on the host microcontroller. Figure 44 illustrates a typical two-wire application for ETx and ERx.
AFE031
Internal Configuration
E_Tx_In
TMS320F28x
E_Tx_Out
GPIO
Flexible PLC
Software Engine
CEXT
E_Rx_In
E_Tx_CLK
GPIO
+
N1
+
N2
Two-Wire Bus
E_Rx_Out
GND
GPIO
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AFE031
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SERIAL INTERFACE
The AFE031 is controlled through a serial interface that allows read/write access to the control and data
registers. A host SPI frame consists of a R/W bit, a 6-bit register address, and eight data bits. Data are shifted
out on the falling edge of SCLK and latched on the rising edge of SCLK. Refer to the Timing Diagrams for a valid
host SPI communications protocol. Table 7 through Table 16 show the complete register information.
Table 7. Data Register
ADDRESS
DEFAULT
ENABLE1
REGISTER
0x01
0x00
FUNCTION
GAIN SELECT
0x02
0x32
ENABLE2
0x03
0x00
CONTROL1
0x04
0x00
CONTROL2
0x05
0x01
Interrupt enable
RESET
0x09
0x00
DIE_ID
0x0A
0x00
Die name
REVISION
0x0B
0x02
Die revision
R/W
ADDR9
ADDR10
10
ADDR11
11
ADDR12
12
ADDR13
13
ADDR14
14
R/W
15
BIT NAME
ADDR8
FUNCTION
LOCATION
(0 = LSB)
DEFAULT
R/W
FUNCTION
PA
R/W
TX
R/W
RX
R/W
ERX
R/W
ETX
R/W
DAC
R/W
--
--
Reserved
--
--
Reserved
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AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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RX2G-0,
RX2G-1
TXG-0,
TXG-1
LOCATION
(0 = LSB)
0, 1
2, 3
DEFAULT
0, 1
0, 0
R/W
FUNCTION
R/W
R/W
4, 5
1, 1
R/W
--
--
Reserved
--
--
Reserved
LOCATION
(0 = LSB)
DEFAULT
R/W
FUNCTION
ZC
R/W
REF1
R/W
REF2
R/W
PA_OUT
R/W
--
--
Reserved
--
--
Reserved
--
--
Reserved
--
--
Reserved
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AFE031
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LOCATION
(0 = LSB)
DEFAULT
R/W
FUNCTION
TX_CAL
R/W
RX_CAL
R/W
TX_PGA_CAL
R/W
CA_CBCD
R/W
--
--
Reserved
--
--
Reserved
TX_FLAG
RX_FLAG
LOCATION
(0 = LSB)
DEFAULT
R/W
--
--
Reserved
--
--
Reserved
--
--
Reserved
--
--
Reserved
--
--
Reserved
T_FLAG_EN
R/W
I_FLAG_EN
R/W
--
--
FUNCTION
Reserved
37
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
www.ti.com
LOCATION
(0 = LSB)
DEFAULT
R/W
--
--
Reserved
--
--
Reserved
2, 3, 4
0, 0, 0
R/W
SOFTRST0,
SOFTRST1,
SOFTRST2
T_FLAG
I_FLAG
--
R/W
--
FUNCTION
Reserved
LOCATION
(0 = LSB)
DEFAULT
R/W
DIE ID<0>
DIE ID<1>
DIE ID<2>
DIE ID<3>
DIE ID<4>
DIE ID<5>
DIE ID<6>
DIE ID<7>
FUNCTION
LOCATION
(0 = LSB)
DEFAULT
R/W
REVISION ID<0>
REVISION ID<1>
REVISION ID<2>
REVISION ID<3>
REVISION ID<4>
REVISION ID<5>
REVISION ID<6>
REVISION ID<7>
FUNCTION
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AFE031
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POWER SUPPLIES
The AFE031 has two low-voltage analog power-supply pins and one low-voltage digital supply pin. Internally, the
two analog supply pins are connected to each other through back-to-back electrostatic discharge (ESD)
protection diodes. These pins must be connected to each other on the application printed circuit board (PCB). It
is also recommended to connect the digital supply pin and the two analog supply pins together on the PCB. Both
low-voltage analog ground pins are also connected internally through back-to-back ESD protection diodes. These
ground pins should also be connected to the digital ground pin on the PCB. It is recommended to bypass the
low-voltage power supplies with a parallel combination of a 10-f and 100-nf capacitor. The PA block is biased
separately from a high-voltage, high-current supply.
Two PA power supply pins and two PA ground pins are available to provide a path for the high currents
associated with driving the low impedance of the ac mains. Connecting the two PA supply pins together is
recommended. It is also recommended to place a bypass capacitor of 47 F to 100 F in parellel with 100 nF as
close as possible to the AFE031. Care must be taken when routing the high current ground lines on the PCB to
avoid creating voltage drops in the PCB ground that may vary with changes in load current.
The AFE031 has many options to enable or disable the functional blocks to allow for flexible power-savings
modes. Table 17 shows the specific power supply that each functional block draws power from, as well as the
typical amount of power drawn from the associated power supplies for both the enabled and disabled states. For
additional information on power-supply requirements refer to Application Report SBOA130, Analog Front-End
Design for a Narrowband Power-Line Communications Modem Using the AFE031 (available for download at
www.ti.com).
Table 17. Power Consumption with Enable and Disable Times (Typical)
BLOCK
PA
Tx
Rx
ERx
ETx
DAC
ZC
REF1
REF2
DISABLE TIME
AVDD SUPPLY
CURRENT
DVDD SUPPLY
CURRENT
PA SUPPLY
CURRENT
10 s
61 mA
10 s
70 A
10 s
3.7 mA
10 s
1 A
On
10 s
5.3 mA
Off
10 s
1 A
On
10 s
900 A
Off
10 s
1 A
On
10 s
1.2 mA
Off
10 s
1 A
On
10 s
16 A
Off
10 s
1 A
On
10 s
25 A
Off
10 s
1 A
On
10 s
26 A
Off
10 s
8 A
On
10 s
25 A
Off
10 s
4 A
STATUS
ENABLE TIME
On
Off
On
Off
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AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
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PIN DESCRIPTIONS
DAC (Pin 7)
The DAC pin is used to configure the SPI to either read or write data to the Command and Data Registers, or to
write data to the DAC register. Setting the DAC pin high allows access to the DAC register. Setting the DAC pin
low allows access to the Command and Data Registers.
SD (Pin 8)
The Shutdown pin (SD) can be used to shut down the entire AFE031 for maximum power savings. When the SD
pin is low, normal operation of the AFE031 occurs. When the SD pin is high, all circuit blocks within the AFE031,
including the serial interface, are placed into the lowest-power operating modes. In this condition, the entire
AFE031 draws only 95 A of current. All register contents at the time the AFE031 is placed into shutdown mode
are saved; upon re-enabling the AFE031, the register contents retain the respective saved values.
INT Pin (9)
The Interrupt pin (INT) can be used to signal the microprocessor of an unusual operating condition that results
from an anomaly on the ac mains. The INTpin can be triggered by two external circuit conditions, depending
upon the Enable Register settings. The AFE031 can be programmed to issue an interrupt on these conditions:
Current Overload
Thermal Overload
Current Overload
The maximum output current allowed from the Power Amplifier can be programmed with the external RSET
resistor connected between PA_ISET (pin 46) and ground. If a fault condition should occur and cause an
overcurrent event for the PA, the PA goes into current limit and the I_FLAG bit (location 6 in the RESET
Register) is set to a '1' if the I_Flag_EN bit (location 6 in the Control2 Register) is enabled. This configuration
results in an interrupt signal at the INT pin. The I_FLAG bit remains set to '1' even after the device returns to
normal operation. The I_FLAG bit remains at '1' until it is reset by the microprocessor.
If the I_FLAG_EN bit (location 6 in the Control2 Register) is disabled and a current overload condition occurs, the
PA goes into current-limit mode to protect the AFE031; however, the contents of the I_FLAG bit (location 6 in the
RESET Register) remain at the respective previous values (presumably '0' for normal operation), and the
AFE031 does not issue an interrupt at the INT pin.
Thermal Overload
The AFE031 contains internal protection circuitry that automatically disables the PA output stage if the junction
temperature exceeds +150C. If a fault condition occurs that causes a thermal overload, and if the T_FLAG_EN
bit (location 5 in the Control2 Register) is enabled, the T_FLAG bit (location 5 in the RESET Register) is set to a
'1'. This configuration results in an interrupt signal at the INT pin. The AFE031 includes a thermal hysteresis and
allows the PA to resume normal operation when the junction temperature reduces to +135C. The T_FLAG bit
remains set to a '1' even after the device returns to normal operation. The T_FLAG bit remains '1' until it is reset
by the microprocessor.
If the T_FLAG_EN bit (location 5 in the Control2 Register) is disabled and a thermal overload condition occurs,
the PA continues to go into thermal limit and protect the AFE031, but the contents of the T_FLAG bit (location 5
in the RESET Register) remain at the previous value (presumably '0' for normal operation), and the AFE031 does
not issue an interrupt at the INT pin.
Once an interrupt is signaled (that is, INT goes low), the contents of the I_FLAG and T_FLAG bits can be read
by the microprocessor to determine the type of interrupt that occurred. Using the Control2 Register, each
interrupt type (current or thermal) can be individually enabled or disabled, allowing full user customization of the
INT function. For proper operation of the interrupt pin it is recommended to configure the interrupt enable
registers in the Control2 Register by writing to bit locations 5, 6, and 7 following the information in Table 18 after
each time the AFE031 is powered on. Failure to properly configure bit locations 5, 6, and 7 after power on may
result in unexpected interrupt signals.
40
AFE031
www.ti.com
Table 18 lists the register contents associated with each interrupt condition.
Table 18. Register Contents to Configure the Interrupt Pin
CONTROL2 REGISTER CONTENTS:
DETERMINE INTERRUPT PIN FUNCTIONALITY
I_FLAG_EN
(CURRENT
OVERLOAD)
T_FLAG_EN
(THERMAL
OVERLOAD)
FUNCTION
D7
D6
D5
undefined
No interrupt
0.1 mF
1
AFE031
V+
SCL
50 W
TSENSE
50 pF
D+
10 kW
(typ)
10 kW
(typ)
10 kW
(typ)
10 kW
(typ)
TMP411
SDA
DALERT/THERM2
THERM
SMBus
Controller
Over-Temperature
Fault
GND
5
41
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
www.ti.com
CALIBRATION MODES
The AFE031 can be configured for three different calibration modes: Tx Calibration, Rx Calibration, and Tx PGA
Calibration. Calibration values can be determined during the calibration process and stored in system memory. A
one-time calibration can be performed the first time that the system powers on; this calibration remains valid over
the full temperature range and operating life of the AFE031, independent of the number of power-on/power-off
cycles, as long as the calibration factors remain in the system memory. Calibration mode is accessed through the
Control1 Register. Note that calibration is not required.
Tx Calibration Mode
The Tx PGA + Tx Filter ac gain can be calibrated in Tx Calibration Mode. Figure 46 shows the signal path during
Tx Calibration mode.
C2000 MCU
AFE031
DAC
PGA
PA
LPF
SPI
SPI
PGA
PGA
LPF
AFE031
DAC
PGA
PA
LPF
SPI
SPI
PGA
PGA
LPF
42
AFE031
www.ti.com
AFE031
DAC
PGA
PA
LPF
SPI
SPI
PGA
PGA
LPF
BASIC CONFIGURATION
Figure 49 shows the AFE031 configured in a typical PLC analog front-end application. The schematic shows the
connections to the microprocessor and ac line. The values of the passive components in Figure 49 are suitable
for a single-phase powerline communications application in the CENELEC A band, connected to a 120-VAC or
240-VAC, 50-Hz or 60-Hz ac line.
43
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
www.ti.com
+15 V
C5
10 mF
C13
10 mF
3.3 V
R10
7.5 kW
R1
33 kW
C15
10 mF
C14
10 mF
C16
100 nF
L1
1 mH
R2
33 kW
D1
C6
10 mF
D2
+
N1
D3
GPIO
R12
4.7 W
C3
10 mF
Flexible PLC
Software Engine
R3
33 kW
38
SPI
Tx
Filter
Tx
PGA
12
23
22
C9
1 nF
C10
10 nF
Test
Point
23 kHz to
105 kHz
Fourth-Order
Passive
Passband
Filter
R13
150 W
25
C11
L4
10 nF 470 mH
C20
22 nF
R14
150 W
LPF
18
17
15
14
13
ADC IN
26
Rx
Filter
Rx
PGA2
C8
3.3 nF
C12
1 mF
28
L3
330 mH
27
LPF
C7
10 nF
C4
10 mF
Rx
PGA1
3.3 V
C2
24
11
3.3 V
LPF
Power
Amplifier
16
R5
10 kW
Rx
31
30
10
R4
10 kW
32
29
GPIO
Tx
21
GPIO
33
20
SPI
Two-Wire
Support
Circuitry
DAC
GPIO
C19
33 nF
34
DAC
Registers
19
SPI
Neutral
D4
TVS
35
SPI
Phase
+
N2
36
SPI
L2
15 mH
Zero
Crossing
C18
470 nF
C17
10 nF
37
40
39
41
43
42
44
46
3.3 V
45
R6 through R9
10 kW each
48
3.3 V
47
GPIO
TMS320F28x
1.5:1
See Note (2)
C1
R11
330 W
(1)
2.
C1:
CENELEC A: 680 pF
CENELEC B, C, D: 270 pF
C2:
CENELEC A: 680 pF
CENELEC B, C, D: 560 pF
44
AFE031
www.ti.com
LINE-COUPLING CIRCUIT
The line-coupling circuit is one of the most critical circuits in a powerline modem. The line-coupling circuit has
two primary functions: first, to block the low-frequency signal of the mains (commonly 50 Hz or 60 Hz) from
damaging the low-voltage modem circuitry; second, to couple the modem signal to and from the ac mains. A
typical line-coupling circuit is shown in Figure 50.
Power
Amplifier
Low-Voltage
Capacitor
High-Voltage
Capacitor
+
N1
Phase
+
N2
Neutral
CIRCUIT PROTECTION
Powerline communications are often located in operating environments that are harsh for electrical components
connected to the ac line. Noise or surges from electrical anomalies such as lightning, capacitor bank switching,
inductive switching, or other grid fault conditions can damage high-performance integrated circuits if they are not
properly protected. The AFE031 can survive even the harshest conditions if several recommendations are
followed.
First, dissipate as much of the electrical disturbance before it reaches the AFE031 with a multi-layer approach
using metal-oxide varistors (MOVs), transient voltage suppression diodes (TVSs), Schottky diodes, and a Zener
diode. Figure 51 shows the recommended strategy for transient overvoltage protection.
PA
Power Supply
AFE031
D1
D2
Low-Voltage
Capacitor
High-Voltage
Capacitor
Phase
+
N1
+
N2
MOV
D3
Power
Amplifier
Neutral
TVS
45
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
www.ti.com
DESCRIPTION
MANUFACTURER
D1
Zener diode
Diodes, Inc.
1SMB59xxB (1)
D2, D3
Schottky diode
Diodes, Inc.
1N5819HW
TVS
Diodec Semiconductor
P6SMBJxxC (2)
MOV
Varistor
LittleFuse
TMOV20RP140E
HV Cap
High-voltage capacitor
474MKP275KA (3)
COMPONENT
DESCRIPTION
MANUFACTURER
D1
Zener diode
Diodes, Inc.
1SMB59xxB (1)
240 VAC, 50 Hz
(1)
(2)
(3)
D2, D3
Schottky diode
Diodes, Inc.
1N5819HW
TVS
Diodec Semiconductor
P6SMBJxxC (2)
MOV
Varistor
LittleFuse
TMOV20RP300E
HV Cap
High-voltage capacitor
474MKP275KA (3)
Select the Zener breakdown voltage at the lowest available rating beyond the normal power-supply operating range.
Select the TVS breakdown voltage at or slightly greater than (0.5 PA_VS).
A common value for the high-voltage capacitor is 470 nF. Other values may be substituted depending on the requirements of the
application. Note that when making a substitution, it is important in terms of reliability that the capacitor be selected from the same
familiy or equivalent family of capacitors rated to withstand high-voltage surges.
THERMAL CONSIDERATIONS
In a typical powerline communications application, the AFE031 dissipates 2 W of power when transmitting into
the low impedance of the ac line. This amount of power dissipation can increase the junction temperature, which
in turn can lead to a thermal overload that results in signal transmission interruptions if the proper thermal design
of the PCB has not been performed. Proper management of heat flow from the AFE031 as well as good PCB
design and construction are required to ensure proper device temperature, maximize performance, and extend
device operating life.
The AFE031 is assembled into a 7-mm2 x 7-mm2, 48-lead, QFN package. As Figure 52 shows, this QFN
package has a large area exposed thermal pad on the underside that is used to conduct heat away from the
AFE031 and into the underlying PCB.
Figure 52. QFN Package with Large Area Exposed Thermal Pad
Some heat is conducted from the silicon die surface through the plastic packaging material and is transferred into
the ambient environment. Because plastic is a relatively poor conductor of heat, however, this route is not the
primary thermal path for heat flow. Heat also flows across the silicon die surface to the bond pads, through the
wire bonds, into the package leads, and finally into the top layer of the PCB. While both of these paths for heat
flow are important, the majority (nearly 80%) of the heat flows downward, through the silicon die, into the
thermally-conductive die attach epoxy, and into the exposed thermal pad on the underside of the package (see
Figure 53). Minimizing the thermal resistance of this downward path to the ambient environment maximizes the
life and performance of the device.
46
AFE031
www.ti.com
Less than 1%
~20%
~20%
~80%
AFE031
47
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
www.ti.com
Increasing the number of layers in the PCB, using thicker copper, and increasing the PCB area are all factors
that improve the spread of heat. Figure 55 through Figure 57, respectively, show thermal resistance performance
as a function of each of these factors.
THERMAL RESISTANCE vs NUMBER OF PCB LAYERS
36
2
PCB Area = 3 in , 2 oz Cu
(Results are from thermal
simulations)
34
32
30
28
26
24
22
20
1
Number of Layers
Figure 55. Thermal Resistance as a Function of the Number of Layers in the PCB
THERMAL RESISTANCE vs BOARD AREA
28
Four-Layer PCB, 2 oz Cu
(Results are from thermal
simulations)
26
24
22
20
18
16
14
12
10
2
10
12
14
33
31
29
27
25
23
21
19
17
15
0.5
1.5
2.5
Cu Thickness (oz)
48
AFE031
www.ti.com
For additional information on thermal PCB design using exposed thermal pad packages, refer to Application
Report SBOA130, Analog Front-End Design for a Narrowband Power-Line Communications Modem Using the
AFE031 and Application Report SLMA002E, PowerPAD Thermally-Enhanced Package (both available for
download at www.ti.com).
PACKAGING/MECHANICALS
Complete mechanical drawings and packaging information are appended to the end of this data sheet.
49
AFE031
SBOS531D AUGUST 2010 REVISED MAY 2012
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2012) to Revision D
Page
Page
Changed transmit power amplifier operating range description in Description section ........................................................ 1
Added cross-reference to footnote 2 to Output short-circuit parameter in Absolute Maximum Ratings table ..................... 2
Changed Frequency Response, Passband frequency (B/C/D Modes) parameter minimum and typical specifications
in Electrical Characteristics: Receiver (Rx) ........................................................................................................................... 6
Deleted Digital Outputs (INT, Tx_Flag, Rx_Flag), INT pin high, INT pin low, Tx_Flag high, Tx_Flag low, Rx_Flag
high, and Rx_Flag low parameter units from Electrical Characteristics: Digital ................................................................... 8
Changed Digital Outputs (INT, Tx_Flag, Rx_Flag), Tx_Flag high, Tx_Flag low, Rx_Flag high, and Rx_Flag low
parameter specification descriptions in Electrical Characteristics: Digital ............................................................................ 8
Changed Operating Supply Range, Power amplifier supply voltage parameter maximum specification in Electrical
Characteristics: Power Supply ............................................................................................................................................ 10
50
www.ti.com
30-Jul-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
AFE031AIRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
AFE031AI
AFE031AIRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
AFE031AI
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
www.ti.com
30-Jul-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
25-Mar-2015
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
AFE031AIRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
AFE031AIRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
25-Mar-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AFE031AIRGZR
VQFN
RGZ
48
2500
367.0
367.0
38.0
AFE031AIRGZT
VQFN
RGZ
48
250
210.0
185.0
35.0
Pack Materials-Page 2
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