chapter

S ERIAL , IR S ERIAL , P ARALLEL ,

AND USB I NTERFACES
National Semiconductors PC97338 is used for several I/O functions. The 97338
incorporates a Diskette Controller (FDC), one fully functional 16550 UART, a second
UART which can be used for IrDA, and an enhanced parallel port, in one 100 pin
TQFP package.
The 97338 has power down modes used during Static Suspend and On (doze and sleep)
states to reduce power consumption. The 97338 also offers full plug and play support.

Serial Port Interface

The serial port controller supports two independent serial port devices and is software
compatible to the 16550 and 16450 UARTs. The controller contains two on-chip
programmable baud rate generators in which an external 14Mhz clock is divided by 13
for 1.8462 MHz, sent to each baud rate generator, and used for both receiving and
transmitting serial data.
Serial-to-parallel conversion is performed on received data and parallel-to-serial
conversion is performed on transmitted data. Status of either or both of the UARTs is
available at any time. To access it, the I/O controller must read the appropriate status
register in the controller. The current state and type of transfer is contained in this
status information, along with details regarding any errors that were encountered. The
conditions under which the CPU is interrupted and the interrupt line to be used are
programmable.
A standard 9-pin male D-subminiature connector is provided for external connection.

Serial, IR Serial, Parallel, and USB Interfaces 6-1

Parallel Port Interface

The I/O controllers parallel port supports four modes of operation: the unidirectional
ISA standard, the fully bi-directional PS/2 standard, Enhanced Parallel Port (EPP)
mode, and Extended Capabilities Port (ECP). The chip is capable of driving the
interface directly with no external buffers.
In the PS/2 bi-directional mode, data is read and written through the full 8-bit data port.
Configuring the I/O controller for PS/2 parallel port mode enters this mode. For more
information on this process, refer to the National Semiconductor PC97338 design
guide.
The high speed, fully bi-directional, EPP mode was designed to improve performance
on devices communicating through the parallel port such as network adapters and
storage devices. Previously, the software drivers for these devices had to send one byte
at a time due to the need to manually generate the strobe output and poll the busy input.
This mode allows auto-generation of either an address or data strobe and allows the
slave device to automatically extend the write or read cycle by controlling the I/O
Channel Ready (IOCHRDY) signal. All of this is done without sacrificing AT or PS/2
compatibility. For more information on this process, refer to the PC97338 design guide.
The ECP mode is a further design improvement of the EPP mode which provides a 16
byte FIFO that can be configured for either direction, command/data, threshold
interrupts for both directions, FIFO status (empty/full), and automatic generation of
strobes to fill/empty the FIFO and to transfer data. For more information on this
process, refer to the PC97338 design guide.

IrDA
The computer provides support for Standard Infrared (SIR) at 115Kbps, and Fast
Infrared (FIR) at 4Mbps. From the SIO, this is a two-wire interface: TX and RX. These
signals are connected to a TFDS6000/6500 IrDA transceiver module that consists of
the transmit and receive LEDs and the amplifier circuit required. The module has a
power down input pin that is connected to the IRPWRDOWN signal from the SIO.
This signal is also used to program the module for 115Kbps or 4Mbps.

6-2 Serial, IR Serial, Parallel, and USB Interfaces