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Learning Objectives
Given the design, library and script files, your task will be to
successfully perform STA using the PrimeTime GUI and
generate reports.
After completing this lab, you should be able to:
Add index(es) to ease searching of information in SOLD
Invoke PrimeTime GUI and perform 4 STA steps:
READ, CONSTRAIN, CHECK and ANALYZE
Analyze the designs timing using the 4 GUI windows:
Histogram, Path profiler, Schematic viewer and
Waveform viewer
Generate and interpret timing and constraint reports
Report cell and net delay calculations
60 minutes
UNIT
Unit 1
1-1
Lab 1
Getting Started
Directory structure and relevant files
../Libs/
core_slow.db
Lab1_Intro/
.synopsys_pt.setup
PrimeTime Setup
Scripts/
Scripts directory
1_read_design.pt
2_constrain_design.pt
3_check_design.pt
4_timing_analysis.pt
Source/
Verilog/
RISC_CORE*.v
Reports/
Reports directory
$SYNOPSYS/
doc/online/static
index.pdx
1-2
Lab 1
Introduction to STA using PrimeTime
Add Search index(es) to SOLD
ANALYZE Graphically
Generate STA reports for analyzing the Timing, Design Rules and
Net and Cell delays
1-3
Lab 1
Background
You are provided with the gate level netlist of a design, library, a setup file, a
set of script files and the online documentation (SOLD)
The Unix directory for this entire lab is ./Lab1_Intro.
Answers to the Questions are located at the end of this lab for
comparison J
1-4
Lab 1
2. Opening SOLD
Unix> acroread top.pdf
1-5
Lab 1
Click on PrimeTime, the following window will appear.
1-6
Lab 1
4. Search using Index window:
Click on the Index in the left side window (see picture above). You
will see the window below:
Scroll down the Index window (right side window), look for clock, then look
for transition time.
5. Search using key word:
You need to make sure you have the proper index installed to do searches.
To install the index, click on:
Edit --> Search --> Select Indexes
1-7
Lab 1
Edit --> Search --> Select Indexes opens a Index Selection window:
6. Click on Add
The Add Index window will appear:
1-8
Lab 1
An Index Selection window opens
If the box to the left of an index is pushed in, the index is enabled. The
boxes not pushed in are disabled. Click the box to toggle between enable
and disable. The search will be done using the indices that are enabled.
8. Search using key word:
Click
Edit Search Query
Type timing reports in the search window, then click Search.
1-9
Lab 1
The Search Results window will appear.
1-10
Lab 1
Task 2. Invoke PrimeTime GUI and Verify Setup
1. Invoke PrimeTime from the Lab1_Intro directory.
unix% cd Lab1_Intro
unix% primetime &
It will take a few moments for the GUI to show up. Familiarize yourself with
the following key areas of the GUI:
q
2. From the GUI pull down menu, verify that the Search and Link paths are
consistent with that of the .synopsys_pt.setup file. Click OK once done.
1-11
Lab 1
Task 3. READ, CONSTRAIN and CHECK
1. Read the Verilog design netlist using the script provided.
GUI: File -> Run Script
Run Script: Browse ..
Run Script File: Scripts 1_read_design.pt Open
Run Script: Select Echo Command and Verbose OK
4. Verify that you sufficiently constrained the design using the clock period
alone. Do this step using the command line interface:
pt_shell> check_timing -verbose
1-12
Lab 1
Task 4. Analyze the design using GUI
1. Analyze the design timing using the Endpoint slack Histogram.
(Search for Endpoint Slack Histogram in SOLD)
GUI: Reports -> Histograms -> End Point Slack
Endpoint Slack: OK
(accept the defaults)
Question 12. What is the largest amount of Negative slack in the design?..............
(Hint: Look at the Top most Endpoint on the Right Hand window)
Question 13. Does the above agree with the Scoreboard reading? ..........................
2. Display the Path Profiler. (To invoke Path profiler, you need to start with the
Histogram)
Histogram: Click on the Worst violating endpoint
Histogram: Window -> Create Path Profiler
Question 14. How many higher level modules (partitions) does the Timing
path pass through? .............................................................................
Question 15. Which module in the path causes the maximum delay? ....................
Question 16. How many library leaf cells are present in each module?...................
(Double Click Module Use Up arrow icon to go back)
Question 17. In I_ALU, which library leaf cell causes the largest percentage
of delay?.............................................................................................
1-13
Lab 1
3. Display the Schematic Window (You can invoke it from the Histogram or the
Path Profiler).
Histogram: Click on the Worst violating endpoint
Histogram: Window -> Create Schematic Viewer
Question 18. What is the Start point of the timing path (input port or register)?.........
(HINT: Simply place the mouse at the start point and look for an yellow info tip box)
Question 19. What is the End point of the timing path (output port or register)?....
(HINT: If you do not see an yellow info tip box, then look at the lower left
corner for the end point name)
Question 20. How many combinational library cells (do not count any
registers) are present on the timing path? ..........................................
4. Display the Waveform Window (you can invoke it from the Histogram or the
Path Profiler).
Histogram: Click on the Worst violating endpoint
Histogram: Window -> Create Waveform Viewer
1-14
Lab 1
Task 5. Generate Reports
1. Generate the Setup timing report from the command prompt:
pt_shell> report_timing
Question 37. What 2 design rules are checked in the library? .................................
1-15
Lab 1
4. Generate reports to explain the delay calculations of cell and net delays.
To generate the report, you need to know the start and end points of
cells and nets. Note: the net delays are very small, you need at least 4
significant digits to see non zero net delays.
pt_shell> report_timing input_pins significant 4
Question 38. Why is every library cell name on this path shown twice?.................
Question 39. What is the longest cell delay on this path? ........................................
5. Choose the CLK to Q cell delay arc and report its delay calculation:
HINT: To copy text from the Console into the command prompt, select the
text using left mouse click; to paste into the command prompt, use the right
mouse click and then select Paste with a left mouse click. Its more easily
done, than said J
pt_shell> report_delay_calculation from \
I_DATA_PATH/Oprnd_B_reg[3]/CLK to \
I_DATA_PATH/Oprnd_B_reg[3]/Q
Question 40. What are the CLK2Q delays for rise and fall?....................................
Question 41. What are the rise and fall output transitions of this register?..............
6. Choose the net that ends at the D0 pin of the register (end point):
pt_shell> report_delay_calculation from \
I_ALU/U537/Y to \
I_ALU/Zro_Flag_reg/D0
Question 42. What is the net delay during rise or fall? ............................................
1-16
Lab 1
Task 6. Quit Primetime
1. Exit PrimeTime GUI
GUI: File -> Exit
PrimeTime: OK (for Exit PrimeTime?)
CONGRATULATIONS! Give yourself a pat on the back. You have just conducted
STA on the RISC_CORE design using PrimeTime.
1-17
Lab 1
Q 2.
Q 4.
Q 5.
Q 6.
Q 7.
Q 8.
1-18
Lab 1
Task 4. Analyze the design using GUI
Q 9.
Q 10. Where do you find worst slack, to the left or right most side of the X
axis?
Left
Q 11. How many endpoints are contained in the worst violating bin?
127
Q 12. What is the largest amount of Negative slack in the design?
1.291897
Q 13. Does the above agree with the Scoreboard reading?
Yes
Q 14. How many higher-level modules (partitions) does the Timing path
pass through?
2 (DATA_PATH, ALU)
Q 15. Which module in the path causes the maximum delay?
ALU (82%)
Q 16. How many library leaf cells are present in each module? (Double Click
Module Use Up arrow icon to go back)
1 in I_DATA_PATH, 13 in I_ALU
Q 17. In I_ALU, which library leaf cell causes the largest percentage of
delay?
and6a6, 12.32%
Q 18. What is the Start point of the timing path (input port or register)?
Register Oprnd_B_reg[3] (fdesf1a9)
1-19
Lab 1
Q 19. What is the End point of the timing path (output port or register)?
(NOTE: If you do not see an yellow info tip box, then look at the
lower left corner for the end point name)
Register Zro_Flag_reg (fdesf1a9)
Q 20. How many combinational library cells (do not count any registers) are
present on the timing path?
13
Q 21. How many waveforms are displayed?
2 (Data arrival time and Data required time)
Q 22. Do the start and end points agree with that of Schematic viewer?
Yes
Q 23. What is the path delay?
3.4 ns
Q 24. What is the slack?
1.3 ns
Q 25. What is Registers setup time requirement?
0.4 ns
Q 26. Is there a timing violation?
Yes, -1.3 ns
1-20
Lab 1
Q 29. What is the Clock period?
2.50 ns
Q 30. What is the slack? Was it MET or VIOLATED?
1.29 ns (VIOLATED)
Q 31. What is the register CLK to Q delay?
0.62 ns
Q 32. What is the library setup time?
0.36 ns
Q 33. What is the Data arrival time?
0.22 ns
Q 34. What is the Data required time?
0.11 ns
Q 35. What is the slack? Was it MET or VIOLATED?
0.11 ns (MET)
Q 36. What is the library hold time?
0.11 ns
Q 37. What 2 design rules are checked in the library?
max_capacitance and max_transition
Q 38. Why is every library cell name on this path shown twice?
Once to show the input pin of the cell, another to show the output pin
of the cell
Q 39. What is the longest cell delay on this path?
CLK to Q
1-21
Lab 1
Q 40. What are the CLK2Q delays for rise and fall?
0.617072ns , 0.536889 ns
Q 41. What are the rise and fall output transitions of this register?
0.319435 ns, 0.18629 ns
Q 42. What is the net delay during rise or fall?
9.02512e-05 ns
1-22