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Wise Guys
Students of
Electronics Engineering
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Laboratory 1 EEPROM
Semiconductor Memories
Memory Arrays
Memory Arrays
Dynamic
RAM
Static
RAM
Flash
EEPROM
Memory Arrays
Latches
Flip-flops
Registers
Register bank
Very small
capacity
Memory Arrays
RAM
SRAM
DRAM
ROM
EPROM
EEPROM flash
Very high
capacity
DRAM
EEPROM
Flash
Processor
Fast
static
Dynamic
RAM
Disk
CACHE
Main
memory
Secondary
storage
CACHE
SRAM
DRAM
1. Anatomy of a Computer
Block diagram view: memory system
address
Processor
read/write
data
1
VA
Processor
Memory
System
MMU
PA
PA
Main
Mem
Cache
D or I
D or I
1. Anatomy of a Computer
Block diagram view: memory system
address
Processor
read/write
data
1
VA
Processor
MMU
PA
PA
Main
Mem
Cache
secundaria
Cache
primaria
Memory
System
D or I
D or I
1. Memory Hierarchy
Various memory
devices are used in a
computer system
They have different
speeds and costs
Processor
Registers
10 ns
On Chip
Cache
10 ns
20 ns
60 ns
100 ns
10
12 ms
1,200
Local
Memory
DRAM
HDD
Slower
Access
Secondary
Cache
Global
Memory
Mass
Storage
Higher
Cost
Higher
Density
1. Memory Hierarchy
Want inexpensive, fast memory
Main memory
Large,
inexpensive,
slow
memory stores entire program
and data
Cache
Small, expensive, fast memory
stores copy of likely accessed
parts of larger memory
Can be multiple levels of cache
Processor
Registers
Cache
Main memory
Disk
Tape
1. Memory Arrays
Memory Arrays
Read/Write Memory
(RAM)
(Volatile)
Static RAM
(SRAM)
Mask ROM
Erasable
Programmable
ROM
(EPROM)
Queues
Shift Registers
Serial In
Parallel Out
(SIPO)
Dynamic RAM
(DRAM)
Programmable
ROM
(PROM)
Parallel In
Serial Out
(PISO)
Electrically
Erasable
Programmable
ROM
(EEPROM)
First In
First Out
(FIFO)
Flash
EEPROM
Last In
First Out
(LIFO)
1. Memory types
Memory Types
Features
FLASH
ROM
Read-Only Memory
SRAM
Static Random-Access Memory
EPROM
Electrically Programmable ReadOnly Memory
DRAM
Dynamic Random Access Memory
EPROM
EEPROM
Updatable
Nonvolatile
FLASH
DRAM
High
Density
ROM
Memory access
r/w: selects read or write
enable: read or write only when asserted
multiport: multiple accesses to different locations simultaneously
A10 11 2K
A20 21 2M
A1 2 4
A11 12 4K
A21 22 4M
A2 3 8
A12 13 8K
A22 23 8M
A3 4 16
A13 14 16K
A23 24 16M
A4 5 32
A14 15 32K
A24 25 32M
A5 6 64
A15 16 64K
A25 26 64M
A6 7 128
A16 17 128K
A26 27 128M
A7 8 256
A17 18 256K
A27 28 256M
A8 9 512
A18 19 512K
A28 29 512M
2
22
=2
=4
23
=8
24
2
2
2
2
2
2
5
6
7
8
9
10
11
= 16
2
12
2
13
2
14
2
= 2048
= 4096
= 8192
= 16384
= 32
= 32768
= 64
= 128
= 256
= 512
= 1024
2
2
2
2
2
15
16
17
18
20
30
40
= 65536
= 131072
= 262144
= 1 X106
= 1 X109
= 1 X1015
m n memory
m words
r/w
enable
2k n
A0
Ak-1
Dn-1
D0
1. Memory Architecture
word-lines
bit-line conditioning
bit-lines
row decoder
memory cells:
2 n-k rows x
2 m+k columns
n-k
k
column
circuitry
n
column
decoder
2 m bits
1. Array Architecture
2n words of 2m bits each
If n >> m, fold by 2k into fewer rows of more columns
Good regularity easy to design
Very high density if good cells are used
2. ROM Types
EEPROM: E2PROM and FLASH E2PROM
charge on a floating gate
erased by electrical signal
(UV) EPROM
charge on a floating gate
erased by UV light
OTP PROM
fusible nichrome/polysilicon links
programmed by blowing fuses
ROM
mask-programmed
Emulated ROM NVRAM RAM-with-a-battery
A0
Address
A1
ROM
8 words x 5 bits
A2
D4 D3 D2 D1 D0
Data
3 Inputs
ROM
8 words x 5 bits
F4 F 3 F2 F1 F0
5 Outputs
16
A0 A15
ROM
32K x 8 bits
OE
CS
D7 D0
A0
D0
ROM
An-1
Dn-1
CS
OE
DIRECCIN
PALABRA DE DATOS
MEMORIA
A2
A1
A0
D3
D2
D1
D0
M0
M1
M2
M3
M4
M5
M6
M7
f3=
m ( 2 ,3 ,5 )
m (1,3 ,5 , 6 )
CODIFICADOR
M7
D3
D2
D1
D0
CS
A0
A1
A2
38
decoder
word line
data line
programmable
connection
wired-OR
D3 D2 D1 D0
m ( 2 ,3 ,5 )
m (1 , 3 , 5 , 6 )
A0-A2
DECODIFICADOR
FILA
ARREGLO
8x8
D7 D0
A3 A7
A 8 A12
ADDRESS
BUFFERS
ADDRESS
BUFFERS
5
5
COLUMN
DECODER DRIVER
2 5 = 32
256 x 32
1st LEVEL
ROW
SELECT
2st
2 8 = 256
LEVEL
ARRAY OF 8
ROW
BIT WORDS
SELECT
CS
1
CHIP SELECT
OUTPUT BUFFERS
D7 D0
floating gate
source
(a)
drain
drain
(b)
5-30 min
(c)
(d)
source
drain
ADDRESS
INPUTS:
A0-A10
DATA OUTPUTS: D7 D0
OUTPUT ENABLE
CHIP ENABLE
AND PROG LOGIC
OUTPUT
BUFFERS
Y
DECODER
Y GATING
X
DECODER
16, 384-BIT
CELL MATRIX
A6-12
Row
Address
Latches
Row
Address
Decoder
A0-5
Column
Address
Latches
Column
Address
Decoder
CE
WE
Edge
Detect &
Latches
E2
Memory Array
64 Byte
Page
Buffer
Timer
Latch Enable
OE
Control
Latch
I/O Buffer/
Data Polling
Control
Logic
PE RSTB CLK
VW
I/O7-0
ONO
floating gate
Tunnel oxide
Bitline
Drain
N+
Source
N+
P-Substrate
AS
WL 1
Q3
Q1
Q2
ES
WL 2
Q1 MEMORY TRANSISTOR
Q2 PASS GATE (EACH 16 COLUMNS)
Q3 SECTOR SELECT (EACH 16 ROWS)
EVERY 16 ROWS 2K BYTES 1 SECTOR
1FFFFFH
FlashFile Memory
0H
Intel StrataFlash
Memory
0H
8x8 Kbyte
64 Kbyte
128 Kbyte
64 Kbyte
64 Kbyte
128 Kbyte
64 Kbyte
128 Kbyte
Symmetrically
Blocked
32 Mbit
128 Kbyte
64 Kbyte
Asymmetricall
y Blocked
32 Mbit
1FFFFFH
128 Kbyte
128 Kbyte
128 Kbyte
1FFFFFH
128 Kbyte
Symmetrically
Blocked
128 Mbit
Pins
17bits address (128k) + 8 data = 25 + control
16
A0 A15
R/W
OE
CS
SRAM
32K x 8 bits
D7 D0
bit
bit
bit
bit
A0 A6
R
O
W
S
E
L
E
C
T
128 x 128
CELL
ARRAY
Data I /O
CS
W
W = 1: READ
W = 0; WRITE
COLUMN SELECT
DI: DATA IN
DO: DATA OUT
A7 A13
A0
A10
I/O0
I/O7
CS
OE
WE
ADDRESS
DECODER
INPUT
DATA
CIRCUIT
CONTROL
CIRCUIT
128 X 128
MEMORY
ARRAY
I/O CONTROL
Vcc
GND
Refresh
DRAM has one-transistor cells
Charge leaks from storage capacitor
Refresh interval ~ 1-4 ms
RAM unavailable during refresh!
Some bandwidth loss
bit
word
C
Vdd
d
e
c
o
d
e
r
row
address
data
Column
Address
Column Decoder
A0A10
Memory Array
(2,048 x 2,048)
Word Line
Storage
Cell
Data I/O
...
...
...
...
...
...
Row
driver
...
Sense
Amplifier
Sense
Amplifier
...
RAS
CAS
W/R
word line
Row
driver
Address buffer
address
Row
driver
Sense
Amplifier
Data I/O
precharge BL
decode row
discharge BL
sense amp
column select
data > out
---
row col
row
---
(a) random
access
mode
---
data
Random access time
Column address cycle time
RAS
CAS
address
Data out
---
row c1
--d1
c2
--d2
c3
--d3
(b) page
mode
RAS
CAS
address --Data out
c1
c2
d1 d2
c3
d3
c4
d4
c5
c6
d5
c7
d6
d7
9 10 11 12 13 14 15
clk
cmnd
bank
addr
data
ACT
READ READ
ROW
COL COL
PRE
da1
db1
db2
db3
ACT
READ
ROW
COL
db4
dc1
Hi-Z
CAS latency
1/2/3 for 33/66/99 MHz
Burst length =
1/2/4/8/full page
9 10 11 12 13 14 15
clk
cmnd
ACT
WRIT WRIT
bank
addr
data
ROW
COL
COL
da1
db1
PRE
db2
db3
db4
ACT
WRIT
ROW
COL
dc1
Hi-Z
Final goal = 1 access each clock cycle
banking
burst length large enough (e.g. 8)
dc2
dc3
9 10 11 12 13 14 15
clk
cmnd
bank
addr
data
ACT
ROW
READ READ
COL
PRE
COL
da1
db1
CAS latency
db2
db3
db4
ACT
READ
ROW
COL
db5
db6
db7
db8 dc1
9 10 11 12 13 14 15
clk
cmnd
bank
addr
data
ACT
ROW
READ READ
COL
COL
da1
db1 db2
PRE
db3 db4
db5 db6
ACT
READ
ROW
COL
db7 db8
dc1
dc2 dc3
13
Row
address
Column
address
Control
13
Address
1 or 4
DRAM
Data
RAS
R/W
SENSE WRITE
AMPLIFIERS
8
2 = 256
8
ROW
ADDRESS
LBS LATCH
REFRESH
CIRCUITRY
CONTROL
256 x 256
ROW
DECODER
ARRAY OF
4 BITS
WORDS
R / W READ/WRITE
DI DATA IN
DO DATA OUT
STEP 1
A0-7
A8-15
CS CHIP SELECT
STEP 2
8
2 = 256
MBS COLUMN
ADDRESS
LATCH
COLUMN DECODER
CAS
D I/O 0-3
86
1 Mb
4 MB
8 MB
16 MB
32
DRAM Generation
89
92
96
99
02
4 Mb 16 Mb 64 Mb 256 Mb 1 Gb
8
16
4
8
32 MB
64 MB
128 MB
256 MB
4. Memory Arrays:
column
row
Bank A
Bank B
15 ------------------8 7 ------------------------0
LSB
13
A 12A0
A13
MSB
A 14
D 70
CS
3 BIT
DECODER
A15
D 70
CS
8Kbyte
D 70
CS
D 70
CS
ROM 64Kx8
D 70
CS
D 70
CS
D 70
CS
D 70
CS
D
A
T
A
L
I
N
E
S
R/W
A0
A1
BIT6
BIT7
BIT0
14 BIT
ADDR
A2
A13
16 BIT
ADDRESS
A14
A15
2 BIT
DECODER
SRAM 64Kx8
usando SRAMs 16Kx1
cs
cs
cs
cs
cs
cs
DI 7 DO7
DI 6 DO6
DI 0 DO0
E2
E1
Organizacin 1-D
de una memoria de
64Kbyte usando
SRAMs de 8Kx8
D (7 : 0)
W
OE
A (12: 0)
E2
E1
D (7 : 0)
W
OE
A (12: 0)
E2
E1
D (7 : 0)
W
OE
A (12: 0)
DECODER
`138
G1
Y6
G2 A
Y5
G2 B
ADDR (15:13)
15
14
13
Y7
Y3
E2
E1
W
Y2
OE
A (12: 0)
Y4
SEL C
SEL B
SEL A
E2
E1
W
D (7 : 0)
OE
A (12: 0)
Y1
Y0
E2
E1
W
DATA (7:0)
D (7 : 0)
D (7 : 0)
OE
A (12: 0)
ADDR (12:0)
WRITE
READ
E2
E1
W
D (7 : 0)
OE
A (12: 0)
E2
E1
W
OE
A (12: 0)
D (7 : 0)
ADDR(16)
ADDR (15)
A
Organizacin 2-D
de una memoria de
64Kbyte usando
SRAMs de 8Kx8
139
DECODER
Y 0 Y1 Y 2 Y 3
EN 3
E2
E1
W
OE
A(12 : 0)
EN 2
G
ADDR (14)
ADDR (13)
E2
E1
W
OE
D(7 : 0)
E2
E1
W
OE
139 Y 3
EN 3
D(7 : 0)
A(12 : 0)
EN 2
D(7 : 0)
E2
E1
W
OE
A(12 : 0)
D(7 : 0)
A(12 : 0)
Y2
Y1
EN 1
E2
E1
W
OE
Y0
EN1
D(7 : 0)
W
OE
A(12 : 0)
DECODER
EN 0
A(12 : 0)
D(7 : 0)
A(12 : 0)
E2
E1
W
OE
E2
E1
EN 0
D(7 : 0)
E2
E1
W
OE
A(12 : 0)
D(7 : 0)
WRITE
READ
ADDR (12 : 0)
DATA (7: 0)
Organizacin de
una memoria
1Mx8 usando
DRAMs de
64Kx4
COL 0
COL 1
COL 2
64K x 8
64K x 8
64K x 8
COL 3
CS
RAS 0
ROW 0
ROW 1
RAS 1
RAS 2
2 64 K 4
ROW 2
DRC
ADOUT 0 - 7
RAS 3
WE
CAS
CAS
CAS
CAS
A 07 A 06
WE
ROW 3
CAS
0
1
2
3
CS CHIP SELECT
RAS ROW ADDRESS STROBE
DI/O
8
DI/O
8
DO
8
DO
8
Word-line
VDD
VDD
VDD
a) DRAM cell
....
a) ROM cell
b) EEPROM cell
permanence
Storage
Life of
product
Tens of
years
Battery
life (10
years)
Ideal memory
EPROM EEPROM
FLASH
NVRAM
Nonvolatile
In-system
programmable
SRAM/DRAM
Near
zero
Write ability
During
fabrication
only
External
programmer,
one time only
External
External
External
programmer, programmer
programmer
1,000s
OR in-system, OR in-system,
1,000s
block-oriented
of cycles
writes, 1,000s
of cycles
of cycles
In-system, fast
writes,
unlimited
cycles
6. Memory Hierarchy
Various memory
devices are used in a
computer system
They have different
speeds and costs
Processor
Registers
10 ns
On Chip
Cache
10 ns
20 ns
60 ns
100 ns
10
12 ms
1,200
Local
Memory
DRAM
HDD
Slower
Access
Secondary
Cache
Global
Memory
Mass
Storage
Higher
Cost
Higher
Density
6. Cache Memory
Two main problems:
mismatch in speed between processor and main memory
contention for contents of shared memory, or for
switching, significantly increases latency
Answer: Use a cache
6. What is a Cache?
High-speed memory module connected to a processor for its
private use
Contains copies of actively referenced material
Copied between cache & memory in lines or blocks
Caching works because of
temporal locality - repeated references to same memory in a small
time
spatial locality - references to nearby memory addresses in a small
time
/CAS
AD0-12
Row
Add
Column
Add
(a) random
access
mode
WRITE
/OE
DATA (out)
DATA (in)
tRAC
tRC
Row
Add
Column
Add
Column
Add
Column
Add
WRITE
/OE
Valid
Data
DATA (out)
DATA (in)
tRAC
tRC
Valid
Data
Valid
Data
Row
Add
Column
Add
Column
Add
Column
Add
WRITE
/OE
Valid
Data
DATA (out)
DATA (in)
tRAC
tRC
Valid
Data
Valid
Data
5. Dynamic RAM
Refresh
DRAM has one-transistor cells
Charge leaks from
storage capacitor
Refresh interval ~ 1-4 ms
RAM unavailable during refresh!
Some bandwidth loss
bit
word
C
Vdd
Bit-lines
VDD Word-line
a) CMOS cell
VDD
b) RMOS cell
VDD
VDD
d) DRAM cell
VDD
f) ROM cell
e) DRAM self-refresh cell
VDD
....
g) EEPROM cell
h) NOVRAM cell