SWNT SPICE Model

The drain current (IDS) is modeled as:

IDS = IPFET + IAmbipolar + IMetallic
1. PFET current is modeled using square law model.
a) Cut-off Region (|VGS| < |VT|):
I PFET 0
b) Linear Region (|VDS| < |VGS|-|VT|):
V
W

I PFET K p 1 VDS VGS VT DS *VDS

L
2

c) Saturation Region (|VDS| > |VGS|-|VT|):

2
VGS VT

W
I PFET K p 1 VDS
L
2
2. Ambipolar current is modeled as a voltage (VGS and VDS) dependent exponential
current source. The exponential term is expressed in terms of Taylors series and first
three terms are incorporated in the SPICE model.

V2
I ambipolar K n VGS VG 0 1 Vx x L
2

Where, Vx Vthershold VGS VDS

3. Metallic tube current component is modeled as resistor connected between the drain
and the source terminal.
W
I Metallic Metallic *VDS
L
The metallic tube component will scale linearly with the width of the device. Also the
probability of finding a metallic tube would reduce as the channel length is increased.
Hence term (W/L) is used in the above expression
4. Source-Drain resistance: The effect of RS and RD is also taken into account such that
The Drain current is sum of 1-3

I DS I PFET I ambipolar I Metallic

Comment #4: I agree that a reliable SPICE model is a critical component of an

advanced integrated circuit technology, and I am excited to see that the authors have
implemented such a model for their carbon nanotube network transistors. I believe that
the most important test for the new model is whether it correctly predicts the significant
increase in off-state drain current with increasing drain-source voltage and with
decreasing channel length. In other words, does the model correctly predict that the offstate drain current of transistors with a channel length of 100 m measured at VDS = -2
V is three orders of magnitude larger than at VDS = -0.2 V (100 nA versus 100 pA), and
that the off-state drain current of transistors with a channel length of 10 m is four
orders of magnitude larger than of transistors with a channel length of 100 m (1 A
versus 100 pA, when measured at VDS = -0.2 V)? Unfortunately, the authors reveal the
agreement between simulation and experiment only for one particular drain-source
voltage and one particular channel length, i.e. for VDS = -1 V and L = 100 m (see
Figure 2b). (The authors may argue that they are showing simulation and experiment for
a range of drain-source voltages in Figure 2c, but since the drain current in Figure 2c is
presented on a linear, rather than logarithmic scale, it is impossible to compare the
simulated and measured off-state currents in Figure 2c.) In order to validate the claim
that the SPICE model indeed predicts the significant increase in off-state current with
drain-source voltage, please show the simulated and measured log-ID vs. VGS curves
for a drain-source voltage of -0.2 V and for a drain-source voltage of -2 V, and for a
channel length of 10 m.
Our response to comment #4: The SPICE model developed is as explained above. We
have taken into account the exponential increase in the OFF state current due to
ambipolar conduction. We have modeled abmipolar conduction as a voltage dependent
(VGS and VDS) exponential current source. We have also incorporated the contribution of
metallic tubes in determining the OFF state current. In SPICE model the equations are
transformed into second order polynomial as
I = P0 + P1 VGS + P2 VDS + P3 VGS 2 + P4 VGS. VDS + P5 VDS2
Following table shows the model parameters used for W=200m/L=100m device and
W=200m/L=10m device.
Current Component
Parameter W=200m/L=100m W=200m/L=10m
Vthreshold
-4
-4
Ambipolar Current

0.45
0.45

3
3
KN
10e-9
10e-9
VG0
1
1

0.1
0.1
VT
-0.4
-0.4
PFET Current
KP
40e-6
13e-6
RS
11e3
3e3
RD
11e3
3e3
Metallic Tube Current
metallic
0
4e-7
Our SPICE model predicts the device characteristics for all bias conditions (V DS, VGS) as
well as for small/large channel lengths. Following graphs show the experimental vs.
SPICE model results

W = 200um L = 100um

Experiment
SPICE

-5

-ID, [A]

10

VD = -5

-6

10

VD = -2.5

-7

10

-8

10

VD = -0.5

-2

-1

VG, [V]

10

ON/OFF Ratio

10

10

10

10
-5

Experimental
SPICE
-4

-3

-2

VD, [V]

-1

W = 200um L = 10um
-4

-I D , [A]

10

Experiment
SPICE

-5

10

VD = -0.15

-1

-0.5

VG, [V]

0.5

VD = -0.9

10

O N /O FF R atio

10

10
VD = -1.5

10

10
-1.5

Experimental
SPICE
-1

VD, [V]

-0.5

88 Transistor Decoder Circuit: Time Domain Analysis

Pull up device: 20um/100um; Pull down device : 200um/100um (Assumed, can be changed) Frequency = 10 KHz

Zoomed-in view of first 8 outputs (Frequency is 10KHz) ; The output transitions are downwards (from 0 to -4V). In the paper,
output transitions are shown upwards.