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DMA Controller (V3)

This semester, we are designing a module for an embedded control system. The DMA controller is
programmable, and connected to a high speed bus. The high speed bus is inspired by the AHB, but is
not the same as the AHB. The DMA controller manages devices connected to a low speed bus. The
DMA controller can handle up to 4 devices. The buses are shared buses, and the controller must
generate the correct bus sequences on both the high speed bus, and the low speed bus. The test bench
will represent the memory connected to the high speed bus, and the high speed bus manager. The test
bench will also represent the low speed bus, and the devices connected to the low speed bus.

High
speed
bus

High speed bus


Interface

DMA Controller

The high speed bus has the following signals:


Name
Bits Dir

Low speed bus


Interface

Low
speed
bus

Function

System
clk

In

System clock

Rst

In

System reset

HSB Request
Req

Out Transaction request

CmdOut

Out Request command type


000=read single
001=read burst
010=write single
011=write burst
100=Interrupt request (Generated when reg f is written non zero)
101-111 = Reserved (Ignore them)

Name

Bits Dir

Function

Addrout

32

Out Address associated with request (Low two bits ignored)

LenOut

Out Number of words (4 bytes) for this request

HSB Response
Resp

In

Response to a request

RespType

In

Response type
000=Rejected (No such address or HW error)
001=Data from read
010=Data for write requested
011=Data for interrupt (returns register 15)
101=Slave read
110=Slave write

RespEnd

In

This satisfies the request

RespAddr

32

In

The address for this data (byte address. Lower 2 bits ignored)

RespDataIn

32

In

The response data from the bus

RespDataOut

32

Out The response data to the bus

RespHold

Out Cannot respond, please hold the bus. Used primarily for slave read and
writes.

LSB Interface
LSBreq

Out Request on the low speed bus

LSBaddr

16

Out Low speed bus Peripheral address (byte address)

LSBwrite

Out This is a write cycle

LSBdataOut

Out Data to a low speed device

LSBdataIn

In

Data from a low speed device

LSBatten

In

Attention request from low speed devices

The DMA controller is a bus master, and a slave on the high speed bus. It receives data in 32 bit word
units. On a write to the memory DMA can read a word, modify it, and then write back the entire word
if it wishes to update only one byte. There is no implied coherency between DMA and CPU accesses.
The CPU should not access the memory until an interrupt has been signaled indicating all DMA
activity is complete. It is assumed the memory controller will manage cache coherency.
The DMA controller responds to a slave write and read to a set of registers. These registers are accessed
at slave memory address 0xffff0C00 to 0xffff0FFF;
Addr
offset from
0xffff0c00
0

Name

PC

Bits

32

Comment

The program counter for the DMA controllers

Addr
offset from
0xffff0c00

Name

Bits

Comment

10

Run

LOB '1' allows running. '0' stops instruction execution. If


the CPU executes a stop instruction, this bit is cleared.

100-13C

Regs

32

The local registers 0-f for the DMA controller

The DMA controller is programmable. It has a set of internal registers. It executes a simple set of
instructions. Each instruction is coded into a 32 bit word as follows:
Opcode

Reg

Constant

Jump Op

Jump offset

10

Each instruction has two parts. The Opcode part uses a register and a constant field (Which may
address another register, After the calculation in the first part of the instruction, there is an optional
transfer of control to a jump offset from the current program counter. Each instruction is compound. It
may execute an opcode, and it may jump.
The DMA controller has an instruction execution unit. It executes instructions from the main system
memory using the high speed bus interface. To reduce bus traffic, the instruction execution unit has an
8 instruction buffer. As long as a loop is within this buffer, no external traffic will be created. All
requests for instruction data will be made as a burst of 8 words.
The registers addressed as 0-f are internal registers. These registers are private to the DMA controller.
They may be read and written over the bus. The constant is a signed value.
The jump offset is coded as two registers for some jump instructions. Reg A is bits 7:4 of the offset, and
Reg B is 3:0.
Opcode

Name

Function

00000

Load

The constant is loaded into the Reg

00001

Add

The constant is added to the contents of Reg

00010

And

The constant is anded to the contents of Reg

00011

Xor

The constant is XORed with the contents of Reg

00100

Sub

The constant is subtracted from the contents of Reg

00101

Cmp

The constant is subtracted from the contents of Reg, but not stored

00110

Tst

The constant is anded with Reg, but not stored

00111

Or

The constant is 'ored' with the reg

01000

Loadr

The constant selects a register, it is loaded into reg

Opcode

Name

Function

01001

Addr

The constant selects a register, it is added to the reg

01010

Andr

The constant selects a register, it is anded with the register

01011

Xorr

The constant selects a register, it is XORed with the register

01100

Subr

The constant selects a register, it is subtracted from reg

01101

Cmpr

The constant selects a register, it is subtracted from reg, but not stored

01110

tstr

The constant selects a register, it is anded with reg, but not stored

01111

Orr

The constant selects a register, it is 'ored' with reg

10000

SignExt

The reg bit 7 is copied to all upper 24 bits.

10001

Sl

The reg is shifted left by the number of bits specified in constant 4:0

10010

Sr

The reg is shifted right by the number of bits specified in constant 4:0

10011

LoadPC

The current PC + offset is placed in reg

10100

Slr

The reg is shifted left by the number of bits specified in the register
addressed by constant 4:0

10101

WriteLSB

Write the data in register 0 to the LSB at the address pointed to by the
register plus the constant. N and Z are not changed.

10110

ReadLSB

Read the LSB data to register 0 addressed by the address pointed to by the
register plus the constant. The 8 bits read set Z, and N is set to bit 7;

10111

ReadTst

Read the LSB data addressed by the register . And the data read with the
constant. Do not store the results. (Sets the condition code).

11000

ReadAtten Read the 4 atten bits anded with the constant, and stored in the register. Z
and N are set for 32 bit and operation.

11001

Read

32 bits are read from main memory pointed to by Reg, and the register
addressed by Constant 3:0 and placed in register 0

11010

Write

32 bits are written to main memory pointed to by Reg and the register
addressed by Constant 3:0. The data is obtained from register 0. N and Z are
not changed

11011

Stop

The run bit is turned off in register 0x10 for this CPU.

Rest

Reserved

Do nothing for now...

In general, most instructions perform


reg <- reg (opcode) data
where data is either another register, a constant, or the result of a bus operation.
Notable exceptions:
write
writelsb

all 'tst' instructions

Note: all instructions except load will set a condition code: the condition code consists of the following
bits:
Z (result is zero)
N (bit 31 of result is a one)
The jmp portion is encoded as follows:
Code

Action

0000

Do not jump PC<-PC+4

0001

Jmp zero PC<-PC+se(jump offset)

0010

Jmp negative PC<-PC+se(jump offset)

0011

Jmp zero or negative PC<-PC+se(jump offset)

0100

Jmp always PC<-PC+se(jump offset)

0101

Jmp non zero PC<-PC+se(jump offset)

0110

Jmp not negative PC<-PC+se(jump offset)

0111

Jmp not negative and not zero PC<-PC+se(jump offset)

1000

Do not jump PC<-PC+4

1001

Jmp (PC<-reg a + reg b) if zero

1010

Jmp (reg a + reg b) if negative

1011

Jmp (reg a + reg b) if zero or negative

1100

Jmp (reg a + reg b) always

1101

Jmp (reg a + reg b) if non zero

1110

Jmp (reg a + reg b) if not negative

1111

Jmp (reg a + reg b) if not negative and not zero

The jump offset is sign extended, and a length in words (shift left 2), and added to the program counter.
For opcodes 0000-0111. Reg A and Reg B are the addresses of two registers. These two registers are
added together to become the next PC. The lower 3 bits encode the branch condition. One half of the
jump opcodes are reserved for future expansion and customization. If no jump occurs, the PC = PC+4;
The instruction execution unit is not real fast. It runs at the design clock speed of 200 MHz, and takes 4
or more clocks to perform an instruction. These clocks are divided as follows:
1.
2.
3.
4.

Instruction fetch (May take more than one cycle if instruction not in the buffer)
Instruction decode
Instruction reg execute (May take more than one cycle if accessing the HSB or LSB)
jump calculations

All four instruction execution units are running at the same time. Arbitration is required to and from
each bus.

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