TMS320C50

Architecture
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OVERVIEW OF DSP
PROCESSORS
BY
Dr. M.Pallikonda Rajasekaran,
Professor/ECE
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Short history of DSPs

1960
DSP hardware using discrete components
1970
Monolithic components for DSP subsystems
1979
Intel 2920 DSP
(40 pin DIP)(EPROM,A/D,D/A,RAM)(1200bps modem)
1982

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Texas Instruments TMS32010

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Inside a DSP?

Computer
Engine

Program
Memory

Data
Memory

Input / Output
Serial ports
Timers
Host ports
I/O
External ports connects
Link ports
to
outside
world

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INSIDE A DSP ENGINE?

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Why DSP?
- Flexible to change Signal Processing
Operations through a change in Software,
whereas hardwired machines are difficult to
Reconfigure.
- High Speed Parallel Processing enables it
to Real World Processing.
- Multi-Function Instruction like MAC etc,.
- Multiple data paths
- Flexible addressing modes
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MEMORY ARCHITECTURE
Stored
Program
and
Data

Program
Control

ALU
Input
Output

Von Neumann Architecture

Stored
Program

Program
Control

ALU

Input
Output

Stored
Data

Harvard Architecture
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Conventional microprocessors
use:
Von Neumann architecture
-program and data all in a single
memory
-Address and data buses are
shared between instruction and
data fetches.

CPU/ALU

Addre
ss
Data

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Memory

-simple
-effective
BUT

performance problems:
-fetch for next instruction collides
with data fetch/store
-Buses may be idle during
instruction decode

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 Most DSP chips use Harvard architecture

-separate memory space(s) for program and data
-separate data and program buses
P Address

CPU/ALU
Instr.
D1
Address

Memory
#1

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Memory

D1 Data
D2 Address

Data

Program

D2 Data

Data
Memory
#2
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Comparison between DSP &

GP processor

GP P optimized for:
-Multi task operations
-handling huge OS
-handling various
programs
-Multiple I/O management
-transporting large size of
data

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DSPs optimized for:

-special digital processing
-real time processing
-small code size
-single program
-limited number of I/O
-low power

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DSP LEADING MANUFACTURERS

TEXAS INSTRUMENTS (TI)

ANALOG DEVICES (ADSP)
MOTOROLA

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TMS320C320 DSP Family

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DSP TEXAS
INSTRUMENTS FAMILY
TMS320C6000
C62X,C64X,C67X DSPs
TMS320C2000
C24X,C28X DSPs

Control
Optimized

TMS320C5000
C54X,C55X DSPs

Power
Efficient

OMAP
C55X+ARM

High
Performance

www.ti.com
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TMS320C2000 PLATFORM ROADMAP

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TMS320C2000 DSP Platform

TMS320C2000 family offers various DSP
processors for motor control. Based on the specific
requirements, the user can choose the particular
device for the speed control of Induction Motor/Brush
less motor/ Switch Reluctance motor. In this platform
varieties of DSP Processors are available in 3
categories.
TMS320F240
TMS320F2407
TMS320F2812.
Targeted for Industrial Automation, Automatic Control
Application, UPS, Motor Control, etc.
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TMS320F240

TMS320F2407A

TMS320F2812

16 Bit Fixed point

16 Bit Fixed point

32 Bit Fixed point

20 MIPS

40 MIPS

150 MIPS

544 x 16 Bit RAM

2.5k x 16 Bit RAM

18k x 16 Bit RAM

3 Timers

4 Timers

7 Timers

SPI & SCI Serial

ports

SPI, SCI & CAN

Serial ports

SPI, SCI & CAN

Serial ports

12 PWM Channels

16 PWM Channels

16 PWM Channels

16 Channel ADC @
6 microsec
conversion time

16 Channel ADC
@ 0.5 micro sec
conversion time

16 Channel ADC @
200 ns conversion
time

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TMS320C5000 PLATFORM ROADMAP

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TMS320C6000 PLATFORM ROADMAP

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TMS320C6000 DSP Platform

This has got 3 series of DSP Processor family.

TMS320C62XX

TMS320C64XX 

32 Bit Fixed Point DSP

TMS320C67XX

32 Bit Floating Point DSP

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32 Bit Fixed Point DSP

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Development Tools
CODE COMPOSER STUDIO
It includes

Assembler

Linker

Simulator

C/C++ compiler

Debugger
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ANALOG DEVICES
FAMILY

Blackfin processors

Tiger SHARC processors

SHARC DSPs

ADSP-21xx

Mixed signal DSPs
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www.analog.com/dsp

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NOMENCLATURE OF DSP
PROCESSORS

TMS 320 C 25 GB L
TMX-Expt. Device
TMP-Prototype Device
TMS-Qualified Device
PACKAGE TYPE
GB-Ceramic
N-Plastic DIP
FN-Plastic Leaded
FD-Ceramic Leadless

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C-CMOS
E-CMOS EPROM

TEMPERATURE
L -0 -70
H -0 -50
S - -55 -100
M - -55 - 125
A - -40 -85

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TMS320C5x Family Features

Fabrication using CMOS integrated-circuit
technology
Architectural design is based on the C25
Advanced Harvard architecture
A CPU with application-specific hardware
logic
On-chip peripherals
On-chip memory
Highly specialized instruction set
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TMS320C50 PROCESSOR

TMS320C50PQ57

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D/P RAM D. RAM

B0
B1
A(15-0) 512 X 16 512 X 16

D(15-0)

D/P RAM
9K X 16

CPU
16-bit T-Reg0
16 X 16 Multiplier
16-bit Barrel
32-bit P-register
Shifter (L or R)
ShiftL(0, 1, 4, -6)
32-bit ALU
32-bit Accumulator and Buffer
ShiftL( 0 7 )
8 Auxiliary Registers
8 Level H/W Stack
3 Status Registers
Block repeat/Circular Buffer
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Registers
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16-bit T-Reg 1,2

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D. RAM
B2
32 X 16

P. ROM
2K X 16

TMS320C50

I/O Ports
64K X 16
Software
Waitstates
Timer
Serial Port
Sync

PLU
BitSet, Clear
Test, Toggle
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Central Arithmetic Logic Unit (CALU )

16-bit 16-bit hardware multiplier with a 32-bit
product capability
32-bit arithmetic logic unit (ALU)
PLU-Executes IIy only logical operation without
affecting Accumulator
32-bit accumulator (ACC)
32-bit accumulator buffer (ACCB)
0- to 16-bit left and right data barrel-shifters

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Program Bus

TMS320C50 Multiplier/Accumulator

Data Bus

16

32
MUX

32

Right/Left
Shifter
(0-16)

16

16
T Register (16)

16
Multiplier (16 X 16)
32
P Register (32)
32
Left Shifter (0,1,4,-6)

16

MUX
16
32

MUX 32
32
32
Arithmetic Logic Unit (ALU)
32
Accumulator Register (32)
Accumulator Buffer (32)
32
16
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Left Shifter (0 7) ENGINEERING

C50 MEMORY MAPPING

Program

Data

0000

0000

INTERNAL
RAM (32KW)

EEPROM
(48KW)
7FFF
8000

BFFF
C000

EXTERNAL
RAM
(32KW)

EXTERNAL
RAM (16KW)
FFFF
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FFFF
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TMS320C50 DATA MEMORY

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TMS320C50 DATA MEMORY

Total memory = 0000h FFFFh (64KW)
Total no. pages = 200h
Every page contains 80h locations
Page 0 = 0h * 80h = 0000 to 007F
Page 1 = 1h * 80h = 0080 to 00FF

.
.
.
.
.
.
.

.
.
.
.
.
.
.

.
.
.
.
.
.
.

Page 100 = 100h * 80h = 8000 to 807F

Page 1FF = 1FFh * 80h = FF80 to FFFF
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Addressing Modes
Direct addressing-ADD 9h
Indirect addressing
Immediate addressing-Rpt # 99
Dedicated-register addressing
Memory-mapped register addressing
Circular addressing
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Dedicated-register addressing
BLDD BMAR,DAT 100
BLDD-Block Move from Data memory to
Data memory
BMAR-Block move Address Register
BMAR-200h-Predefined
Data in Address 200h is copied to data
memory location 100h
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Memory-mapped register addressing

LMMR, CBCR #800h
Data in CBCR is loaded to the location
800H
CBCR-Circular buffer control Register

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Circular addressing

CBSR-1
CBSR-2
CBER-1
CBER-2
CBCR

Used for convolution, correlation & FIR Filter

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ASSEMBLEY LANGUAGE PROGRAMS

Linear convloution
.text
.mmregs
START:
LDP #0002H
LAR 3,#8200H ;y(n) starting
LAR 4,#0007 ;N1+N2-1
LAR 1,#8100H ; x(n) data array with N1-1 trailing zeros
LOP: MAR *,1
LACC *+
SACL 050H ;starting of the scope of multiplication
LAR 2 ,#0153H ; end of the array, to be multiplied with
h(n)
{150+N1-1}
MAR *,2
ZAP
RPT #0003 ;N1-1 times so that N1 times
MACD 0C100H,*APAC
;to accmulate the final product sample
MAR *,3
SACL *+
MAR *,4
BANZ LOP ,*H:
B
H

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input :
h(n) - program memory
c100 - 1
c101 - 3
c102 - 1
c103 - 3
c104 - 0
c105 - 0
c106 - 0
c107 - 0
x(n) - data memory
8100 - 0
8101 - 1
8102 - 2
8103 - 1
output:
y(n)
- data memory
8200 - 1
8201 - 5
8202 - 8
8203 - 8
8204 - 7
8205 - 3
8206 - 0
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Basic software tools for dsp design

Basic text editor

:This can be a very simple application such as

windows notepad.It is used for entering DSP
programs

Assembler/ Compiler :Used to convert the user editor based files into a
machine readable format

Conversion
Utilities

:Converts assembled and linked DSP code into a

DSP chip executable format (.hex, .bin, .asc etc)

Down loader

:It is used to transfer the DSP executable format

into the DSP development board

Debugger

:Enables software to be tested for the particular

DSP device; the debug environment may be in
NETWORK or emulator
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theTIFAC
formCORE
of aINsimulator

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Software
Source

Efficiency Effort

C
C++

Compiler
Optimizer

80 100%

ASM

Hand
Optimize

100%

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Low

High

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Software Tools
Assembler
optimizer

Link.cmd

Text
editor

Assembler

.asm
.c
Compiler
optimizer

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Linker
.obj

.c
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Debugger
.out

c source file
assembly source file
object file
executable file
linker command file
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DSP choosing considerations

Arithmetic formats
Data width
Speed
Memory organization
Ease of development
Multiprocessor support
Power consumption management
Cost

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 Fixed point

Floating point

-more flexible
-easier to program
-more expensive
-higher power
consumption

-difficult programming
-low cost
-limited dynamic
-range & precision

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Data widths are

-32 bit
-16 bit
-24 bit
-20 bit
Cost considerations
-chip size
-pin number
-external memory
Memory organization
-On and Off-chip memory size

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Development tools:
-software tools
assemblers
linkers
simulators
debuggers
compilers
-hardware tools
development boards
emulators

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Cost:
Least expensive DSPs have
-fewer features
-less on chip Memory
-lower performance
Chipset price depends on:
-Packaging
-Quantity

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MAC using GPP

R0

11
12
3

11

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2
3

24

X
R1

R2

Loop

Clr

;Clear Accumulator A

Clr

; Clear Accumulator B

Mov

*R0, Y0

; Move data from memory location 1 to register Y0

Mov

*R1,X0

; Move data from memory location 2 to register X0

Mpy

X0,Y0,A

;X0*Y0 ->A

Add

A,B

;A + B -> B

Inc

R0

;R0 + 1 -> R0

Inc

R1

;R1 + 1 -> R1

Dec

;Dec N (initially equals to 3)

Tst

;Test for the value

Jnz

Loop

;Different than zero loop again

Mov

B,*R2

;Move result to memory

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MAC using DSP

Harvard Architecture allows multiple
memory reads
11
12
3

11

R2

24

44

2
3

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Clr

;Clear Accumulator A

Rep

; Rep N times the next instruction

MAC

*(R0)+, *(R1)+, A

; Fetch the two memory locations pointed by R0 and R1, multiply

them together and add the result to A, the final result is stored back
in A

Mov

A, *R2

; Move result to memory

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.mmregs
.text
Start:
LACC #2345H
LAR AR1,#8000H
LAR AR2,#0fffH
Loop:
MAR *,AR1
SACL *+,AR2
BANZ Loop,*HERE:B HERE
.end
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TI 5000 SERIES
TMS320C50
1. MICRO 50 ST
2. MICRO 50 LC
3. MICRO 50 EB
TMS320VC5416
1. MICRO 5416
2. MICRO 5416 AT
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TMS 320C50 STARTER KIT

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TMS 320C50 TRAINER KIT

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C50 TRAINER KIT

BUS EXPANDER

MONITOR
EEPROM

TIMER &
SERIAL
LOGIC

SERIAL
PORT

TIMER
PORT
CONNECTOR
Analog

EXTERNAL
DATA
MEMORY

EXTERNAL
PROGRAM
MEMORY

Output

C50
PROCESSOR
Analog
Input

HIGH
SPEED
ADC

HIGH
SPEED
DAC

RESET
LOGIC

BATTERY
BACKUP
(MICRO 50LC)
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TMS320C50 KIT WITH FUNCTION GENERATOR

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TMS 320C50 PROFESSIONAL TRAINER KIT

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TMS 320VC5416 TRAINER KIT

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TMS320VC5416 ADVANCED TRAINER KIT

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TI 6000 SERIES
TMS320C33
1. MICRO 33
TMS320C6713
1. MICRO 6713 AT
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TMS 320C33 TRAINER KIT

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TMS320C6713 TRAINER KIT

MICRO-6713

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TI 2000 SERIES
TMS320F240
1. MICRO 240
TMS320F2407
1. MICRO 2407
2. MICRO 2407 EB
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TMS 320F240 TRAINER KIT

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TMS 320F2407 TRAINER KIT

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IPM UNIT

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TMS 320F240 BASED MOTOR CONTROL

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ANALOG DEVICES SERIES

ADSP 2181
1. EZ KIT 81
2. MICRO 81 AD
3. MICRO 81 AT
ADSP 2189
1. MICRO 89 ST
2. MICRO 89 AT
ADSP 2191
1. MICRO 91
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ADSP 2181 ADVANCED TRAINER KIT

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ADSP 2181 TRAINER KIT

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ADSP 2181 TRAINER KIT

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THANK YOU
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