F2015 Lec 02 MOS Delay Models

MOS and Delay
EEM216A
Models
Fall 2015
Prof. Dejan Marković

ee216a@gmail.com
I Assume You Know This
(2) MOS IV Model

EE115C (3) MOS RC Model
(4) Inverter VTC
Lectures 2-5 (5) Propagation Delay
2.22
D. Markovic / Slide
Levels of Modeling
Analytical
CAD analytical
Switch-level sim
Transistor-level sim
complexity
Different complexity, accuracy, speed of convergence…
2.33
D. Markovic / Slide
MOS Transistor Modeling
Our goal is to model

S
delay and energy
D
not current
But have to start

with current
2.44
D. Markovic / Slide
MOSFET, Notations
G
D S
tox
Leff
xd xd
Ld
Hand-analysis I-V formulas: L = Leff

2.55
D. Markovic / Slide
MOS I-V Model
VGT = VGS – VT Subthreshold region (VGT ≤ 0)

G W VGS – VT + γD·VDS
ID = I0· ·10 S
W0
S D
ID Active region (VGT ≥ 0) Lin, Sat, V-Sat
2
W Vmin
B ID = k’· ·(VGT·Vmin – )·(1 + λ·VDS)
L 2
Vmin = min(VDS, VGT, VDSAT)
Lin Sat V-Sat

2.66
D. Markovic / Slide
Model Parameters: Active Region
VT0 : Threshold voltage

γ : Body effect
VDSAT : Velocity saturation
k’ : Transconductance (k’ = µ·Cox)
λ : Channel-length modulation (CLM)
• CLM term (1 + λVDS) also included for linear region

▪ Empirical, no physical justification
2.77
D. Markovic / Slide
Threshold Voltage, VT
VSB = 0
𝑽𝑻 = 𝑽𝑻𝟎 + 𝜸 ⋅ ( 𝟐𝚽𝑭 + 𝑽𝑺𝑩 − 𝟐𝚽𝑭 )
G VT S
NMOS:
D
• VSB > 0 (RBB)
• VSB < 0 (FBB)
VSB PMOS:
• VSB > 0 (FBB)
B • VSB < 0 (RBB)
2.88
D. Markovic / Slide
Vsat Occurs at LOWER VDS than Sat
VDS = k·VGT VDS = VGT
ID
Vsat Sat 𝟏
𝑘=
k 𝑽𝑮𝑻
𝟏+
𝝐𝒄 ⋅ 𝑳
k = k(VGT)
VDS
2.99
D. Markovic / Slide
Vsat: Less Current for Same VGS
ID Sat (Long-L)
VGS = VDD
Vsat (Short-L)
VDSAT VGT VDS
2.10
D. Markovic / Slide 10
CLM Holds in Vsat
VDS > VDSAT
S VDS D
Leff Lp
VDSAT
ΔVDS
2.11
Simulation: Long vs. Short Channel (90nm)
• IDVSat(VGS) quadratic, IDSat(VGS) linear
• Stronger CLM in short-L than long-L
• IDVsat < IDSat only for large VGS
2.4µm/0.5µm
0.48µm/0.1µm
2.12
Simplification: VDSAT = Constant
Const • Simplifies hand

VDSAT calculations
ID
BUT…
VDS
2.13
Regions of Operation
Const • Simplification
VDSAT introduces “Sat”
region for low VGS
ID
• VGT < VDSAT, the
device appears
Lin VSat to be in “Sat”
VGT = VDSAT
“Sat”
VDS
2.14
Unified Model vs. SPICE Simulation
VDS = VDSAT simulation
model
0.25
• Transition
lin/v-sat:
0.2 Lin largest
VSat modeling
ID (mA)
0.15 error
0.1
0.05 VGT = VDSAT

“Sat”
0
0 0.2 0.4 0.6 0.8 1
VDS / VREF
VDS = VGT 2.15
Model Parameters: Subthreshold
I0 : Nominal leakage current

S : Subthreshold slope
γD : DIBL factor
2.16
Modeling the Sub-threshold Behavior
G
S D Parasitic BJT
Cox 𝑽𝑩𝑬
n+ E B C n+ 𝑰𝑪 = 𝑰𝟎 𝒆 𝚽𝒕
𝑽𝑮𝑺
Cd 𝑽𝑩𝑬 =
𝑪𝒅
𝟏+
𝑪𝒐𝒙
𝐶𝑑
𝑛 =1+
𝐶𝑜𝑥
𝑽𝑮𝑺 𝑽 𝑘𝑇
− 𝜱𝑫𝑺 Φ𝑡 =
𝑰𝑫 = 𝑰𝟎 ⋅ 𝒆𝒏𝜱𝒕 ⋅ (𝟏 − 𝒆 𝒕 ) 𝑞
2.17
Sub-threshold ID vs. VGS
Physical 𝑽𝑮𝑺 𝑽
− 𝑫𝑺
model 𝑰𝑫 = 𝑰𝟎 ⋅ 𝒆𝒏𝚽𝒕 ⋅ (𝟏 − 𝒆 𝚽𝒕 )
𝑉𝑇
𝑊 2 −𝑛Φ
𝐼0 = 𝜇 Φ𝑡 𝑒 𝑡
𝐿
DIBL
Empirical 𝑾 𝑽𝑮𝑺 −𝑽𝑻 +𝜸𝑫 𝑽𝑫𝑺

𝑰𝑫 = 𝑰𝟎 ⋅ ⋅ 𝟏𝟎 𝑺
model 𝑾𝟎
𝑺 = 𝒏𝚽𝒕 𝐥𝐧(𝟏𝟎) [mV/dec]
2.18
Drain Induced Barrier Lowering (DIBL)
Effective VT
Long-L
Short-L
decreasing L
VDS
• Field lines from the drain affect charge in the channel

• Typically derived for small VDS, holds for large VDS
▪ Even if we neglect CLM, IDS will increase b/c of VT drop
▪ Device turned off by VGS (below VT) may turn on by VDS
2.19
The Sub-threshold Slope Parameter
𝑺 = 𝒏𝚽𝒕 𝐥𝐧(𝟏𝟎) [mV/dec]
Change in VGS that gives 10x change in IDS

• n=1 60 mV/dec (ideal)
• n = 1.5 90 mV/dec (typical)
• S: increases with temperature (𝚽𝒕 )

• n: intrinsic to device topology / structure
2.20
90nm Simulation: Sub-threshold ID vs. VGS
𝑽𝑮𝑺 −𝑽𝑻 +𝜸𝑫 𝑽𝑫𝑺

𝑰𝑫 ~𝟏𝟎 𝑺
PMOS NMOS VDS : 0 to 0.4V
10x
𝑺 = 𝒏𝚽𝒕 𝐥𝐧(𝟏𝟎)
90mV
90mV/dec
2.21
90nm Simulation: Sub-threshold ID vs. VDS
𝑽𝑮𝑺 −𝑽𝑻 +𝜸𝑫 𝑽𝑫𝑺

𝑰𝑫 ~𝟏𝟎 𝑺
PMOS NMOS VGS : 0 to 0.3V
480nm/100nm 240nm/100nm
2.22
Transistor Stacks Reduce Leakage
VDD
A=B=0
A B
Vx @ ID1 = ID2?
B M1 • VT1 > VT10 (RBB)
𝑉
− 𝑆𝑇1
Vx ▪ 𝐼𝐷1 ∝ 10
A M2 • Large ΔVDS1 required
▪ Vx very small
2.23
~10x Lower Leakage for a Stack of 2
VDD
A=B=0 VDD − VT
A B
Temp
B M1
10x
A M2
Vx
[IEEE Press, New York,  2000]
2.24
Practically Stack 2 or 3 Transistors
Leakage Power Reduction
[IEEE Press, New York,  2000]
2.25
Near-VT Region
(VT + ΔV Region)
2.26
Definition: Inversion Coefficient (IC)
Inversion coefficient indicates proximity to VT
IC = 1 (@ VT), IC < 1 (sub-VT), IC > 1 (above-VT)
1/100 1/10 1 10 100
Sub-VT VT Strong inv.
a.k.a. VT + ΔV region
2.27
Current Model
Start from IS
𝑾
𝑰𝑺 = 𝟐𝒏 ⋅ 𝝁 ⋅ 𝑪𝒐𝒙 ⋅ ⋅ 𝚽𝒕 𝟐
𝑳
Sub-VT (VGS = 0) Above-VT

𝝈𝑽𝑫𝑫 −𝑽𝑻
𝑰𝑫 = 𝑰𝑺 ⋅ 𝒆 𝒏𝚽𝒕 𝑰𝑫 = 𝑰𝑺 ⋅ 𝑰𝑪/𝒌𝒇𝒊𝒕
(𝟏+𝝈)𝑽𝑫𝑫 −𝑽𝑻
𝑰𝑪 = (𝒍𝒏 (𝒆 𝟐𝒏𝚽𝒕 + 𝟏))𝟐
2.28
Calculate VDD from IC
Useful for optimizations
𝑽𝑻 + 𝟐𝒏𝚽𝒕 𝒍𝒏 (𝒆 𝑰𝑪 − 𝟏)
𝑽𝑫𝑫 =
𝟏+𝝈
Given IC, find VDD for LVT and HVT?
2.29
Fitting the IC Parameter
Constrain MMSE-based curve fit with IC = 1 @ VT
65nm tech.
2.30
Toward Delay Model:
Alpha-Power-Law Model
2.31
Alpha-Power Model of the Drain Current
Basis for delay calculation, useful for hand analysis
1 W α Neglects
ID  μ·C ox · ·(VGS  VT )
2 L CLM
Empirical α: vel. sat index

model 1<α<2
T. Sakurai and R. Newton, “Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter
Delay and Other Formulas,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990.
1.32
α-Power Model: Curve Fitting (MMSE)
simulation model
6
How to fit the model?
VGS
ID (normalized)
4 • 1<α<2
3 ▪ Degree of v-sat
2 • α depends on VT
1
▪ Many combinations
0
▪ Use VT0 (your tech.)
0 0.2 0.4 0.6 0.8 1
VDS / VDD
1.33
Simulation Models
Physical + empirical parameters (100+ parameters)
• Spectre 45nm Cadence GPDK
/w/apps/public.2/tech/cadence
/45nm/gpdk045_v_3_5/models
/spectre/gpdk045_mos.scs
• HSPICE 32-28nm Synopsys EDK
/w/apps/public.2/tech/synopsys
/32-28nm/SAED32_EDK/tech
/hspice/saed32nm.lib
2.34
MOSFET Behavior: Summary
• MOSFET: a 4-terminal device

▪ Body impacts performance (VT)
• The current in (V)Saturation depends on VDS

▪ CLM: Leff is a function of VDS
▪ DIBL: High EDS lowers VT
2.35
MOSFET: Modes of Operation
• Velocity saturation
▪ Charge velocity saturates at high EDS
• Subthreshold
▪ Current still flows when VGS < VT
• Linear
▪ Not interesting in digital design
• Weak (near-VT) inversion
▪ Crucial for ultra-low-power design
2.36
Modeling
Gate Delay
2.37
Review: CMOS Inverter VTC
WP/LP P: Lin
in out Vout N: Off P: Lin
WN/LN N: Sat
1.0 Vin = Vout
0.8
• Inverter DC response P: Sat
0.6 VM N: Sat
0.4
• 5 regions of operation P: Sat P: Off
0.2 N: Lin N: Lin
• Logical threshold
▪ Vin = Vout 0.2 0.4 0.6 0.8 1.0 Vin
2.38
Logical Threshold Voltage
• Set IDP = IDN and solve
▪ Dependence on P:N sizing WP/LP
in out
and mobility ratio WN/LN
▪ Slight dependence on VTP/N
𝑽𝑫𝑺𝑨𝑻𝑵 𝑽𝑫𝑺𝑨𝑻𝑷
𝑽𝑻𝑵 + + 𝒓 ⋅ (𝑽𝑫𝑫 + 𝑽𝑻𝑷 + )
𝑽𝑴 = 𝟐 𝟐
𝟏+𝒓
𝒌𝒑 ⋅ 𝑽𝑫𝑺𝑨𝑻𝑷
𝒓=
𝒌𝒏 ⋅ 𝑽𝑫𝑺𝑨𝑻𝑵
2.39
Use VM = VDD/2 Unless Severely Skewed
• Not so easy if not an inverter
▪ Depends on which input the gate is driving
• In1 to Out VTC can be different from In2 to Out
▪ Use VDD/2 as average case
• Unless severely skew the P:N ratio
Vout in2 WP2

in1 WP1
Vin = Vout
out
in2 WN2
in2
in1 in1 WN1
Vin
2.40
Sensitivity of VTC to P:N
• Fortunately, VM is not very sensitive to P:N ratio (skew)
▪ Ranges from 1.35V to 1.75V (for a 3.3-V VDD)
▪ VM = VDD/2 is quite reasonable
10-15% change
for 2x skew
2.41
Gate Delay
Inputs Outputs
Logic Gates
• Time b/w an input transition and an output transition

▪ Different delays for different input to output paths
▪ Different for an upward or downward transition
2.42
Logic Transition
• Time at which a signal crosses logical threshold voltage
▪ Digital abstraction for 1 and 0
▪ Often use VDD/2
out in
tpHL
Voltage
VM High-to-Low
Output Transition
Time
tpHL
2.43
Delay Definitions
50%
Logic
delay
90%
50%
10%
Fall time Rise time 2.44

Static CMOS Gate Delay
• Gate output drives the inputs to other gates (+ wires)
▪ Only pull-up or pull-down, not both
▪ Capacitive loads (CLOAD)
tp
in out
CLOAD
tp = tpLH or tpHL
2.45
Multi-Stage Logic
The delay of each stage treated separately
tp1 tp2
in out
tp = tp1 + tp2
2.46
RC Delay Model
• R: we can use the resistor model of a transistor
▪ Take into account the different regions of operation
▪ Use a realistic slope to model an input switching
• C: take the average capacitance of a transistor as well
• The easy model Inverter

Model RDRVP
(one we’ll primarily use)
▪ Delay ~ RDRVCLOAD in out
▪ RDRV ~ L/W
RDRVN
2.47
Switched Resistor Model
600
• Switch model insufficient
500
• Regions of operation matter
400
IDS (µA)
300 • With digital input on gate,

device is either ON or OFF
200
100
0
0 0.5 1 1.5 2 2.5
VDS (V)
2.48
Resistor Approximation
600
• Linear R approximation
500
• With digital input on gate,
400
device is either ON or OFF
IDS (µA)
300 ▪ Approx. ON device

200 with Ron (red line)
100
0
0 0.5 1 1.5 2 2.5
VDS (V) Ron
S D
Vo = VDD
G CG
2.49
Range of VDS = Vswing
600
Assumptions:
500
• Saturation region
400
IDS (µA)
• VDS : VDD  VM
300
200 Vswing • Vswing = VDD – VM
100
0
0 0.5 1 1.5 2 2.5
VDS (V) Ron
S D
Vo = VDD
G CG
2.50
Calculating the Resistance
• Ron is an “effective” resistance that is averaged
𝑽𝑫𝑫
𝑹 𝑽𝑫𝑺 = + 𝑹(𝑽𝑫𝑺 = 𝑽𝑫𝑫 )
𝑹𝒐𝒏 = 𝑹𝒂𝒗𝒈 = 𝟐
𝟐
• R is large-signal resistance
𝑽𝑫𝑺𝟎
𝑹(𝑽𝑫𝑺 = 𝑽𝑫𝑺𝟎 ) =
𝑰𝑫 (𝑽𝑫𝑺𝟎 )
• Input transition dependent
▪ Input is not a perfect step
2.51
Calculating (Effective) Ron
VGS ≥ VT ID VGS = VDD

Ron
S D Rmid
R0 Vswing
VDS
VDD /2 VDD
[EE115C stuff]
2.52
0th Order Model: Step Input
off Vo = VDD 600 VSat

CLOAD 500 Lin
400
IDS (µA)
300
• NNOS and PMOS drive
200
with maximum |VGS|
100
• I = CdV/dt, Δt = CΔV/I 0
0 0.5 1 1.5 2 2.5
▪ Discharge CLOAD in VSat VDS (V)
▪ Discharge in Triode
2.53
0th Order Model: Discharge Model
• Discharge in VSat
off Vo = VDD ▪ VDSAT < Vout < VDD
CLOAD 𝑽𝑫𝑫 − 𝑽𝑫𝑺𝑨𝑻
𝚫𝒕𝟏 = 𝑪𝑳𝑶𝑨𝑫 ⋅
𝑰𝑫𝑺𝑨𝑻,𝒂𝒗𝒈
• I = CdV/dt • Discharge in Triode

▪ Remainder of the way
• Δt = CΔV/I
𝟎
𝒅𝑽
𝚫𝒕𝟐 = 𝑪𝑳𝑶𝑨𝑫 ⋅
𝑰𝑫
𝑽𝑫𝑺𝑨𝑻
2.54
Output Transition of 0th Order
ID
VSat
off Vo = VDD
CLOAD Lin
time
• Solvable equations, BUT • Empirical model

▪ Unrealistic input ▪ Slope correction
▪ CLOAD not linear ▪ Effective CLOAD
▪ Only Vsat matters ▪ Linear resistance
2.55
Calculating the Capacitance
• Like R, MOS capacitances are voltage-dependent
• Many capacitance models, here’s a common one:
G
CGS CGD
Too detailed
S D
CSB CGB CDB
for designers
B
• For delay analysis, we linearize gate and diffusion caps
▪ Gate capacitance (G-Ch, G-overlap)
▪ S/D capacitance (Diffusion)
2.56
MOS Capacitances: Summary
• Gate-Channel Capacitance
▪ CGC = Cox·W·Leff (Off, Lin)
▪ CGC = (2/3)·Cox·W·Leff (VSat)
Cgate
• Gate Overlap Capacitance
▪ CGSO = CGDO = CO·W (All)
• Junction/Diffusion Capacitance
Cparasitic
▪ Cdiff = Cj·LS·W + Cjsw·(2LS + W) (All)
γ = Cpar / Cgate < 1 𝑪∝𝑾 (fF / µm)
2.57
Elmore Delay
2.58
Elmore Delay (1948)
• Defined as the first moment of the impulse response
▪ Derivative of the unit step response, V’(t)
∞
V’(t)
𝒕𝑬𝒍𝒎𝒐𝒓𝒆 = 𝒕 ⋅ 𝒗′ 𝒕 ⋅ 𝒅𝒕
𝟎
tElmore t ∞
when 𝒗′ 𝒕 ⋅ 𝒅𝒕 = 𝟏
𝟎
• Works for monotonic waveforms

• Works well with symmetric impulse response
▪ Reasonable for an output transition of a gate
2.59
The ln(2) Issue
• Ideal RC response has a non-symmetric V’(t)
▪ This results in a positive skew (overestimated delay)
▪ Dominant-pole approximation:
𝒕
−𝑹𝑪
𝑽 𝒕 =𝟏−𝒆
• The 50% point delay

▪ For ½ = et/RC, t = tElmoreln(2)  a factor of 0.69
• tElmore is the upper bound on gate delay
▪ If we use a slow input transition (instead of a step),
the factor approaches 1
2.60
The ln(2) Issue: Another Look
𝒕𝒑 = 𝟎. 𝟔𝟗 ⋅ 𝒕𝑬𝒍𝒎𝒐𝒓𝒆 = 𝟎. 𝟔𝟗 ⋅ 𝑹𝑪
• Account for the error by characterizing gate resistance

▪ Use RC delay to calculate Reffective
▪ Reffective already includes the ln(2) factor
𝒕𝒑 = 𝑹𝒆𝒇𝒇𝒆𝒄𝒕𝒊𝒗𝒆 𝑪
Slope dependent
2.61
The Impact of Input Slope
• Model the delay as tp = 0.69RC (step response)
▪ Non-step input: rise/fall time is absorbed in R
▪ R is different than the one extracted from I-V
Too many R’s to keep track of…
2.62
Input Slope: A Better Model
Delay is linearly dependent on input rise/fall time:
tp = 0.69RC + η·tslope
• η is the slope factor (typical values: 0.1 – 0.2)

• The model is limited to a range of fanouts
Another version of this model (stage n):

tp(n) = tp(n),step + β·tp(n-1),step
• β is the slope factor (typical values: find by simulation)

• Slope is proportional to step-delay of previous stage
2.63
Example 2.1: RC Gate Delay
• NAND2 driving an Inverter
in2 in1
Assumptions (Sat): 3µm 3µm 12µm
out
• RN = 3 kΩ-µm, RP = 7.5 kΩ-µm in2 2µm 6µm
• CGN = CGP = 2 fF/µm
• CDN = 1.5 fF/µm, CDP = 2 fF/µm 2µm
in1
Pull-Down Pull-Up
RP Calculate τPU and τPD:

out
• RN = 1.5 kΩ, RP = 2.5 kΩ [?]
RN CLoad out • CLoad = 36 fF
RN CLoad
• τPU = 90 ps, τPD = 108ps
2.64
Accounting for Velocity Saturation
• PMOS (no stack) is VSat

▪ RP,no-stack = 6/5·RP,stack = 6/5·RP (Sat)
Pull-Up
• VSat : less current  higher R
RP
Calculate RP in VSat:
out
RP = 6/5·2.5 kΩ = 3 kΩ
CLoad
• CLoad = 36fF
• τPU = 108 ps
(instead of 90ps)
2.65
Including Self-Loading Capacitance
• CN: diffusion cap (depends on the layout and sharing)
Pull-Down Pull-Up
out RP
RN out
CLoad
CN RN CLoad
CN
• Model is now RC network and depends on input

▪ In1 switching assumed
2.66
Finding the Capacitances
in2 in1
3µm 3µm
12µm Assumptions (Sat):
out
• CGN = CGP = 2 fF/µm
in2 2µm 6µm
• CDN = 1.5 fF/µm
CLoad
CN 2µm • CDP = 2 fF/µm
in1
Calculate CLoad and CN: Components:

• CLoad = Cinv + Cpar = 51 fF • Gate
▪ Cinv = 2·(12 + 6) = 36 fF • Diffusion
▪ Cpar = 2·3 + 2·3 + 1.5·2 = 15fF • Shared diff
• CN = 1.5 · 2 = 3 fF
2.67
Calculate RC Time Constants
Pull-Up
τPU = 127.5 ps RP
Worst-case RC (In1, In2) out
2.5k·51f
CLoad
τPD = 153 ps τPD = 157.5 ps

In2-out Pull-Down In1-out Pull-Down
out out
RN CLoad V0 = VDD − VTN RN CLoad
V0 = 0
CN RN
3k·51f 1.5k·3f
CN RN
+ 3k·51f
2.68
Two Components of Delay
• Delay due to self-loading
CLoad = Cself + Cgate
▪ Blue and red capacitances
• Delay due to gate loading in2 in1
3µm 3µm
12µm
▪ Green capacitances out
in2 2µm 6µm
CLoad
CN 2µm
Write delay as 2 parts: in1
τPU = RPCself + RPCgate

Note the high
τPD = RN(CN+2Cself) + 2RNCgate self-loading delay
2.69
C·ΔV/I Delay Model
• Based on the capacitance charging and discharging
• ΔV is the voltage to the transition (~VDD/2)
• Similar except we are breaking R into 2 components

▪ Averaging of V/I
▪ I is an average drive current
• Helps understand what determines R

▪ I ∝ mobility and W/L
▪ I ∝ (VGS − VT), VGS ∝ VDD
▪ Can anticipate what might happen if VDD drops
2.70
Alpha-Power-Law Model
• Bad for current
• Good for delay
2.71
Alpha-Power Model: Saturation Current
• |VDS| > 0.5V
simulation model
300 300
Kn = 63 Kp = 31
250 VTn = 0.28 250 VTp = 0.30 12%
an = 1.13
13% ap = 1.31 rms error
NMOS ID ( A)
PMOS ID ( A)
200 200
rms error
150 150
100 100
50 50
0 0
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
V (V) |V | (V)
DS DS
The model could be refined to include CLM

2.72
Saturation + Linear: Error Increases
• |VDS| > 0.1V 13%  40%+ error
simulation model
300 300
Kn = 54 Kp = 26
250 VTn = 0.29
an = 1.09
250 VTp = 0.33
ap = 1.23
40%
rms error
46%
NMOS ID ( A)
PMOS ID ( A)
200 200
150 rms error 150
100 100
50 50
0 0
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
V (V) |V | (V)
DS DS
Alpha-power model does not fit well in linear region

2.73
Alpha-Power Model: Great for Delay
• Start from 1st principles
𝚫𝐕
𝑫𝒆𝒍𝒂𝒚 = 𝑪 ⋅
𝑰𝒂𝒗𝒈
• Delay = f (W, VDD)
Fitting parameters:
Von, αd, Kd
𝐊 𝐝 ⋅ 𝐕𝐃𝐃 𝑾𝒐𝒖𝒕 𝑾𝒑𝒂𝒓

𝑫𝒆𝒍𝒂𝒚 = 𝜶
⋅ +
(𝑽𝑫𝑫 − 𝑽𝒐𝒏 − 𝚫V𝑻 ) 𝒅 𝑾𝒊𝒏 𝑾𝒊𝒏
2.74
Gate Delay as a Function of VDD
100,000
100000
10,000 Exp.
Delay (norm.)
10000
increase
1,000
1000 in sub-VT
Delay (norm.)
100
100
10
10
11
00 0.2
0.2 0.4
0.4 0.6
0.6 0.8
0.8 11 1.2
1.2
V DD (V)
Vdd (V)
2.75
Summary
• Device R and C determine circuit performance
• Elmore delay (approximation): initial insight into design
▪ Step response, does not account for signal slopes
▪ Several models to account for slope (+ more coming)
▪ Simulation-based parameter extraction most accurate
(next lecture)
Next lecture:
• Logic design concepts
• Simulation-based models
• Gate vs. wire delay
• Gate sizing basics
2.76

F2015 Lec 02 MOS Delay Models

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F2015 Lec 02 MOS Delay Models

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MOS and Delay

Prof. Dejan Marković

(2) MOS IV Model

Different complexity, accuracy, speed of convergence…

Our goal is to model

But have to start

Hand-analysis I-V formulas: L = Leff

VGT = VGS – VT Subthreshold region (VGT ≤ 0)

Lin Sat V-Sat

VT0 : Threshold voltage

• CLM term (1 + λVDS) also included for linear region

𝑽𝑻 = 𝑽𝑻𝟎 + 𝜸 ⋅ ( 𝟐𝚽𝑭 + 𝑽𝑺𝑩 − 𝟐𝚽𝑭 )

VDS = k·VGT VDS = VGT

VDSAT VGT VDS

VDS > VDSAT

Const • Simplifies hand

0.05 VGT = VDSAT

I0 : Nominal leakage current

Empirical 𝑾 𝑽𝑮𝑺 −𝑽𝑻 +𝜸𝑫 𝑽𝑫𝑺

𝑺 = 𝒏𝚽𝒕 𝐥𝐧(𝟏𝟎) [mV/dec]

• Field lines from the drain affect charge in the channel

𝑺 = 𝒏𝚽𝒕 𝐥𝐧(𝟏𝟎) [mV/dec]

Change in VGS that gives 10x change in IDS

• S: increases with temperature (𝚽𝒕 )

𝑽𝑮𝑺 −𝑽𝑻 +𝜸𝑫 𝑽𝑫𝑺

PMOS NMOS VDS : 0 to 0.4V

𝑽𝑮𝑺 −𝑽𝑻 +𝜸𝑫 𝑽𝑫𝑺

PMOS NMOS VGS : 0 to 0.3V

Leakage Power Reduction

[IEEE Press, New York,  2000]

1/100 1/10 1 10 100

Sub-VT VT Strong inv.

Sub-VT (VGS = 0) Above-VT

Useful for optimizations

Given IC, find VDD for LVT and HVT?

Empirical α: vel. sat index

• Spectre 45nm Cadence GPDK

• HSPICE 32-28nm Synopsys EDK

• MOSFET: a 4-terminal device

• The current in (V)Saturation depends on VDS

Vout in2 WP2

• Time b/w an input transition and an output transition

Fall time Rise time 2.44

The delay of each stage treated separately

• C: take the average capacitance of a transistor as well

• The easy model Inverter

300 • With digital input on gate,

300 ▪ Approx. ON device

200 Vswing • Vswing = VDD – VM

VGS ≥ VT ID VGS = VDD

off Vo = VDD 600 VSat

• I = CdV/dt • Discharge in Triode

• Solvable equations, BUT • Empirical model

γ = Cpar / Cgate < 1 𝑪∝𝑾 (fF / µm)

• Works for monotonic waveforms

• The 50% point delay

• Account for the error by characterizing gate resistance

Too many R’s to keep track of…

• η is the slope factor (typical values: 0.1 – 0.2)

Another version of this model (stage n):

• β is the slope factor (typical values: find by simulation)

RP Calculate τPU and τPD:

• PMOS (no stack) is VSat

• Model is now RC network and depends on input