International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)

ISSN: 0976-1353 Volume 14 Issue 2 APRIL 2015

Power Analysis Of Digital Filters Implemented On

FPGAs
P.V.Gopikrishna1, Harsh Kamath2, Dr.G.H.Kulkarni3
1

Department of Electrical & Electronics Engg. Gogte Institute of Technology,Belgaum

2
Department Electrical & Electronics Engg. Gogte Institute of Technology,Belgaum
3
Professor, Department Electrical & Electronics Engg. Jain College of Engg., Belgaum
pvgopikrishna@git.edu
nick5199@gmail.com
ghkulkarni1@rediffmail.com

Abstract The proposed work is to analyze the power

consumption of Finite Impulse Response (FIR) filter under
different combinatorial modules. Under the considered modules
namely Parallel, serial
and
Distributed Arithmetic(DA)
architectures, effects of variation of clock frequency, leakage
capacitance, supply voltage are chosen to determine power
consumption and junction temperature. Each module is
simulated using Mentor Graphics ModelSim SE6.5 and the
results are presented.
KeywordsFPGAs; Distributed Arithmetic (DA); Power
Analysis; Finite Impulse Response (FIR) filter; Look-Up table
(LUT); Complementary Metal Oxide Semiconductor (CMOS).

I. INTRODUCTION
Basically the filters are designed by using finite number of
samples of impulse response which is termed as finite impulse
response (FIR) filters. It is a non- recursive, discrete time
filter. The output depends only on present and previous inputs.
It is to remove unwanted parts of the signal such as random
noise and also to extract useful parts of the signals such as the
components lying within a certain frequency range [8]. FIR
filters are inherently stable due to the fact that all the poles are
located at the origin and thus are located within the unit
circle.Since the digital filter circuits are extensively used in
audio signal processing, Image processing and communication
systems, it is desired to meet the specification such as speed,
area required on chip for implementation and power
consumption. The complexity in implementation increases
with the order of the filter. The digital filters are usually
implemented using Application Specific Integrated Circuit
(ASIC) or using a reprogrammable configurations such as
Field Programmable Gate Arrays (FPGAs). FPGAs offer a
very attractive solution that balance high flexibility, time-tomarket, cost and performance. This issue has been partially
solved with the new generation of low cost FPGAs that have
embedded DSP blocks.

Various parameters like area, delay, LUTs used etc., are

analyzed for the FIR filters implemented with or without
multipliers is presented[2][3][4]. An attempt to analyze the
power consumed by the FIR filters implemented on FPGAs is
made in this paper. The power analysis can be done directly on
the model or it can be done by giving some arbitrary input to
the circuit. The power analysis is done by two approaches:
static and probabilistic. This paper explains the various static
power analysis methods for the digital filters. We analyze the
power consumption of an Equiripple FIR filter for different
architectures. The area of the chip is further reduced by using
transposed structures. This causes the reduction in multipliers
required for implementation.
There are two types of power dissipation in CMOS circuits,
the static and the dynamic. The static power dissipation is
mostly due to the leakage currents and capacitance of the
circuit. The static power is always related to the physics of the
transistors used on board. In contrast, the dynamic power
consumption is dependent on the design, architecture, clock,
various signals and utilization of the board. The paper is
organized as follows. Section II deals with the FIR Filter
architectures, while the power analysis and temperature issues
are carried in section III and IV. Simulation is shown in section
V while results and conclusion are given in section VI.
II. FILTER ARCHITECTURE
Whenever we talk about filters, they are usually causal
systems. The conventional Finite Impulse Response filter is
shown in Fig.1. uses multipliers, adders and delay elements to
produce the required output. The multiplier which multiplies
input with the fixed content significantly occupies more place
to store their temporary values and also increases the power
consumption [3]. So, these multipliers are replaced with
memory based structures to reduce area.

1002

International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)

ISSN: 0976-1353 Volume 14 Issue 2 APRIL 2015

general an Nth order filter is characterized by N+1 coefficients,

N+1 multipliers and N number of adders. In the present work
the filter implemented is a 36th order low pass filter with a pass
band frequency of 400Hz, stop band frequency of 2000Hz and
stop band attenuation of 36 dB.

Fig.1. General FIR Filter structure

The filter is implemented with a fixed point quantization

shown inFig.2.where in the fractions are represented using
fixed number of bits with an implied binary point after the
most significant bit

Fig.2. Fixed point quantization

A. Serial and Parallel architectures

The parallel architecture shown in Fig. 3. is perhaps the
simplest way of implementation of FIR filters as they require
N number of multipliers and N+1 number of adders. The
parallel filters have high speed because all the coefficients
have their own multipliers and adders. So resetting operation
of elements is not too often as iteration does not occur more
often. In contrast the series architecture shown in Fig. 4. uses
only one multiplier and N+1 adders. The speed of this
architecture is comparatively low as the multipliers have to be
reset after every iteration. The serial architecture also involves
an N-bit counter to maintain synchronism with input samples
and coefficients.

Several architectures have been reported for memory-based

implementation of digital filters for Digital Signal Processing
Applications. One of the memory based technique is
Distributed Arithmetic (DA) [3]. In FIR filters, the multipliers
are replaced with the multiplier-less Distributed Arithmetic
based technique and it has gained popularity, for its highthroughput processing capability and increased regularity
which results in cost-effective and area-time efficient
computing structures. DA technique of implementing FIR filter
consists of Look-Up Table, shift registers and scaling
accumulator.
The design of filter corresponds to determination of
parameters of the transfer function that describe the desired
impulse response of the filter. Another way of representation of
digital filter is by constant coefficient difference equation. The
filter can be designed by determining these coefficients and
modeling them into the transfer function. The general constant
coefficient difference equation is given by

..

Fig.3. Parallel architecture of FIR filters

(1)

Where Ak and Bk are the coefficients.

The transfer function corresponding to above equation is given
by
Fig.4. Serial architecture of FIR filters

..

(2)

Since FIR filters have only zeros except a pole at z = 0, all a k

are
zero.
The
equation
the
becomes

..

(3)

The above equations involve adders, multipliers and

memory for storing previous coefficients. Resetting these
digital elements after every system iteration is important. In

Since the parallel architecture uses N number of multipliers

when compared to just one of serial architecture, the hardware
required to implement a parallel architecture is more than that
required for the serial architecture. In series there is only one
multiplier and N coefficients to be multiplied. So the clock
frequency required for serial is high. In our design the clock
frequency for serial was nearly 9 times the clock frequency
required for parallel architecture. To reduce the power
consumption, in the implementation which involves

1003

International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)

ISSN: 0976-1353 Volume 14 Issue 2 APRIL 2015
multipliers and adders, Xilinx has provided DSP slices
(Xtreme DSP48A). The number of slices utilized equal the
number of multipliers used. In this design 19 slices were used
for parallel architecture and 1 slice was used for series
architecture. The filter can further be optimized by using
hybrid architectures like partly serial and partly parallel.
B. Distrubuted Arithematic (DA)
In DA the multipliers are not present. The technique
involved the use of Look-Up tables (LUT), shift registers and
accumulators. Such algorithms are very useful in
implementation of filters on FPGAs. The traditional
implementation of filters on FPGAs turn out to be expensive
because of the number of multipliers used. The
implementation of filters require the accumulation of the
product of a series of successive multiplication. To implement
this, we need an adding unit and an additional unit called the
accumulator. This entire configuration is known as multiply
and accumulate or simply MAC. Although the multiplication
and addition in MAC are two different operations, they can be
both be executed in single operation cycle. Hence the clock
frequency required is not too high. The DA uses MAC
(Multiply-and-Accumulate) block shown in Fig.5 that is the
central processor. The size of LUT of implemented filter is
3488 bits.

Where, C is capacitance of circuit, V is voltage and f is

the frequency
Also there is leakage current contributing to the power
consumption. Some basic techniques that can be used to reduce
the power consumption are: 1. Reduction of supply voltage 2.
Reduction of circuit capacitance 3. Reduction of switching
frequency and 4. Reduction of leakage current.
A. Effect of capacitance
Most of the power dissipation is caused by capacitance.
Such capacitance in CMOS circuits is in the order of Pico
Farad. This capacitance may exist at the device level or
between two wires of the circuitry. TABLE I shows the effect
of Capacitance variation on Power dissipation.

TABLE I

Effect of Capacitance
Architecture

Capacitance

Power

5 pF
50 pF
500 pF

0.056 W
0.076 W
0.277 W

Series

5 pF
50 pF
500 pF

0.085 W
0.119 W
0.455 W

DA

5 pF
50 pF
500 pF

0.058 W
0.086 W
0.359 W

Parallel

B. Effects of switching frequency

The switching of clock frequency causes frequent charging
and discharging of capacitance hence dissipating power.
TABLE II shows the effect of variation clock frequency on
Power dissipation.
TABLE II

Fig.5. Basic MAC unit

Effect of Switching

III. POWER ANALYSIS

As the scale of integration improves, more transistors are
being packed into a chip. This leads to the growth of operating
frequency in turn resulting in power dissipation.
The biggest power dissipation in CMOS circuits is caused
by charging and discharging of capacitance and is dependent
on the switching frequency[9]. The power dissipated is given
by
P = CV2f

..

(4)

1004

Architecture

Frequency

Power

International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)

ISSN: 0976-1353 Volume 14 Issue 2 APRIL 2015
Parallel
Series

25 MHz
20 MHz
15 MHz

0.00196 W
0.00167 W
0.00139 W

25 MHz
20 MHz
15 MHZ

0.00234 W
0.00198 W
0.00162 W

1.2V, circuit capacitance of 5pF and at an ambient temperature

of 28 C and the results are shown in Tables IV, V and VI.
TABLE IV
Parallel Architecture

Logical Power = 0.00062 W

Data Power = 0.00115 W

DA

25 MHz
20 MHz
15 MHz

0.00126 W
0.00110 W
0.00095 W

Leakage Current
Dynamic Current = 0.005 A

Clock enable Power = 0.00036 W

Set/Reset Power = 0.00048 W

Static Current = 0.017 A

DSP Slices = 0.00101 W

I/O Power
Input Power = 0.00026 W
Output Power = 0.01188 W

C. Effect of supply voltaage

The supply voltage constitute to short circuit currents that
lead to power dissipation. The effect of these short circuit
currents is observed even if there is no load capacitance on a
transistor. The power dissipated is given by
Psc = Isc VDD
..
(5)
Where Isc is the short circuit current and VDD is the supply
voltage. Usually the systems are designed to work at fixed
supply voltage but recent research has made it possible for the
system to work under dynamically varying supply voltage[10],
hence reducing the power consumption. TABLE III shows the
effect of variation Supply voltage on Power dissipation.
TABLE V

TABLE III

Serial Architecture

Effect of supply voltage

Architecture

Parallel

Serial

Voltage

Power(Device)

0.8 V
1.2 V
1.5 V

0.036 W
0.055 W
0.136 W

0.8 V
1.2 V
1.5 V

0.024 W
0.048 W
0.127 W

Logical Power = 0.00030 W

Data Power = 0.00169 W

Leakage Current
Dynamic Current = 0.004 A

Clock enable Power = 0.00022 W

Set/Reset Power = 0.00049 W

Static Current = 0.017 A

DSP Slices = 0.00021 W

I/O Power

DA

0.8 V
1.2 V
1.5 V

Input Power = 0.00026 W

0.040 W
0.060 W
0.141 W

Output Power = 0.00545 W

TABLE VI

D. Other factors dissipating power

There are various other factors like the leakage currents
which is the current caused by reverse biased PN junction in
MOS transistor that have their effect on power. Other than
these factors there are many dynamic power consumption
caused by processing various signals. The analysis of all other
factors, for different architectures is made. The analysis is
made at a switching frequency of 25 MHz, an input voltage of

1005

Distributed Arithmetic
Leakage Current

International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)

ISSN: 0976-1353 Volume 14 Issue 2 APRIL 2015
Logical Power = 0.00099 W
Dynamic Current = 0.003 A

Data Power = 0.00104 W

Clock enable Power = 0.00005 W

Static Current = 0.017 A

Set/Reset Power = 0.00013 W

DSP Slices = Not Used
I/O Power
Input Power = 0.00026 W
Output Power = 0.01576 W

IV.

POWER AND TEMPEARATURE ISSUES

If the capacitance is more, the charging and discharging of

capacitor dissipates more power. This power loss is in the form
of heat. Due to the heat, the junction temperature raises. It is
important that ambient temperature is maintained for optimum
working of the device. This is shown in Table VII.
TABLE VII

Effect
temperature

of

Capacitance

capacitance

on

ambient

Fig.6. Filter response to White noise

To get an insight into the effects of supply voltage and

temperature on power dissipation, various graphs of
Temperature v/s Power are plotted at different values of
supply voltages as shown in Fig.7. to Fig.9.

Junction temperature
29.1 C

5 pF

29.5 C

50 pF
500 pF

33.3 C
V. SIMULATION

The filter is tested with two inputs, one is the chirp signal
Fig.5. and the other is white noise Fig.6. that occurs
undesirably in communication systems. The simulations were
made on Xilinx Spartan 6 (XC6SLX45T) package: FGG484.
The synthesizing application is Xilinx ISE 14.3 and waveform
analyzer is Mentor Graphics ModelSim SE 6.5.

Fig.7. Temperature v/s Power at 0.8 V

Fig.5. Filter response to Chirp signal

Fig.8. Temperature v/s Power at 1.2 V

1006

International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)

ISSN: 0976-1353 Volume 14 Issue 2 APRIL 2015
port of the filter. This effect of capacitance is negligible for
other ports. The serial architecture consumes the least power
because of presence of only one multiplier, but the frequency
of operation of series is high which causes some power
dissipation. An effective trade off must be made between
hardware and frequency if the filter is constructed by either
parallel or serial architectures. Also it is seen that reducing the
supply voltage brings down the power consumption
drastically. It is found that among the modules considered
Serial architecture consumes least power, but due to high
frequency requirements of Serial architecture, it is not
preferred. Though Distributed Arithmetic consumes
marginally more power as compared to Parallel architecture, it
is preferred for implementation on FPGAs as it does not use
DSP slices as compared to the Serial or Parallel architecture.
REFERENCES

Fig.9. Temperature v/s Power at 1.8 V

KR Santha and V. Vaidehi, Design of synchronous and asynchronous

architectures for DFT based adaptive equalizer, IEEE transaction.
[2] Y.A. Durrani and T. Riesgo, Power estimation techniques for DSP
architectures, Digital Signal Processing 19, pp.213-219, Elsevier 2009.
[3] Ramesh.R and Nathitya.R, realization of FIR filters using modified
distrubuted algorithm architecture, Signal and Image processing: An
Interational journal, Vol.3, Febrauary 2012.
[4] Pontus Astrom, Peter Nilson and Mats torrerson, Powe reduction in
custom CMOS digital filter structures, Analog IC and Signal
Processing, pp.97-105, Kluwer acedamic publishers 1999.
[5] S.Karunakaran and N.Kasthuri, Area and power efficient VLSI
architecture of FIR filters using asynchronous multiplier, British
journal of science, Vol.2, December 2011.
[6] N.S.Pal, H.Singh, S.Singh and R.K.Sarin, Implementation of high
speed FIR filter using serial and paralled Distrubuted algorithm,
International journal of computer applications, Vol.25, No.7, July 2011.
[7] Gary Yeap, Practical low-power digital VLSI design, Springer
publishers, 2009.
[8] Avtar Singh and S.Srinivasan, Digital Signal Processing
Implementation using DSP microprocessors,Cengage Learning,2004
[9] Bill Moyer, Low-power design for embedded processors, Proceedings
of the IEEE, Vol.89, Bo.11, November 2001.
[10] L.S. Nelson, Cees Niessen, Jens Sparso and Kees van Berkel, Lowpower operation using self-timed circuits and adaptive scaling of the
supply voltage, IEEE transactions on VLSI systems, Vol.2, No.4,
December 1994.
[1]

VI. CONCLUSION AND RESULTS

Table VIII shows the overall power consumption by different
architectures.
TABLE VIII

Power consumption for various architectures

Architecture

Total Power

Dynamic
Power

Static Power

Parallel

0.056 W

0.017 W

0.039 W

Serial

0.049 W

0.010 W

0.039 W

DA

0.058 W

0.020 W

0.039 W

It is observed that the static power is independent of design

methodology. The increase in power dissipation is due to
increase in capacitance which has its effect only on the output

1007