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Course Title

EE604 CMOS VLSI LAYOUT

DESIGN

CHAPTER 5:

FULL CHIP
INTEGRATION AND
TAPE OUT
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SYLLABUS
5.0 FULL CHIP INTEGRATION AND TAPE OUT
5.1 Explain full chip integration and tape out
5.1.1 Arrange Basic Full Chip Development

Cycle
5.2 Determine Basic Full Chip Layout Components
5.2.1 Identify Basic Tape Out Flow and

Activities involved
5.2.2 Classify Elements of Optical Proximity
Corrections (OPC)

5.2.3 Relate Dummification and CAMDEX

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What This Class Isnt

We will not cover/discuss:
This class is for general new VLSI engineer or
mask designers knowledge.
Many full chip/tapeout details not cover. Just
an overview.
Will not guarantee you are able to do Full
chip/Tapeout after this class.
No full chip layout/tapeout hands on exercises.

This class is not for Full chip layout/Tapeout

experts.

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5.1 Explain full chip integration

and tape out
What is Full Chip layout?
In simple terms, full chip layout is an integration of all layout
blocks/subblocks into a HUGE hierarchical blocks or Full
Chip. It is just like any other layout block EXCEPT more
complex in terms of
More # of Subcells/sub-blocks (can be both custom/APR)
More complex routings/# nets connecting each other sub-blocks.
More considerations in terms of layout or design for
manufacturing. E.g dummifications.
More quality checks needed.
More complex project management skill needed to balance
between PAS (Performance, Area, Schedule).
More resources and compute power needed as physically is
bigger.
Moremore.. More

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5.1.1 Arrange Basic Full Chip

Development Cycle
Where is Full Chip layout in the whole development cycle?
Initial Concept
Logic
Schematic Design

Full chip layout

and integration

Physical Layout
TAPEOUT

Mask Generation
Wafer Generation
Assembly
Testing
Shipment of Final Product
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5.1.1 Arrange Basic Full Chip

Development Cycle
Where Does Full Chip layout fit in the
whole development cycle?
Fullchip layout work started even before project
approved.
for feasibilities study and evaluations.
Fullchip actual layout work started in parallel with design.
Constantly update with latest design info
calibrate/change the floorplans or other global
requirements(e.g powers, clocks, timing etc)

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Fullchip layout activities PEAK from mid to end of design

project.
Test out all the fullchip layout/tapeout flows. (e.g FC
integration, FC verifications, fracturing, DFM
requirements)
Design/layout work converging to their requirements.
(FC floorplaning, power, clock etc..)

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5.2
Determine
Basic
Full
Chip
Full Chip Components
Layout Components
Full Chip Floorplan
IOs
-Inputs/Outputs buffers
-pads
-periphery

EBBs
-datapath
-memory
-analog special circuit

CBD
-Standard cells APR
-Sea Of Cells
-core
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5.2 Determine Basic Full Chip

Layout Components
Definitions
IOs :
Stands for Input/Outputs.
Main communications gateways which
transfer data between outside world and
internal functional units.
Consists of transistors, ESD structures,
diodes, resistors and other protection
devices.
Fully custom, hand-drawn layout.
Examples : USB, PCI, IDE buffers.

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5.2 Determine Basic Full Chip

Layout Components
Definitions
EBBs :
Stands for EmBedded Blocks.
Standalone functional circuits or units which
is critical to timings(shortest distance
possible), minimum area usage.
Normally custom hand-drawn layout.
Examples : RAM, ROM, PLLs,
CBDs:
Stands for Cell Based Designs.
Consists of EBBs and sea of standard cells
with certain functions and placed quite
randomly across an area of the chip.
Automatically Place and Route.
Examples : FARM execution units etc
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5.2 Determine Basic Full Chip

Layout Components
Full chip integration/assembly

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Introduction
Full chip floorplanning is a top down process
and bottom up fine tuning.
Setting the size, shape, and placements of
the blocks
Planning the power, clock and signal
routing
Repeating the process for each lower
level of hierarchy
This process continues until the EBB floor
plan is complete when the floor plan
reflects exact sizes and placements for all
the blocks in the EBB, and routing that
fully connects all these blocks.

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5.2 Determine Basic Full Chip

Layout Components
Full chip integration/assembly (cont.)
Full chip layout are integrated hierarchically.
Transitors standard cells ebbs
units clusters fullchip
Full chip Assembly is an ongoing parallel
task. It is performed not just once but at
frequent intervals.
Any block area change identified and
accommodated early as possible.
Pilot/test out all the full chip flows upfront
to avoid full chip in critical path.
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From transistors to FC layout

Logic Gate

Transitors

VCC

Sticks

ethel

P-diffusion

lucy

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DEMO

N-Diffusion

Layout

VSS

Cells to unit to cluster to

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5.2 Determine Basic Full Chip

Layout Components
Full Chip Consideration
Optimized die size
Setting the size, shape, and placements of
the blocks

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Pad and Core limited (balanced)

Database Hierarchies
Power plan and bussing
Planning the power, clock and signal routing
ESD scheme
CTGEN (Clock Tree Generation)
Data Flow, PV, Critical timing
Parasitic extraction

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5.2 Determine Basic Full Chip

Layout Components
Full Chip Quality Check
DFM (Design For Manufacturability)
Density in the chip
DFT (Design For Testability)
Fib cells
Probe cells -- a Mechanical access to the
signal (By BIG /marked M1 only with
proper keep-out and navigation aids.)
Bonus cells

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Generic Full chip Verification Flows

Fix the layout
database if the
verification is not
clean

After the fullchip

merged (30mins ~ 1 hr)

After the first

fullchip
merged. If the
layout fixes not
touching metal1
layers, then do
not required to
rerun notchfix

Run the notchfix hercules

to fill up all the metal1
notches in layout (1.5 hrs)

Stream out or merge the notchfix cell into the fullchip then submit jobs (30 mins)

XOR
2 hrs

DRCD
6 hrs

DRCBM
2 hrs

ERC
4 hrs

LVS
4 hrs

TFC
1.5 hrs

NAC
3 hrs

C- thru
2hrs

NAC
3 hrs

C- thru
2 hrs

NO

Clean?

YES

Metals
Dummification.
( 4hrs for each layer)

Risk Fracture
database

DRCD
6 hrs

TAPEOUT

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DRCBM
2 hrs

ERC
4 hrs

YES

LVS
4 hrs

Clean ?

TFC
1.5 hrs

NO

Fix the Errors caused by

metal
dummification flow

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Full chip layout Quiz

1. When is full chip layout activities
started/peak?
a) before project even approved.
b) In parallel with other layout sub-designs.
c) in the middle and end of the projects.
d) All of the above.

2. Full chip layout is assemble in many

hierarchies?
a) True
b) False

3. Full chip most likely fully integrated and clean

before which steps in the diagram.
a) 1
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b) 2

c) 3

d) 4

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Initial Concept
Logic
Schematic Design
Physical Layout
TAPEOUT

Mask Generation
Wafer Generation
Assembly
Testing
Shipment of Final Product
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5.2.1 Identify Basic Tape Out Flow

and Activities involved
What is Tapeout?
Tapeout is the completion of a major milestone in
the whole IC development cycle whereby :
Tape In
All layout done. Design timing/power etc. met. Full
chip layout assembled and verified. Database sent
for fracturing.
Fracture
Circuit layout is translated into Electron Beam (Ebeam) readable data for process of mask
generation by Fab
Tapeout
Release of Fracture data to Mask vendors, this is
the start of manufacturing of the product
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5.2.1 Identify Basic Tape Out Flow

and Activities involved
Synthesize and final check
database for Tapeout

My Design done

Send to Mask shop

for Mask generation

Fabrication

1
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15

Tapeout Process

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TapeOut in the Design Flow

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The Product Design Mask Designers

- Design rules
Cycle
(who responsible for what?)

Logic and circuit

design engineers
Circuit

Layout

Logic

Verification
Concept

Tapeout

FAB PE
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Mask Shop runsets

Process rules only

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5.2.1 Identify Basic Tape Out Flow

and Activities involved
Types of TapeOuts
New Product: A-stepping. (first time, brand
new: A0)
New Stepping: B0,C0, A full set with design
change to an existing product. All layers are
taped out.
Retrofit (Dash steppings):A1,A2, B1, B2...
Some layers are modified on an existing product.
Only those layers that are changed are taped
out.
FEW layers are changed => ALL other layers
are XOR to Ensure NO Change.
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5.2.1 Identify Basic Tape Out Flow

and Activities involved
Key Players in Tapeout
Project Planner
Design Engineers (physical device owners)
Frame Cell Set Owners (frame owners)
FAB Engineers (process owners)
Tapeout Engineer (coordinates TO meetings and
owns the conversion process of the device/frame to mask
shop)

Legal (approves the copyright/logo)

Assembly and Package Engineer(Interface
Units hardware)
And YOU?

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5.2.1 Identify Basic Tape Out Flow

and Activities involved
Tape In

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All layout done. Full chip assembled. Verification CLEAN!!

Layout audit/review done with design engineers and expert
users.
Design timing, power, clocks requirements met!!
Went through few Dry runs (MOCK tapeouts) to test out the
fracturing, DFM flows, machines usage etc.
Dry runs (MOCKs): Pre-Tapeout activities to check and
decide the proper TapeOut tools/flows and machines.
Enables best estimation for required resources
Tapeout deals with the whole Chip at a time, this required
large CPU, huge disks & memory.
30K device ->> 250K -> 1M -> 10 -> 30 M devices.
Memory of ; 0.5G -> 1G -> 2G -> 4G -> 8G. Max
mem?
All checklists(e.g layout) or waivers(e.g drcs) signed-off by
respective owners..

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5.2.1 Identify Basic Tape Out Flow

and Activities involved
Tape Out Flow
1. Create Golden DB
2. Run Fullchip Verification jobs in parallel (e.g.
22 jobs)
3. FC verification results analyzed, debugged and
fixed.
4. Send Stream file (GDSII) to Tapeout Team for
fracturing and release to Mask Shop for mask
generation.
5. Archive the Whole Data-Base and tools.
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5.2.1 Identify Basic Tape Out Flow

and Activities involved
Fracture Process/Verification
Fracture Purpose: Flatten the data by removing
the hierarchy. (.stm), Breaks up polygons to
rectangles/ trapezoids that the Ebeam machine can
read.
OPC: (Optical Proximity Correction) Improves yield
in synthesis flow(dog ears).
Fracture Verification: Validate that theres no data
dropped or drcs after fracture (MRC). Also, for
retrofits, to validate changes between old stepping
and current changes.
MRC: Manufacturing Rule Checker. Checks
minimum spacing,end of line, runs reverse actos
(dropped data)
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Basic fracturing process

The fracture flows add sizing (vendor and
process). It also generates the synthesis
layers. When fracture is completed, the
product is tapeout.

Basic Fracturing process:

Fracture
Sizing
Synthesis

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Fracture
Drawn database showing poly, diffusion regions, and
contacts

The fracture process will convert individual drawn

layers according Process Design Rules
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Fracture - Sizing
Fracture will alter (size) the data to meet the
requirements of the process and Fab.
Data sized
up by 0.2
m per
side

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Synthesis
AND poly N+
npoly
AND poly P+
ppoly
OR npoly
ppoly gate

Metal
ppoly

npoly
P+

N+
Poly

pWell

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New layers generated from existing drawn and/or

generated layers.
Blocking mask, implant mask and well masks are
synthesized.
Utilize digital logic synthesis to generate the layers (AND,
OR, NOT etc..)

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Fracture - CF Mask
Poly fractures to a clear field mask

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5.2.2 Classify Elements of Optical

Proximity Corrections (OPC)
What is OPC?
Why OPC and how it is done?
How do Mask Designers can help to
improve?
OPC guidelines

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5.2.2 Classify Elements of Optical

Proximity Corrections (OPC)
What is OPC?

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OPC stands for Optical Proximity Corrections.

Flow manipulates the drawn and/or synthesized
geometries to improve FAB patterns.

Simple drawn
geometries are
comprehensively
modified using
post-layout flows
6x increase in vertices means larger database sizes

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5.2.2 Classify Elements of Optical

Proximity Corrections (OPC)
Why OPC and how it is done?

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Dogears are added to line ends to

reduce exterior corner rounding.
Cutouts are subtracted from interior
corners to reduce interior corner
rounding.

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5.2.2 Classify Elements of Optical

Proximity Corrections (OPC)

DRAWN

What We draw is
Not what we get.

ACTUAL
Silicon

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Lines shorter
Curves
bulge/larger

What You See IS

(almost)What You
Get

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Rule Based OPC:

Rule

Input

Output

2-D corrections
applied

Uncorrected Data

Model Based OPC:

Uncorrected Data
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Corrected Data
1-D and 2-D
corrections applied

Corrected Data

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5.2.2 Classify Elements of Optical

Proximity Corrections (OPC)
OPC Guidelines
1. Minimize the total number of jog segments
Device layout
2. Avoid small jog segments
Interior corners on opposite sides of same
line
3. Avoid interior diffusion corners next to gates
Minimize such occurrences
4. Avoid horseshoe layouts
Increase spacing between end of line
segment and opposite feature
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5.2.2 Classify Elements of Optical

Proximity Corrections (OPC)
1. Minimize the Total Number of Jog Segments
Metal

More Vertices

More Vertices
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Fewer Vertices

Fewer Vertices

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5.2.2 Classify Elements of Optical

Proximity Corrections (OPC)
Reduce vertices
Poly

More Vertices

Fewer Vertices

More Vertices
Fewer Vertices

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5.2.2 Classify Elements of Optical

Proximity Corrections (OPC)
2. Avoid small jogs
Stub and inside metal corner space.
Risk: Yield
Type of issue: OPC
Fix type: add material to not fit the problematic values

Inside corner space

Inside corner space

Metal stub

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5.2.2 Classify Elements of Optical

Proximity Corrections (OPC)
3. Interior Diffusion Corner Recommendations
Minimize number of interior diffusion corners

Original Layout

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Better

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5.2.2 Classify Elements of Optical

Proximity Corrections (OPC)
3. Interior Diffusion Corner Recommendations
Minimize number of interior diffusion corners

Original Layout
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Better

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5.2.2 Classify Elements of Optical

Proximity Corrections (OPC)
4.0 Avoid Horseshoe Layouts
Avoid layouts where line segments are
enclosed on three sides at minimum space
Increase the distance between the end of the
line segment and the enclosing horseshoe

Applies to diffusion,
poly, and metal layers

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5.2.3 Relate Dummification and

CAMDEX
What is Dummification?
Process of generating dummies - metal,
poly, diffusions in the layout design.
Dummies have no electrical representation but
have physical impact/interference to circuit
performance
Special circuit like PLL analog layout,
differential amplifiers etc..
Dummification are generated during design
phase (mainly metals) and also during
fracturing flow (mainly poly and diffusions).
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5.2.3 Relate Dummification and

CAMDEX
Dummification
Array of dummies
generated with
specified size and
spacing
Dummies cleaned up
to be a specified
keepaway distance
from drawn layers.

New Process have 2 sizes of STR dummy

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5.2.3 Relate Dummification and

CAMDEX
Synthesis Flow Generated STR Dummies

Small
Dummies

Large Dummies

STR Fracture Data

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5.2.3 Relate Dummification and

CAMDEX
Dummification Line/Space Dimensions
High Pattern Density

Max line width with min

spacing causes high
erosion rate

Lower Pattern Density

Similar line width and

spacing avoids high
erosion rate
Preferred

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5.2.3 Relate Dummification and

CAMDEX
Purpose of Dummification
1. For Pattern/density uniformity during
fabrication process such as oxidation,
metallization and etc.
2. Can increase ability to control smaller transistor
dimensions (increasingly influenced by the
distribution of pattern density).
The number of process steps influenced by
pattern density is growing
Lithography

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Etch
Polish
Annealing

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5.2.3 Relate Dummification and

CAMDEX
Purpose of Dummification (cont.)
3. Each generation of technology will
improve design rules that strict
pattern density.
However, there are still density
issues that are difficult to cover with
design rules

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5.2.3 Relate Dummification and

CAMDEX
STR Polish Breakthrough
Nitride
Silicon

Oxide

Oxide

Slower Polish Rate

Slower Polish Rate

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Polish Breakthrough
Polish Breakthrough

No Remaining Nitride!

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5.2.3 Relate Dummification and

CAMDEX

What is CAMDEX
CAMDEX stands for CATS based Metal Density
Extraction (CATS stands for Computer Aided
Transcription System)
Metal Density and CAMDEX- Pre-Tapeout layers
density review.(STR/PLY/Metals)
CAMDEX provides die level modeling of mask
layer pattern density and polish thickness
variation

CAMDEX pattern density and polish simulation

plots are one of the primary tools the factories
use to assess the manufacturability of a given
device design prior to final tapeout.
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5.2.3 Relate Dummification and

CAMDEX

What is CAMDEX

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5.2.3 Relate Dummification and

CAMDEX

What is CAMDEX
Example:

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Full chip tapeout Quiz

1. What is/are the reason(s) to do dummification?
a) To ensure pattern/density uniformity during
fabrication.
b) To ensure higher wafer yield.
c) To ensure the IC can be fabricated correctly.
d) All of the above.
2. Below which process is NOT a fabrication
process?
a) Lithography
c) Polish
b) Abrasive
d) Etch
e) Anneal
3. Which layout is better?
3.1
a) 1
b) 2
c) 3
3.2
a) 1
b) 2
3.3
a) 1
b) 2
c) 3
d) 4
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Metal

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Metal

Diffusion

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EE604 CMOS VLSI LAYOUT DESIGN

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