Digital Electronics Combinational Tests PDF

Chapter 1
Analog to Digital Conversion
1.
1p
The process of converting the analog signal into a digital signal

consists of:
a.) converting a continuous signal to a digital number
b.) converting a broken signal to a digital number
c.) converting a continuous signal to a analog number
d.) converting a broken signal to a analog number
Correct answer a.)
2.
1p
The figure below shows:
a.) block diagram of an analog filter

b.) block diagram of a digital analog to converter;
c.) block diagram of a digital filter;
d.) block diagram of an analog to digital converter
Correct answer d.)
3.
2p
From a formal standpoint, the A-D conversion involves only:

a.) sampling followed by quantification of the analog signal;
b.) sampling of the analog signal;
c.) quantification of the analog signal
d.) quantification followed by sampling of the analog signal;
Correct answer a.)
4.
2p
Sampling an analog signal means means:

a.)
that the sample selection is based on the average value of the

1
signal
b.) that the sample selection is based on signal peaks
c.) taking of samples of the signal at some intervals
d.) taking of samples of the signal at predetermined intervals
Correct answer d.)
5.
1p
Figure 1.1 shows a digital anolog converter. Digital word D0 - D7

is:
Figura 1.1
a.) input signal

b.) output signal
c.) control signal
d.) synchronization signal
Correct answer b.)
6.
3p
Figure 1.1 shows a digital anolog converter. The full scale voltage
range (VF) is:
Figura 1.1
a.)
b.)
c.)
d.)
VF = VREF VREF+
VREF+
VREF
VF = VREF+ VREF _
VF =
VF =
VREF
VREF+
2
Correct answer a.)

7.
3p
Assume the digital word 10010011. The Most Significant Bit

(MSB) is:
a.) All bits with value "1"
b.)
c.)
d.) All bits with value "0"

Correct answer b.)
8.
3p
Assume the digital word 10010011. The Least Significant Bit

(LSB) is:
a.) All bits with value "1"
b.)
c.)
d.) All bits with value "0"

Correct answer c.)
9.
3p
Binary number N=1010

representation:
a.) N=10 D
b.) N=2 D
c.) N=14 D
d.) N10=6 D
Correct answer a.)
has
the
following
decimal
10.
3p
Binary number
representation:
a.) N=10 D
b.) N=2 D
c.) N=14 D
d.) N=6 D
has
the
following
decimal
N=0010
Correct answer b.)

11
3p
Binary number
representation:
a.) N=10 D
b.) N=2 D
c.) N=14 D
d.) N=6 D
Correct answer c.)
N=1110
has
the
following
decimal
12
3p
Binary number N=0110

representation:
a.) N=10 D
b.) N=2 D
c.) N=14 D
d.) N=6 D
Correct answer d.)
has
the
following
decimal
13.
3p
Binary number N=1010 B has the following hexadecimal

representation:
a.) N=A H
b.) N=2 H
c.) N=E D
d.) N=6 D
Correct answer a.)
14.
3p

representation:
a.) N=A H
b.) N=2 H
c.) N=E D
d.) N=6 D
Correct answer b.)
14.
3p

representation:
a.) N=A H
b.) N=2 H
c.) N=E D
d.) N=6 D
Correct answer c.)
4
15.
3p

representation:
a.) N=A H
b.) N=2 H
c.) N=E D
d.) N=6 D
Correct answer d.)
16.
3p
Hexadecimal number N=A87C H may be encoded, using as

hexadecimal to binary code (8421) as:
a.) 1010 1000 0111 1100
b.) 11001010 0011 1000
c.) 1010 0011 1000 0001
d.) 1010 0001 1000 0101
Correct answer a.)
17.
3p
Hexadecimal number N=C001 H may be encoded, using as

hexadecimal to binary code (8421) as:
a.) 1010 0000 0000 1000
b.) 1010 0000 0000 0001
c.) 0001 0000 0000 1010
d.) 1101 1111 0000 0110
Correct answer b.)
Chapter 2
Combinational Circuits Representing
1.
1p
Figure 2.1 shows the block diagram of a combinational logic

circuit.
X1
X2
Y1
Y2
CLC
Xn
Ym
Figure 2.1
The set X = {X1, X 2 , KX n } is:

a.) the set of states
b.) the set of inputs
c.) the set of outputs
d.) the set of input-output functions
Correct answer b.)
2.
1p

circuit.
X1
X2
Y1
Y2
CLC
Xn
Ym
Figure 2.1
The set Y = {Y1 , Y2 , K Ym } is:

Correct answer c.)
3.

7
1p
circuit.
X1
X2
Y1
Y2
CLC
Xn
Ym
Figure 2.1
Knowing that:
Y1 = f1(X1, X 2 , ... , X n )
Y2 = f 2 (X1, X 2 , ... , X n )
M
Ym = f m (X1 , X 2 , ... , X n )
The set f = {f1 , f 2 , K f m } is:
Correct answer d.)
4.
2p

circuit.
X1
X2
Y1
Y2
CLC
Xn
Ym
Figure 2.1
Noting:
X = {X1 , X 2 , K X n }
Y = {Y1 , Y2 , K Ym }
f = {f1 , f 2 , K f m }
where:
X
the set of inputs
Y
the set of outputs
f
the set of input-output functions.
the combinational logic circuit is defined as:
a.)
Sc = {X, Y, f }
8
b.)
S c = {X, Y}
c.)
S c = {X, f }
S c = {Y, f }
Correct answer a.)
d.)
10
Chapter 3
Logic Gates
1.
1p
The symbol of an AND logic gate, ANSI standard is:
a.)
b.)
c.)
d.)
Correct answer a.)
2.
1p
The symbol of a NAND logic gate, ANSI standard is:
a.)
b.)
c.)
d.)
Correct answer c.)
3.
1p
The symbol of an OR logic gate, ANSI standard is:
a.)
b.)
11
c.)
d.)
Correct answer b.)
4.
1p
The symbol of a NOR logic gate, ANSI standard is:
a.)
b.)
c.)
d.)
Correct answer d.)
5.
1p
The symbol of an AND logic gate, DIN standard is:
a.)
b.)
c.)
d.)
Correct answer a.)
6.
1p
The symbol of a NAND logic gate, DIN standard is:
a.)
b.)
c.)
d.)
12
Correct answer c.)

7.
1p
The symbol of an OR logic gate, DIN standard is:
a.)
b.)
c.)
d.)
Correct answer b.)
8.
1p
The symbol of a NOR logic gate, DIN standard is:
a.)
b.)
c.)
d.)
Correct answer d.)
9.
1p
The symbol of a NOT logic gate, DIN standard is:
a.)
b.)
c.)
d.)
Correct answer d.)
10.
1p
The symbol of a NAND logic gate, ANSI standard is:
13
a.)
b.)
c.)
d.)
Correct answer c.)
11.
1p
The figure shows the symbol of a logic gate, type:
a.) AND standard ANSI;

b.) AND standard DIN;
c.) NAND standard ANSI;
d.) NAND standard DIN;
Correct answer a.)
12.
1p

Correct answer b.)
13.
1p

Correct answer c.)
14
14.
1p

Correct answer d.)
15.
1p
a.) OR standard ANSI;

b.) OR standard DIN;
c.) NOR standard ANSI;
d.) NOR standard DIN;
Correct answer a.)
16.
1p

Correct answer b.)
17.
1p

Correct answer c.)
15
18.
1p

Correct answer d.)
19.
1p

c.) NOT standard ANSI;
d.) NOT standard DIN;
Correct answer c.)
20.
1p

c.) NOT standard ANSI;
d.) NOT standard DIN;
Correct answer d.)
21.
4p
The logic function implemented by an AND gate is:

a.)
b.)
c.)
d.)
Y( A, B) = AB
Y( A, B) = AB
Y( A, B) = A + B
Y( A, B) = A + B
Correct answer a.)
22.
4p
The logic function implemented by a NAND gate is:

16
a.)
b.)
c.)
d.)
Y( A, B) = AB
Y( A, B) = AB
Y( A, B) = A + B
Y( A, B) = A + B
Correct answer b.)
23.
4p
The logic function implemented by an OR gate is:
a.)
b.)
c.)
d.)
Y( A, B) = AB
Y( A, B) = AB
Y( A, B) = A + B
Y( A, B) = A + B
Correct answer c.)
24.
4p
The logic function implemented by a NOR gate is:
a.)
b.)
c.)
d.)
Y( A, B) = AB
Y( A, B) = AB
Y( A, B) = A + B
Y( A, B) = A + B
Correct answer d.)
25.
1p
The logic function implemented by a NOT gate is:
a.)
b.)
c.)
d.)
Y( A, B) = AB
Y( A, B) = AB
Y (A) = A
Y (A ) = A
Correct answer d.)
26.
3p
The logic function Y(A, B) = AB is implemented using:
a.)
b.)
c.)
AND gate
NAND gate
OR gate
17
d.) NOR gate

Correct answer a.)
27.
3p
The logic function Y (A, B) = AB is implemented using:
a.) AND gate

b.) NAND gate
c.) OR gate
d.) NOR gate
Correct answer b.)
28.
3p
The logic function Y (A, B) = A + B is implemented using:
a.) AND gate

b.) NAND gate
c.) OR gate
d.) NOR gate
Correct answer c.)
29.
3p
The logic function Y (A, B) = A + B is implemented using:
a.) AND gate

b.) NAND gate
c.) OR gate
d.) NOR gate
Correct answer d.)
30.
1p
The logic function Y (A) = A is implemented using:
a.) NOT gate

b.) NAND gate
c.) OR gate
d.) NOR gate
Correct answer a.)
31.
4p
AND logic function is described by the truth table noted:
a.)
Inputs
X1 X2
0
0
18
Output
Y
0
0
1
1
1
0
1
0
0
1
b.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
1
1
1
0
c.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
0
1
1
1
d.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
1
0
0
0
Correct answer a.)

32.
4p
NAND logic function is described by the truth table noted:
a.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
19
Output
Y
0
0
0
1
b.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
1
1
1
0
c.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
0
1
1
1
d.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
1
0
0
0
Correct answer b.)

33.
4p
OR logic function is described by the truth table noted:
a.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
0
0
0
1
b.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
1
1
1
0
20
c.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
0
1
1
1
d.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
1
0
0
0
Correct answer c.)

34.
4p
NOR logic function is described by the truth table noted:

a.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
0
0
0
1
b.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
1
1
1
0
c.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
0
1
1
1
21
d.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
1
0
0
0
Correct answer d.)

35.
3p
Funcia logic NOT este descris de tabelul de adevr notat::

a.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
0
0
0
1
b.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
1
1
1
0
c.)
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
0
1
1
1
d.)
Input
X
0
1
Output
Y
1
0
Correct answer d.)
22
36.
4p
The truth table presented below, describes the logical function:
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
0
0
0
1
a.) AND
b.) NAND
c.) OR
d.) NOR
Correct answer a.)
37.
4p
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
1
1
1
0
a.) AND
b.) NAND
c.) OR
d.) NOR
Correct answer b.)
38.
4p
Inputs
X1 X2
0
0
0
1
1
0
1
1
a.)
b.)
AND
NAND
23
Output
Y
0
1
1
1
c.) OR
d.) NOR
Correct answer c.)
39.
4p
Inputs
X1 X2
0
0
0
1
1
0
1
1
Output
Y
1
0
0
0
a.) AND
b.) NAND
c.) OR
d.) NOR
Correct answer d.)
40.
2p
Inputs
X
0
1
Output
Y
1
0
a.) AND
b.) NAND
c.) NOT
d.) NOR
Correct answer c)
41.
4p
The waveforms, associated with an AND-type logic gate, are

shown in figure:
a.)
A
24
b.)
A
c.)
A
B
Y
d.)
A
Correct answer a)
42.
4p
The waveforms, associated with a NAND-type logic gate, are

shown in figure:
a.)
A
b.)
A
25
c.)
A
B
Y
d.)
A
Correct answer b)
43.
4p
The waveforms, associated with an OR-type logic gate, are shown

in figure:
a.)
A
b.)
A
c.)
A
B
Y
26
d.)
A
Correct answer c)
44.
4p
The waveforms, associated with a NOR-type logic gate, are shown

in figure:
a.)
A
b.)
A
c.)
A
B
Y
d.)
A
Correct answer d)
45.
2p
The waveforms, associated with a NOT-type logic gate, are shown

in figure:
27
a.)
A
b.)
A
c.)
A
B
Y
d.)
A
Correct answer b)
46.
4p
The figure presented below shows the waveforms of a logic gate

type:
A
0
1
a.) AND
b.) NAND
c.) OR
d.) NOR
Correct answer a)
28
47.
4p

type:
A
a.) AND
b.) NAND
c.) OR
d.) NOR
Correct answer b)
48.
4p

type:
B
Y
a.) AND
b.) NAND
c.) OR
d.) NOR
Correct answer c)
49.
4p

type:
a.)
b.)
0
1
AND
NAND
29
c.) OR
d.) NOR
Correct answer d)
50.
2p

type:
A
a.) AND
b.) NAND
c.) NOT
d.) NOR
Correct answer c)
30
Chapter 4
Logic Gates - Problems
1.
4p
The logic gate Y = ( X1X 2 )X 3 may be implemented by the circuit:
a.)
b.)
c.)
d.)
Correct answer a)
2.
4p
The logic gate Y = ( X1 X 2 ) X 3 may be implemented by the circuit:
a.)
b.)
c.)
31
d.)
Correct answer b)
3.
4p
The logic gate Y = ( X1 + X 2 ) X 3 may be implemented by the

circuit:
a.)
b.)
c.)
d.)
Correct answer c)
4.
4p
The logic gate Y = ( X1 + X 2 ) X 3 may be implemented by the

circuit:
a.)
b.)
c.)
d.)
Correct answer d)
32
5.
4p
The circuit shown in the figure below performs logic function:
a.)
Y = ( X1 + X 2 ) X 3
b.)
Y = X1X 2 X 3
c.)
Y = ( X1 + X 2 ) X 3
d.)
Y = ( X1 + X 2 ) X 3
Correct answer a)
6.
4p
a.)
Y = ( X1 + X 2 ) X 3
b.)
Y = X1X 2 X 3
c.)
Y = ( X1 + X 2 ) X 3
d.)
Y = ( X1 + X 2 ) X 3
Correct answer b)
7.
4p
a.)
Y = ( X1 + X 2 ) X 3
b.)
Y = X1X 2 X 3
c.)
Y = ( X1 + X 2 ) X 3
d.)
Y = ( X1 + X 2 ) X 3
Correct answer c)
33
8.
4p
a.)
Y = ( X1 + X 2 ) X 3
b.)
Y = X1X 2 X 3
c.)
Y = ( X1 + X 2 ) X 3
d.)
Y = ( X1 + X 2 ) X 3
Correct answer d)
9.
4p
The following waveforms are generated by the circuit:
A
B
C
Y
a.)
b.)
c.)
d.)
Correct answer a)
34
Chapter 5
Multiplexers, Demultiplexers
1.
2p
Assume a logic circuit. Lets note:

[X]-input word
[Y]-output word
[S]-selection word
In this case, the multiplexer is a circuit
a.) with "n" inputs and one output, which performs the function of a
rotary switch connected as shown:
b.)
with one input and "n" outputs, which performs the function of a
c.)
with "n" inputs and "m" outputs, which performs the function of a
rotary switch controlled by the output signal
d.)
35
rotary switch controlled by the input signal
Correct answer a)
2.
2p
Assume a logic circuit. Lets note:

[X]-input word
[Y]-output word
[S]-selection word
In this case, the demultiplexer is a circuit
a.) with "n" inputs and one output, which performs the function of a
b.)
with one input and "n" outputs, which performs the function of a
c.)
rotary switch controlled by the output signal
36
d.)
rotary switch controlled by the input signal
Correct answer b)
3.
3p
The symbol of a multiplexer (4 bits ANSI standard) is:
a.)
b.)
c.)
d.)
Correct answer a)
4.
3p
The symbol of a multiplexer (4 bits DIN standard) is:
a.)
b.)
37
c.)
d.)
Correct answer b)
5.
3p
The symbol of a demultiplexer (4 bits DIN standard) is:
a.)
b.)
c.)
d.)
Correct answer d)
6.
3p
The symbol of a demultiplexer (4 bits ANSI standard) is:
a.)
b.)
38
c.)
d.)
Correct answer c)
7.)
1p
The figure presented below shows the symbol of:
a.) multiplexer, standard ANSI

b.) multiplexer, standard DIN
c.) demultiplexer, standard ANSI
d.) demultiplexer, standard DIN
Correct answer a)
8.)
1p

Correct answer b)
9.
1p
39

Correct answer c)
10.
1p

Correct answer d)
11.
3p
Figure 5.1 presents the schematic diagram of a multiplexer 4 to 1.

Figure 5.2 shows the simplified truth table associated.
Figure 5.1
Figure 5.2
If the selection word is {S0, S1 }={0, 0}, then:

a.)
Y = X0
b.)
c.)
d.)
Y = X1
Y = X2
Y = X3
Correct answer a)
12.

40
3p
Figure 5.1
Figure 5.2

a.)
Y = X0
b.)
Y = X1
c.)
Y = X2
d.)
Y = X3
Correct answer b)
13.
3p

Figure 5.1
Figure 5.2

a.)
Y = X0
b.)
Y = X1
c.)
d.)
Y = X2
Y = X3
Correct answer c)
14.
3p

Figure 5.1
Figure 5.2

41
a.)
b.)
c.)
d.)
Y = X0
Y = X1
Y = X2
Y = X3
Correct answer d)
15.
3p
Figure 5.3 presents the schematic diagram of a demultiplexer 1 to

4. Figure 5.4 shows the simplified truth table associated.
Figure 5.3
Figure 5.4

a.)
{Y0 , Y1 Y2 Y3} = {X 0 , 1, 1, 1}
b.)
c.)
d.)
{Y0 , Y1 Y2 Y3} = {1, X1 , 1, 1}

{Y0 , Y1 Y2 Y3} = {1, 1, X 2 , 1}
{Y0 , Y1 Y2 Y3} = {1, 1, 1, X 3}
Correct answer a)
16.
3p

Figure 5.3
Figure 5.4

a.)
{Y0 , Y1 Y2 Y3} = {X 0 , 1, 1, 1}
b.)
c.)
d.)
{Y0 , Y1 Y2 Y3} = {1, X1 , 1, 1}

{Y0 , Y1 Y2 Y3} = {1, 1, X 2 , 1}
{Y0 , Y1 Y2 Y3} = {1, 1, 1, X 3}
Correct answer b)
42
17.
3p

Figure 5.3
Figure 5.4

a.)
{Y0 , Y1 Y2 Y3} = {X 0 , 1, 1, 1}
b.) {Y0 , Y1 Y2 Y3} = {1, X1 , 1, 1}

c.)
{Y0 , Y1 Y2 Y3} = {1, 1, X 2 , 1}
d.) {Y0 , Y1 Y2 Y3} = {1, 1, 1, X 3}
Correct answer c)
18.
3p

Figure 5.3
Figure 5.4

a.)
{Y0 , Y1 Y2 Y3} = {X 0 , 1, 1, 1}
b.)
c.)
d.)
{Y0 , Y1 Y2 Y3} = {1, X1 , 1, 1}

{Y0 , Y1 Y2 Y3} = {1, 1, X 2 , 1}
{Y0 , Y1 Y2 Y3} = {1, 1, 1, X 3}
Correct answer d)
19.
4p
Assume a 4 to 1 multiplexer. Lets note:

{X0, X1 , X2, X3}-inputs;
{S0, S1 }-selection word;
Youtput.
The truth table is presented below:
43
If the selection word is {S0, S1}={0, 0}, the waveforms associated are
presented in figure:
a.)
X0
X1
X2
X3
b.)
X0
X1
X2
X3
c.)
X0
X1
X2
X3
d.)
X0
X1
X2
X3
Correct answer a)
20.
4p

Youtput.
44
a.)
X0
X1
X2
X3
b.)
X0
X1
X2
X3
c.)
X0
X1
X2
X3
d.)
X0
X1
X2
X3
Correct answer b)
21.
4p

Youtput.
45
a.)
X0
X1
X2
X3
b.)
X0
X1
X2
X3
c.)
X0
X1
X2
X3
d.)
X0
X1
X2
X3
Correct answer c)
22.
4p

Youtput.
46
a.)
X0
X1
X2
X3
b.)
X0
X1
X2
X3
c.)
X0
X1
X2
X3
d.)
X0
X1
X2
X3
Correct answer d)
23.
4p

Youtput.
47
The waveforms presented below are obtained if the selection word

is:
X0
X1
X2
X3
a.)
b.)
c.)
d.)
{S0 , S1} = {0, 0}

{S0 , S1} = {1, 0}
{S0 , S1} = {0, 1}
{S0 , S1} = {1, 1}
Correct answer a.)
24.
4p

Youtput.

is:
X0
X1
X2
X3
a.)
b.)
{S0 , S1} = {0, 0}

{S0 , S1} = {1, 0}
48
c.)
d.)
{S0 , S1} = {0, 1}

{S0 , S1} = {1, 1}
Correct answer b.)
25.
4p

Youtput.

is:
X0
X1
X2
X3
a.)
{S0 , S1} = {0, 0}
b.) {S0 , S1} = {1, 0}
c.)
{S0 , S1} = {0, 1}
d.) {S0 , S1} = {1, 1}
Correct answer c.)
26.
4p

Youtput.

49
is:
X0
X1
X2
X3
a.)
b.)
c.)
d.)
{S0 , S1} = {0, 0}

{S0 , S1} = {1, 0}
{S0 , S1} = {0, 1}
{S0 , S1} = {1, 1}
Correct answer d.)
50
Chapter 6
Decoders, Multiplexers and Demultiplexers
Problems
1.
4p
Figure6.1 shows how to connect the BCD seven segments decoder

with a seven segments display cell. LSB is X0. MSB is X3. If
{X0,X1,X2,X3}={0,1,1,0} then the display cell will show:
Figure 6.1
a.) 2
b.) 6
c.) 4
d.) 8
Correct answer b)
2.
4p
Figure 6.1 shows how to connect the BCD - seven segments decoder
Figure 6.1
a.) 2
b.) 6
c.) 4
d.) 8
Correct answer a)
51
3.
4p
Figure 6.1 shows how to connect the BCD - seven segments decoder
Figure 6.1
a.) 2
b.) 6
c.) 4
d.) 8
Correct answer d)
4.
4p
The circuit diagram and the simplified truth table of a multiplixer

4 to 1 are presented below.
Lets note:
Youtput
If {S0,S1}={0,0} and {X0,X1,X2,X3}={0,1,1,0}, then:
a.) Y=0
b.) Y=1
c.) 0/1 (unpredictable)
d.) according to the the previous state of the multiplexer
Correct answer a.)
5.
4p

52
Lets note:
Youtput
a.) Y=0
b.) Y=1
Correct answer b)
6.
4p

Lets note:
Youtput
a.) Y=0
b.) Y=1
Correct answer b)
7.
4p

53
Lets note:
Youtput
a.) Y=0
b.) Y=1
Correct answer a)
8.
4p
The circuit diagram and the simplified truth table of a

demultiplixer 1 to 4 are presented below.
If {S0, S1}={1, 1} and X=0 then

a.) {Y3, Y2, Y1, Y0}={1, 1, 1, 1}
b.) {Y3, Y2, Y1, Y0}={1, 1, 1, 0}
c.) {Y3, Y2, Y1, Y0}={0, 1, 1, 0}
d.) {Y3, Y2, Y1, Y0}={0, 1, 1, 1}
Correct answer d)
9.
4p

54
If {S0, S1}={1, 1} and X=0 then

a.) {Y3, Y2, Y1, Y0}={1, 1, 1, 1}
b.) {Y3, Y2, Y1, Y0}={1, 1, 1, 0}
c.) {Y3, Y2, Y1, Y0}={0, 1, 1, 0}
d.) {Y3, Y2, Y1, Y0}={0, 1, 1, 1}
Correct answer d)
10.
4p

If {S0, S1}={0, 0} and X=1 then

a.) {Y3, Y2, Y1, Y0}={1, 1, 1, 1}
b.) {Y3, Y2, Y1, Y0}={1, 1, 1, 0}
c.) {Y3, Y2, Y1, Y0}={0, 1, 1, 0}
d.) {Y3, Y2, Y1, Y0}={0, 1, 1, 1}
Correct answer a.)
11.
4p

If {S0, S1}={0, 0} and X=0 then

a.) {Y3, Y2, Y1, Y0}={1, 1, 1, 1}
b.) {Y3, Y2, Y1, Y0}={1, 1, 1, 0}
c.) {Y3, Y2, Y1, Y0}={0, 1, 1, 0}
d.) {Y3, Y2, Y1, Y0}={0, 1, 1, 1}
Correct answer b.)
12.
4p
The truth table of a binaryseven segments decoder and a display

cell are presented below.
55
X3
0
0
0
0
0
0
0
0
1
1
Inputs
X2 X 1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
X0
0
1
0
1
0
1
0
1
0
1
a
1
0
1
1
0
1
0
1
1
1
b
1
1
1
1
1
0
0
1
1
1
Outputs
c d e
1 1 1
1 0 0
0 1 1
1 1 0
1 0 0
1 1 0
1 1 1
1 0 0
1 1 1
1 0 0
f
1
0
0
0
1
1
1
0
1
1
g
0
0
1
1
1
1
1
0
1
1
If {X3, X2, X1, X0}={0, 0, 1, 1} then:

a.) {a, b, c, d, e, f, g}={1, 1, 1, 0, 0, 0, 1}
b.) {a, b, c, d, e, f, g}={1, 1, 0, 1, 0, 0, 1}
c.) {a, b, c, d, e, f, g}={1, 1, 1, 1, 0, 0, 1}
d.) {a, b, c, d, e, f, g}={1, 0, 1, 1, 0, 0, 1}
Correct answer c.)
13.
4p

cell are presented below.
X3
0
0
0
0
0
0
0
0
1
1
Inputs
X2 X 1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
X0
0
1
0
1
0
1
0
1
0
1
a
1
0
1
1
0
1
0
1
1
1
b
1
1
1
1
1
0
0
1
1
1
Outputs
c d e
1 1 1
1 0 0
0 1 1
1 1 0
1 0 0
1 1 0
1 1 1
1 0 0
1 1 1
1 0 0
f
1
0
0
0
1
1
1
0
1
1
g
0
0
1
1
1
1
1
0
1
1
If {X3, X2, X1, X0}={0, 1, 1, 0} then:

a.) {a, b, c, d, e, f, g}={1, 1, 1, 0, 0, 0, 1}
b.) {a, b, c, d, e, f, g}={1, 1, 0, 1, 0, 0, 1}
c.) {a, b, c, d, e, f, g}={1, 1, 1, 1, 0, 0, 1}
d.) {a, b, c, d, e, f, g}={1, 0, 1, 1, 1, 1, 1}
Correct answer d.)
14.
4p

cell are presented below:
56
X3
0
0
0
0
0
0
0
0
1
1
Inputs
X2 X 1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
X0
0
1
0
1
0
1
0
1
0
1
a
1
0
1
1
0
1
0
1
1
1
b
1
1
1
1
1
0
0
1
1
1
Outputs
c d e
1 1 1
1 0 0
0 1 1
1 1 0
1 0 0
1 1 0
1 1 1
1 0 0
1 1 1
1 0 0
f
1
0
0
0
1
1
1
0
1
1
g
0
0
1
1
1
1
1
0
1
1
If {X3, X2, X1, X0}={1, 0, 0, 1} then:

a.) {a, b, c, d, e, f, g}={1, 1, 1, 0, 0, 0, 1}
b.) {a, b, c, d, e, f, g}={0, 0, 1, 1, 1, 1, 1}
c.) {a, b, c, d, e, f, g}={1, 1, 1, 1, 0, 1, 1}
d.) {a, b, c, d, e, f, g}={1, 1, 1, 1, 1, 1, 1}
Correct answer c.)
18.
4p
The diagram circuit of a multiplexer-demultiplexer circuit is

presented below:
X0
X1
X2
X3
S0
S1
D0
2
3
D1
1A
1B
D2
1Y0
5
1Y1
6
1Y2
7
D3
~1G
A
1Y3
Y0
Y1
Y2
Y3
B
~G
S2
S3
Lets note:
X3, X2, X1, X0
input data;
S1 , S0
selection word for the multiplexer
S3 , S2
selection word for the demultiplexer
Y3, Y2, Y1, Y0
output data;
The circuit diagram and the truth table for the multiplexer are
In the same time the circuit diagram and the truth table for the
57
demultiplexer are:
If the selection word for the multiplexer is {S1, S0}={1,0} and the
selection word for the demultiplexer is {S3, S2}={0,1} then:
a.) Y0=X1
b.) Y1=X1
c.) Y2=X1
d.) Y3=X1
Correct answer c.)
19.
4p

presented below:
X0
X1
X2
X3
S0
S1
D0
2
3
D1
1A
1B
D2
1Y0
5
1Y1
6
1Y2
7
D3
~1G
A
1Y3
Y0
Y1
Y2
Y3
B
~G
S2
S3
Lets note:
X3, X2, X1, X0
input data;
S1 , S0
S3 , S2
Y3, Y2, Y1, Y0
output data;
demultiplexer are:
58
a.) Y0=X3
b.) Y1=X3
c.) Y2=X3
d.) Y3=X3
Correct answer a.)
20.
4p

presented below:
X0
X1
X2
X3
S0
S1
D0
2
3
D1
1A
1B
D2
1Y0
5
1Y1
6
1Y2
7
D3
~1G
A
1Y3
Y0
Y1
Y2
Y3
B
~G
S2
S3
Lets note:
X3, X2, X1, X0
input data;
S1 , S0
S3 , S2
Y3, Y2, Y1, Y0
output data;
demultiplexer are:
59
a.) Y0=X2
b.) Y1=X2
c.) Y2=X2
d.) Y3=X2
Correct answer b.)
20.
4p

presented below:
X0
X1
X2
X3
S0
S1
D0
2
3
D1
1A
1B
D2
1Y0
5
1Y1
6
1Y2
7
D3
~1G
A
1Y3
Y0
Y1
Y2
Y3
B
~G
S2
S3
Lets note:
X3, X2, X1, X0
input data;
S1 , S0
S3 , S2
Y3, Y2, Y1, Y0
output data;
demultiplexer are:
60
a.) Y0=X2
b.) Y1=X2
c.) Y2=X2
d.) Y3=X2
Correct answer d.)
61
62
Chapter 7
Memories
1.
1p
ROM Memories
a.)
are storage devices that can be written into once (as a general
rule) and the the information in ROMs is perserved after the
supply voltage is switched of
b.) are storage devices that can be written every time is needed and
the the information in ROMs is not perserved after the supply
voltage is switched of
c.) are storage devices that can be written into once (as a general
rule) and the the information in ROMs is not perserved after the
d.) are storage devices that can be written every time is needed and
all stored information is lost when the supply is switched of
Correct answer a.)
2.
1p
RAM Memories
a.)
are storage devices that can be written into once (as a general
rule) and the the information in ROMs is perserved after the
b.) are storage devices that can be written every time is needed and
the the information in ROMs is not perserved after the supply
voltage is switched of
c.) are storage devices that can be written into once (as a general
rule) and the the information in ROMs is not perserved after the
d.) are storage devices that can be written every time is needed and
all stored information is lost when the supply is switched of
Correct answer b.)
3.
1p
The symbol of a standard memory is presented below. The so

called Address Bus
63
a.)
set of data that transmit information needed to access a memory

location;
b.) set of data that is contained in a memory location;
c.) set of data which control the operation of the memory chip
d.) set of data that is contained in a memory location and set of data
which control the operation of the memory chip
Correct answer a.)
4.
1p

called Data Bus
a.)

location;
Correct answer b.)
5.
1p

called Control Bus
64
a.)

location;
Correct answer c.)
6.
3p
A memory that can be written - once - with a particular device is a:
a.) PROM type

b.) EPROM type
c.) EAROM type
d.) EEPROM type
Correct answer a.)
7.
3p
A memory that can be erased but the writing is performed using a s

particular device is a:
a.) PROM type
b.) EPROM type
c.) EAROM type
d.) EEPROM type
Correct answer b.)
8
3p
A memory whose contents can be changed only one bit is a:
a.) PROM type

b.) EPROM type
c.) EAROM type
d.) EEPROM type
Correct answer c.)
9
A memory that can be erased (not just one bit but whole sections or
65
3p
fully) or rewritten without requiring their removal from the

computer's memory is:
a.) PROM type
b.) EPROM type
c.) EAROM type
d.) EEPROM type
Correct answer d.)
66
67

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Chapter 1

Analog to Digital Conversion

The process of converting the analog signal into a digital signal

The figure below shows:

a.) block diagram of an analog filter

From a formal standpoint, the A-D conversion involves only:

Sampling an analog signal means means:

that the sample selection is based on the average value of the

Figure 1.1 shows a digital anolog converter. Digital word D0 - D7

a.) input signal

Correct answer a.)

Assume the digital word 10010011. The Most Significant Bit

d.) All bits with value "0"

Assume the digital word 10010011. The Least Significant Bit

d.) All bits with value "0"

Binary number N=1010

Correct answer b.)

Binary number N=0110

Binary number N=1010 B has the following hexadecimal

Binary number N=0010 B has the following hexadecimal

Binary number N=1110 B has the following hexadecimal

Binary number N=0110 B has the following hexadecimal

Hexadecimal number N=A87C H may be encoded, using as

Hexadecimal number N=C001 H may be encoded, using as

Figure 2.1 shows the block diagram of a combinational logic

The set X = {X1, X 2 , KX n } is:

Figure 2.1 shows the block diagram of a combinational logic

The set Y = {Y1 , Y2 , K Ym } is:

Figure 2.1 shows the block diagram of a combinational logic

Figure 2.1 shows the block diagram of a combinational logic

The symbol of an AND logic gate, ANSI standard is:

The symbol of a NAND logic gate, ANSI standard is:

The symbol of an OR logic gate, ANSI standard is:

The symbol of a NOR logic gate, ANSI standard is:

The symbol of an AND logic gate, DIN standard is:

The symbol of a NAND logic gate, DIN standard is:

Correct answer c.)

The symbol of an OR logic gate, DIN standard is:

The symbol of a NOR logic gate, DIN standard is:

The symbol of a NOT logic gate, DIN standard is:

The symbol of a NAND logic gate, ANSI standard is:

The figure shows the symbol of a logic gate, type:

a.) AND standard ANSI;

The figure shows the symbol of a logic gate, type:

a.) AND standard ANSI;

The figure shows the symbol of a logic gate, type:

a.) AND standard ANSI;

The figure shows the symbol of a logic gate, type:

a.) AND standard ANSI;

The figure shows the symbol of a logic gate, type:

a.) OR standard ANSI;

The figure shows the symbol of a logic gate, type:

a.) OR standard ANSI;

The figure shows the symbol of a logic gate, type:

a.) OR standard ANSI;

The figure shows the symbol of a logic gate, type:

a.) OR standard ANSI;

The figure shows the symbol of a logic gate, type:

a.) OR standard ANSI;

The figure shows the symbol of a logic gate, type:

a.) OR standard ANSI;

The logic function implemented by an AND gate is: