BCD TO 7 SEGMENTS DECODER

Lara Manuel, Aguilar Armin, Chan Ricardo,

Ros Aaron, Prado Ivn.
UNIVERSIDAD AUTNOMA DE YUCATN
Mrida, Yucatn

Line 1 (of Affiliation): dept. name of organization

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Authors Name/s per 2nd Affiliation (Author)

Abstract Logic gates are physical devices that implement a
Boolean function, and are the base of modern digital electronics
design. In this work we shall explore the basic logical functions such
as AND, OR , NOT, NAND, NOR, XOR and XNOR by simulating
them in a software (ISE Design Suite) and implementing said
functions in a Field Programmable Gate Array (FPGA), which in
this case is a Basys 2 FPGA.

I.

INTRODUCTION

II.

SIMULATION

In this experiment two simulations were realized, the first was

a simulation of the two DeMorgan theorems and is observed in
Fig.2. The second simulation covered the NAND and NOR
equivalent circuits, and is observed in Fig.3.
The experiment was modeled by changing the value of the two
inputs at different time intervals and finally, leaving both inputs
as a logic 1.

To fully understand digital electronics, one must first

understand what logic gates are and how they operate. As
mentioned before, a logic gate is a physical device that
implements a Boolean function as defined by [1], which means it
performs a logical operation (E.g. AND, OR) on one or more
logical inputs producing a single logical output. Generally, logic
gates are implemented using diodes and transistors which act as
electronic switches. In Fig.1 we can observe the basic logic gates
used in digital electronics.
Fig.2. Simulation of the theorem 1 and theorem
2 of DeMorgan in ISE Design Suite.
From Fig.2 we can observe an equivalence between the
NAND logic gate and the OR logic gate (with negated
complements), likewise there is a similar relation between the
NOR logic gate and the AND logic gate (with negated
complements). Thus, we can prove the DeMorgan theorem
correct.

Fig.1. Basic logic gates in digital electronics, each with its

respective symbol, Boolean expression and truth table.

Fig.3. Simulation of the NAND and NOR

equivalent circuits o f the basic logic gates in
ISE Design Suite.

In Fig. 3 we may observe 2 inputs and 14 outputs (2 for each

logic gate), where each pair of outputs represents a basic logic
gate, represented with NAND or NOR logic gates.
It can be clearly observed from fig.3 that all signals from each
pair are identical; therefore we can ascertain that it is possible to
represent each logic gate with a NAND or NOR equivalent
function, as the De Morgan theorem states.
III.

IMPLEMENTED DESIGN

In this section are included the most relevant observations

experimented throughout the implementation of this practice. Is
necessary built a truth table of the structure 4 bits, it declare the
common anode as our reference getting 7 outputs (view in the
table 1), each one represent a segment on display. In the case of
the common anode it must receive 0 logical for turn on the
LEDs on display.
D
0
0
0
0
0
0
0
0
1
1

C
0
0
0
0
1
1
1
1
0
0

B
0
0
1
1
0
0
1
1
0
0

A
0
1
0
1
0
1
0
1
0
1

A
0
1
0
0
1
0
0
0
0
0

B
0
0
0
0
0
1
1
0
0
0

C
0
0
1
0
0
0
0
0
0
0

D
0
1
0
0
1
0
0
1
0
0

E
0
1
0
1
1
1
0
1
0
1

F
0
1
1
1
0
0
0
1
0
0

G
1
1
0
0
0
0
0
1
0
0

Table 1. Truth table 4 bits, 7 segments.

In the table 1, it defines D, C, B and B inputs, and A, B, C, D, E,

F and G are outputs, with this logical values it create a Karnaugh
maps for each output segment using maxterms due the use of
common anode. It use only the first 10 bits and the rest it filled
with X that means the value Doesnt matter due the number
9 its the maximum of terms in the decimal system. This could
change, all depends on the numeric system wanted.
IV.

IMPLEMENTED MODULE

The architecture on the Module VHDL of Project Navigator by

ISE Adept contain four standard logic inputs and one standard
logic vector for the output of size 7.
A, B, C, D: IN STD_LOGIC;
LEDS: OUT STD_LOGIC_VECTOR (6 DOWN TO 0);
For optimize it used the instance method, creating a VHDL
module for each segment, united by one VHDL main module.

V.

IMPLEMENTATION CONSTRAINTS FILE

Is used for allocating the FPGA pin depending of the FPGA

characteristics like the family, device and package with de
variable input/output created in the VHDL module, the syntax is
described in form 2,
NET VARIABLE_NAME LOC= FPGA_PIN; (2)
For the architecture of design, it defines 4 inputs D, C, B, A
linked with 4 switch allocated in the FPGA, also 7 outputs linked
with each segment on display of seven segment, allocated in
FPGA with the target to demonstrate the simplification of
Karnaugh maps and the truth table showed.
VI.

LOADING THE PROGRAM

Once with the design implementation and the constraints file

created, in Xilinx option, it use the synthesizer, after implement
design and finally generate a programming file BIT. Thus, with
the FPGA connected to computer and with the software Diligent
Adept is loaded the bit file before created.
VII.

RESULTS

It has been gotten as a result a Binary-Coder Decimal decoder

implemented on a seven segments display, encountered on the
FPGA board. The functionality of the decoder design consist of
managing the input variables through the switches* to generate a
decimal number represented on the display for each combination
of these switches states (0s if they are off and 1s if are on). As an
example, if the combination on the input is 0110 (LSB on the
right), the value on the displayed output would be the decimal
number 6. This implemented process could be achieve with the
use of combinational logic, as it could be observed in the table 2,
placed below, the behavior or response for each output (segments
in the display) was determined by the functions described on the
right. To turn on the segments it is necessary to send a 0 logic
since the displays are conform in an anode common
configuration. In the same way, to turn on the displays is required
to send a 0 logic because of the already mentioned fact.
*in this case were used four since to represent decimal numbers
up to 9 it is necessary the use of four-bits numbers in binary base.
Segment Output
A
B
C

Function
D + AC+ B + AC
D + C + AB + A B
D+ C+ AD + BD

D
E
F
G

D+ CAB+AC+BC+BA
AC+ BD+ DC+AB
D+ AB+ CB+AC
D+ BC+CB+BA

that a decoder turns a binary number into a specific output, which

represent a digit or a particular character.

Table 2. Functions Output

There are 960 available slices in the architecture of the FPGA

Basys 2; these slices could also be seen as the basic building
block components in the FPGA, which contains a number of LUT
s, flip-flops and carry-logic elements. In the design
implementation only 1% of the occupied slices were used, zero
flips-flops, 17 bonded inputs outputs buses (IOBS) of 83
available, which represents a 20 percent and seven four- input
LUTs were used of 1920 available. This information shows the
amazing power and advantage of the FPGA, because it could be
implemented at a high level, getting efficiency and control design,
also the software give the statistics of the sources, translation
report, map report, synthesis report and control design, also the
statistics of the sources used in the module VHDL.
It was possible to visualize just one display on because is
needed to enable the other displays by sending a digital 0 logic.
It could also be implemented the behavior of the displays in
function of input variables (combinational logic) by using
switches, of which their states determine what display should be
on. Furthermore, it could be possible to modify the generated
truth table with the purpose of showing other characters like
hexadecimal digits, to achieve this it is required to use the six
combinations omitted and determinate which segments should
turn on for each digits array. It is implicit that is necessary to
modify the corresponding function to generate the response
expected on each output (segment). Finally, it could be asserted

VIII.

CONCLUTION

This practice show us how a complex Boolean function could be

reduced to terms more simple, using the axioms and theorems
algebra Boole and the implementations of the Karnaugh maps
however is necessary to emphasize that there are many
possibilities to construct one function or an specific output, but if
the simplification process is successful doesnt matter because
we could express the same output with less terms and logical
operators all depend of the arrangement used and the application
of the DeMorgan theorems. This bring us several advantage in
the time of synthetize, implementation, design, and the sources
used in the FPGA let us be more efficient and create functions
more complex with the necessary sources design. The process of
simplification not always ensure the reduction of the terms and
sources, in special cases could be a function more complex
compare to the original based in the number of logic gates, Flip
flops, IOBs used etc.
REFERENCESE
[1]
[2]

R.Jaeger,T. Blalock. (2011). Microelectric Circuit Desgn, 4 th Edition. New

York, U.S.A: McGraw Hill.
D. Money, Digital Design and Computer Architecture 2 nd edition, chapter
1, pp. 2530, July 2012.

[3]