Phase Locked Loop in ARM7

There are two PLL modules in the LPC2141/2/4/6/8 microcontroller.

o The PLL0 is used to generate the CCLK clock (system clock).
o PLL1 has to supply the clock for the USB at the fixed rate of 48
MHz
Structurally these two PLLs are identical with exception of the PLL
interrupt capabilities reserved only for the PLL0.
The PLL0 and PLL1 accept an input clock frequency in the range of 10
MHz to 25 MHz only. The input frequency is multiplied up the range of
10 MHz to 60 MHz for the CCLK and 48 MHz for the USB clock using a
Current Controlled Oscillators (CCO). The multiplier can be an integer
value from 1 to 32 (in practice, the multiplier value cannot be higher than
6 on the LPC2141/2/4/6/8 due to the upper frequency limit of the CPU).
The CCO operates in the range of 156 MHz to 320 MHz, so there is an
additional divider in the loop to keep the CCO within its frequency range
while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock.
Since the minimum output divider value is 2, it is insured that the PLL
output has a 50% duty cycle.
PLL Registers:
PLL activation is controlled via the PLLCON register
The PLL multiplier and divider values are controlled by t he PLLCFG
register.
These two registers are protected in order to prevent accidental alteration
of PLL parameters or deactivation of the PLL.
The protection is accomplished by a feed sequence similar to that of the
Watchdog Timer. Details are provided in the description of the PLLFEED
register.

The PLL is enabled by software only. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a
clock source
PLL Registers Description:
PLLCON (PLL Control Register):
PLL Control Register Holding registers for updating PLL control bits.
Values written to this register do not take effect until a valid PLLFEED
sequence has taken place.
Bit Symbol
0

PLLE

PLLC

7:2

Description
PLL Enable. When one, and after a valid PLL feed, this bit will activate
the PLL and allow it to lock to the requested frequency.
PLL Connect. When PLLC and PLLE are both set to one, and after a
valid PLL feed, connects the PLL as the clock source for the
Micro controller. Otherwise, the oscillator clock is used directly by the
microcontroller. See PLLSTAT register
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

Reset
value
0
0

PLL Control bit combinations:

PLLC PLLE
PLL Function
0
0
PLL is turned off and disconnected. The CCLK equals the unmodified clock
input. This combination cannot be used in case of the PLL1 since there will be no
48 MHz clock and the USB cannot operate.
0
1
The PLL is active, but not yet connected. The PLL can be connected after
PLOCK is asserted.
1
0
Same as 00 combinations. This prevents the possibility of the PLL being
connected without also being enabled.
1
1
The PLL is active and has been connected. CCLK/system clock is sourced
from the PLL0 and the USB clock is sourced from the PLL1.

PLL Configuration Register :

The PLLCFG register contains the PLL multiplier and divider values.
Changes to the PLLCFG register do not take effect until a correct PLL
feed sequence has been given(PLL Feed register (PLL0FEED - 0xE01F
C08C, PLL1FEED - 0xE01F C0AC)). Calculations for the PLL

frequency, and multiplier and divider values are found in the PLL
Frequency Calculation.
PLLCON Register:
Bit Symbol Description
4:0

MSEL

6:5

PSEL

PLL Multiplier value. Supplies the value "M" in the PLL frequency 0
calculations.
PLL Divider value. Supplies the value "P" in the PLL frequency 0
calculations.
Reserved, user software should not write ones to reserved bits. The NA
value read from a reserved bit is not defined.

Reset
Value
0
0

PLL Divider values:

PSEL Bits (PLLCFG bits [6:5])
00
01
10
11

Value of P
1
2
4
8

PLL Multiplier values:

MSEL Bits (PLLCFG bits [4:0]) Value of M
00000
1
00001
2
00010
3
00011
4

11110
31
11111
32

PLL Status Register:

The read-only PLLSTAT register provides the actual PLL parameters that
are in effect at the time it is read, as well as the PLL status. PLLSTAT
may disagree with values found in PLLCON and PLLCFG because
changes to those registers do not take effect until a proper PLL feed has
occurred.
Bit

Symbol

Description

4:0

MSEL

6:5

PSEL

Read-back for the PLL Multiplier value. This is the value currently
used by the PLL.
Read-back for the PLL Divider value. This is the value currently

Reset
Value
0
0

used by the PLL.

7
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
8
PLLE Read-back for the PLL Enable bit. When one, the PLL is currently
activated. When zero, the PLL is turned off. This bit is
automatically cleared when Power-down mode is activated.
9
PLLC Read-back for the PLL Connect bit. When PLLC and PLLE are
both one, the PLL is connected asthe clock source for the
microcontroller. When either PLLC or PLLE is zero, the PLL is
bypassed and the oscillator clock is used directly by the
microcontroller. This bit is automatically cleared when Power-down
mode is activated.
10
PLOCK Reflects the PLL Lock status. When zero, the PLL is not locked.
When one, the PLL is locked onto the requested frequency.
15:11
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.

N/A
0

0
N/A

PLL Feed Register:

A correct feed sequence must be written to the PLLFEED register in order
for changes to the PLLCON and PLLCFG registers to take effect. The
feed sequence is:
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
The two writes must be in the correct sequence, and must be consecutive
APB bus cycles. The latter requirement implies that interrupts must be
disabled for the duration of the PLL feed operation. If either of the feed
values is incorrect, or one of the previously mentioned conditions is not
met, any changes to the PLLCON or PLLCFG register will not become
effective.
Bit

Symbol

Description

7:0 PLLFEED The PLL feed sequence must be written to this register in order for
PLL configuration and control register changes to take effect.

PLL frequency calculation:

Elements determining PLLs frequency:
Ele ment

Description

Reset
Value
0X00

FOSC
FCCO
CCLK
M
P

the frequency from the crystal oscillator/external oscillator.

The frequency of the PLL current controlled oscillator.
the PLL output frequency (also the processor clock frequency)
PLL Multiplier value from the MSEL bits in the PLLCFG register.
PLL Divider value from the PSEL bits in the PLLCFG register.

The PLL output frequency (when the PLL is both active and connected) is
given by:
CCLK = M X FOSC (or) CCLK = FCCO/ (2 X P)
The CCO frequency can be computed as:
FCCO= CCLK X 2 X P or FCCO= FOSC X M X 2 X P
The PLL inputs and settings must meet the following:
FOSC is in the range of 10 MHz to 25 MHz.
CCLK is in the range of 10 MHz to Fmax(the maximum allowed
frequency for the
Micro controller - determined by the system microcontroller is embedded
in).
FCCO is in the range of 156 MHz to 320 MHz.
Procedure for Enabling PLL In ARM 7:
1. Select the Multiplier and divider values to the required frequency
and load those values into PLLCFG Register.
2. Enable the PLL Using PLLCON Register.
3. To update values into PLLCFG Register and PLLCON Send a feed
sequence 0XAA followed by 0X55 into PLLFEED Register.
4. Wait for the PLOCK bit in PLLSTAT Register.
5. Enable and Connect the PLL Using PLLCON Register.
6. To update values into PLLCON Send a feed sequence 0XAA
followed by 0X55 into PLLFEED Register.
7. to Divide the processor Clock to the Required frequency use
VPBDIV Register.
VPBDIV Register(VPBDIV - 0xE01F C100)

Code:
#include <lpc213x.h>
void PLLConfig()
{
PLLCFG=0X00000024;
PLLCON=0X00000001;
PLLFEED=0X000000AA;
PLLFEED=0X00000055;
while(!(PLLSTAT&0X00000400));
PLLCON=0X00000003;
PLLFEED=0X000000AA;
PLLFEED=0X00000055;
}
main()
{
PLLConfig();
while(1);

}Check the Output in NEXT Page: