Chapter 5

Digital Design and Computer Architecture, 2nd Edition

David Money Harris and Sarah L. Harris

Chapter 5 <1>

Chapter 5 :: Topics

Introduction
Arithmetic Circuits
Number Systems
Sequential Building Blocks
Memory Arrays
Logic Arrays

Chapter 5 <2>

Multipliers
Partial products formed by multiplying a single
digit of the multiplier with multiplicand
Shifted partial products summed to form result
Decimal
230
x 42
460
+ 920
9660

Binary
multiplicand
multiplier
partial
products
result

230 x 42 = 9660

0101
x 0111
0101
0101
0101
+ 0000
0100011
5 x 7 = 35
Chapter 5 <3>

4 x 4 Multiplier
A B
4

x
8

P
A3

A2

B0
B1
A3
B3

A2
B2

A1
B1

A0
B0

A1

A0

0
0

B2

A3B0 A2B0 A1B0 A0B0

0

A3B1 A2B1 A1B1 A0B1

A3B2 A2B2 A1B2 A0B2

B3

A3B3 A2B3 A1B3 A0B3

+
P7

P6

P5

P4

P3

P2

P1

P0
P7

P6

P5

P4

P3

Chapter 5 <4>

P2

P1

P0

Counters
Increments on each clock edge
Used to cycle through numbers. For example,
000, 001, 010, 011, 100, 101, 110, 111, 000, 001

Example uses:
Digital clock displays
Program counter: keeps track of current instruction executing

Symbol

Implementation

CLK

CLK

Q
Reset

Reset
Chapter 5 <5>

Counters
Counters are very often need inside the
system, for instance to measure time.

+4

PC
Clk

Process(clk)
Begin
if rising_edge(clk) then
PC <= PC + to_unsigned(4,32);
End if;
End process;

12

16

20

Shift Registers
Shift a new bit in on each clock edge
Shift a bit out on each clock edge
Serial-to-parallel converter: converts serial input (Sin) to
parallel output (Q0:N-1)

Symbol:

Implementation:
CLK

Q
S in S out

S in

S out
Q0

Q1

Q2

Chapter 5 <8>

Q N-1

Shift Register with Parallel Load

When Load = 1, acts as a normal N-bit register
When Load = 0, acts as a shift register
Now can act as a serial-to-parallel converter (Sin to Q0:N-1) or
a parallel-to-serial converter (D0:N-1 to Sout)
D0
Load
Clk
S in

D1

D2

DN-1

Q0

Q1

Q2

Chapter 5 <9>

S out
Q N-1

Memory Arrays
Efficiently store large amounts of data
3 common types:
Dynamic random access memory (DRAM)
Static random access memory (SRAM)
Read only memory (ROM)

M-bit data value read/ written at each unique N-bit address

Address

Array

Data
Chapter 5 <10>

Memory Arrays
2-dimensional array of bit cells
Each bit cell stores one bit
N address bits and M data bits:

Address

2N rows and M columns

Depth: number of rows (number of words)
Width: number of columns (size of word)
Array size: depth width = 2N M

Address

Array

Data

11

0 1 0

10

1 0 0

01

1 1 0

00

0 1 1

Array

Data

Address Data
2

depth

width
Chapter 5 <11>

Memory Array Example

22 3-bit array
Number of words: 4
Word size: 3-bits
For example, the 3-bit word stored at address 10 is 100
Address Data
Address

Array

Data

11

0 1 0

10

1 0 0

01

1 1 0

00

0 1 1

depth

width

Chapter 5 <12>

Memory Arrays
Address

10

1024-word x
32-bit
Array
32

Data

Chapter 5 <13>

Memory Array Bit Cells

Chapter 5 <14>

Memory Array
Wordline:
like an enable
single row in memory array read/written
corresponds to unique address
only one wordline HIGH at once
2:4
Decoder
11
Address

10

01

00

bitline2

wordline3

wordline2

wordline1

wordline0

bitline1

stored
bit = 0

stored
bit = 1

stored
bit = 0

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 1

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 1

stored
bit = 1

Data2

Data1

Chapter 5 <15>

bitline0

Data 0

Types of Memory
Random access memory (RAM): volatile
Read only memory (ROM): nonvolatile

Chapter 5 <16>

RAM: Random Access Memory

Volatile: loses its data when power off
Read and written quickly
Main memory in your computer is RAM
(DRAM)
Historically called random access memory because any data
word accessed as easily as any other (in contrast to sequential
access memories such as a tape recorder)

Chapter 5 <17>

ROM: Read Only Memory

Nonvolatile: retains data when power off
Read quickly, but writing is impossible or
slow
Flash memory in cameras, thumb drives, and
digital cameras are all ROMs
Historically called read only memory because ROMs
were written at manufacturing time or by burning fuses.
Once ROM was configured, it could not be written again.
This is no longer the case for Flash memory and other
types of ROMs.
Chapter 5 <18>

Types of RAM
DRAM (Dynamic random access memory)
SRAM (Static random access memory)
Differ in how they store data:
DRAM uses a capacitor
SRAM uses cross-coupled inverters

Chapter 5 <19>

Robert Dennard, 1932 Invented DRAM in

1966 at IBM
Others were skeptical
that the idea would
work
By the mid-1970s
DRAM in virtually all
computers

Chapter 5 <20>

DRAM
Data bits stored on capacitor
Dynamic because the value needs to be refreshed
(rewritten) periodically and after read:
Charge leakage from the capacitor degrades the value
Reading destroys the stored value
bitline
wordline
stored
bit

Chapter 5 <21>

DRAM
bitline
wordline
stored + +
bit = 1

bitline
wordline
stored
bit = 0

Chapter 5 <22>

SRAM

bitline

bitline

wordline

Chapter 5 <23>

Memory Arrays Review

2:4
Decoder
11
Address

wordline3

10

01

00

bitline2

wordline2

wordline1

wordline0

stored
bit = 0

stored
bit = 1

stored
bit = 0

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 1

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 1

stored
bit = 1

Data2

DRAM bit cell:

bitline
wordline

bitline1

bitline0

Data1

Data0

SRAM bit cell:

bitline

bitline

wordline

Chapter 5 <24>

ROM: Dot Notation

bitline
wordline
bit cell
containing 0
bitline
wordline
bit cell
containing 1

Chapter 5 <25>

Fujio Masuoka, 1944 Developed memories and high

speed circuits at Toshiba, 1971-1994
Invented Flash memory as an
unauthorized project pursued during
nights and weekends in the late
1970s
The process of erasing the memory
reminded him of the flash of a
camera
Toshiba slow to commercialize the
idea; Intel was first to market in
1988
Flash has grown into a $25 billion
per year market

Chapter 5 <26>

ROM Storage
Address Data
11

0 1 0

10

1 0 0

01

1 1 0

00

0 1 1
width

Chapter 5 <27>

depth

ROM Logic

Data2 = A1 A0
Data1 = A1 + A0
Data0 = A1A0

Chapter 5 <28>

Example: Logic with ROMs

Implement the following logic functions using a 22 3-bit
ROM:
X = AB
Y=A+B
Z=AB

2:4
Decoder
11
A, B

10
01
00
X

Chapter 5 <29>

Example: Logic with ROMs

Implement the following logic functions using a 22 3-bit
ROM:
X = AB
Y=A+B
Z=AB

2:4
Decoder
11
A, B

10
01
00
X

Chapter 5 <30>

Logic with Any Memory Array

2:4
Decoder
11
Address

10

01

00

bitline2

wordline3

wordline2

wordline1

wordline0

bitline1

stored
bit = 0

stored
bit = 1

stored
bit = 0

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 1

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 1

stored
bit = 1

Data2

Data1

Data2 = A1 A0
Data1 = A1 + A0
Data0 = A1A0
Chapter 5 <31>

bitline0

Data0

Logic with Memory Arrays

Implement the following logic functions using a 22 3-bit
memory array:
X = AB
Y=A+B
Z=AB

Chapter 5 <32>

Logic with Memory Arrays

Implement the following logic functions using a 22 3-bit
memory array:
X = AB
Y=A+B
Z=AB
A, B

2:4
Decoder
11

wordline3

10

01

00

bitline2

wordline2

wordline1

wordline0

bitline1

stored
bit = 1

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 1

stored
bit = 1

stored
bit = 0

stored
bit = 1

stored
bit = 0

stored
bit = 0

stored
bit = 0

stored
bit = 0

Chapter 5 <33>

bitline0

Logic with Memory Arrays

Called lookup tables (LUTs): look up output at each input
combination (address)
4-word x 1-bit Array
2:4
Decoder
00

Truth
Table
A
0
0
1
1

B
0
1
0
1

Y
0
0
0
1

A1

A0

bitline

01

stored
bit = 0
stored
bit = 0

10
stored
bit = 0
11
stored
bit = 1

Y
Chapter 5 <34>