Applying a Layered Testbench and

Packet Based Verification Approach

AXI4 interconnects
Increasing use of universal verification methodology
Verification engineers are increasingly adopting universal verification
methodology (UVM) to solve a wide range of design verification issues.
However, inappropriate application of UVM can lead to various problems
at a later stage as the complex random scenarios generated by the
methodology can mask otherwise simple functional bugs. While UVM
is a very powerful verification methodology, testbench architecture
and a proper approach to design verification are critical for successful
outcomes.

Realizing the potential of UVM

UVM can serve as an exceptionally valuable tool in creating scalable and
reusable environments necessary to verify the design intent. Realizing
the true value of UVM depends solely on how skillfully it is used. When
applied using multi-layered approach, UVM can empower designers
to build and verify extremely complex systems with a high degree of
reliability. Use of a top-down testbench architecture that is divided into
different layers based on functionality enables user to create and verify
complex scenarios at unit level with a high degree of reliability.

Leveraging AXI4 test bench architecture

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UVM inherently supports a layered structure and all AXI4 environment

components can be mapped to their standard UVM counterparts. Layers
can be replaced with different protocols, allowing the environment to be
further extended thus offering scalability. Moreover, since components
are independent of each other, they can be easily reused at different
levels. The advantages of a layered architecture approach makes it the
best fit option for a complex testbench that is designed for AXI cachecoherent interconnects. This approach provides greater controllability
and predictability without losing the UVM benefits of scenario
randomization.

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Bringing you the advantage of multi-layered approach

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We recommend a structured approach combined with a sophisticated

coverage model that can help uncover bugs at the early stages of the
design verification. A layered architecture approach offers advantages
such as scalability to address future enhancements of the testbench.
It results in business advantages such as greater control on quality
and flexibility in design and implementation, innovative technologies,
reduced development costs and faster time-to-market.

To learn more about how our unique approach can help optimize UVM,
download the whitepaper Applying a Layered Testbench and Packet
Based Verification Approach AXI4 interconnects

2014 Cyient, Hyderabad, India. Cyient believes the information in this publication is accurate as of its publication date; such
information is subject to change without notice. Cyient acknowledges the proprietary rights of the trademarks and product names of
other companies mentioned in this document.