P R

CT
ODU CEMEN 7
T CA3450
E T E L A 7 74
OL REP 00-442-
OBS ENDED 1 - 8 m
MM ions s.co
O R ECO pplicat p@harri January 1999 File Number 1732.5
N ral A centap
Cent :
Call or email

220MHz, Video Line Driver, High Speed Features

Operational Amplifier • High Open Loop Gain at Video Frequencies
The CA3450 is a large signal video line driver and high - AOL . . . . . . . . . . . . . . . . . . . . . . . . . . >40dB at f = 5MHz
speed operational amplifier capable of driving 50Ω
• Power Bandwidth of 10MHz . . . . . . . ACL = 5; VO = ±3.5V
transmission lines and flash A/Ds. The uncompensated unity
gain crossing occurs at 230MHz without load. It can operate • Slew Rate at Full Load . . . . . . . . . . . . . 330V/µs (AV ≥ 10)
at dual or single supplies of ±7.25V or 14.5V, respectively. • fT = 220MHz; CC = 0pF With a Load of 50Ω ||20pF|| 1MΩ
The CA3450 can be compensated with a single capacitor (Scope Input)
network. It has output drive capability of 75mA SINK or
SOURCE. The CA3450 is capable of driving Flash A/Ds in • VOUT = ±4.1V Into 75Ω
video or high speed instrumentation (accurate) applications • Offset Null Terminals
with bandwidth up to 10MHz. Offset voltage nulling terminals
are also available. Applications
Pinout • Video Line Driver
CA3450 • High Frequency Unity Gain Buffer
(PDIP)
TOP VIEW • Pulse Amplifier
• High Speed Comparator

OFFSET NULL 1 16 OFFSET NULL • High Frequency Oscillator and Video Amplifiers
NC 2 15 NC • Driver for A/Ds in Video Applications . . . . . . . .10MHz BW
- INPUT 3 14 + INPUT

V- 4 13 V-
Part Number Information
V- 5 12 V- TEMP. PKG.
PART NUMBER RANGE (oC) PACKAGE NO.
VO 6 11 COMP

V+ 7 10 NC CA3450E -40 to 85 16 Ld PDIP E16.3

V+ 8 9 COMP

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
 CA3450

Block Diagram
7 V+ 8 V+

BIAS CIRCUIT

+IN
14 +
X180 X0.50 X18 6
3 - OUTPUT
-IN
INPUT CURRENT DC LEVEL OUTPUT POWER
COMPENSATED SHIFT DRIVER AND
DIFFERENTIAL STAGE OUTPUT POWER
AMPLIFIER STAGE

1 16 9 11 4 5 12 13

OFFSET PHASE V-
NULL COMP

Schematic Diagram
FREQUENCY
COMPENSATION V+ V+
11 8 7

D1 D2
C1 Q8 Q9
Q14
Q5 C2
Q15
Q10 C3
Q2
Q16
Q12
Q4 Q6 Q7 Q11
Q1 Q3
Q17
Q18
V- D3
V- Q19

D4
R7
R5 D5 C6 6
C4
2K
D6
R8 6
R4
30 OUTPUT
8.5K R6
V+ 3 Q20 Q23 14 C5
INVERTING NON- 2K D10
Q21 Q22 9
INPUT INVERTING
INPUT FREQUENCY
Q35 COMPEN-
Q26 R2 R3
140 SATION
R1
100K Q27 Q38
R11
Q24 3k D9

R9
Q25 D7 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q36 Q37
780

C7
R10 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22
3.2K 250 860 860 130 860 500 200 100 170 270 250

1 16 4, 5, 12, 13
V-

2
 CA3450

Absolute Maximum Ratings Thermal Information

Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . 14.5V Thermal Resistance (Typical, Note 1) θJA (oC/W)
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Operating Conditions Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications CC = 5pF, VSUPPLY = ±6V, Unless Otherwise Specified

TEMP.
PARAMETER SYMBOL TEST CONDITIONS (oC) MIN TYP MAX UNITS
DC
Input Offset Voltage |VIO| 25 - 8 20 mV
Full - 10 35 mV
Input Bias current |IIB| 25 - 100 400 nA
Input Offset Current |IIO| 25 - 50 200 nA
Open Loop DC Gain AOL VOUT = ±2.5V, RL = 50Ω 25 60 70 - dB
Full 55 - - dB
Power Supply Rejection Ratio PSRR ∆V = ±1V 25 55 65 - dB
Common Mode Rejection Ratio CMRR VICR = ±3.5V 25 50 60 - dB
Common Mode Input Range VICR 25 ±3.5 ±3.7 - V
Full ±3.0 - - V
Supply Current I+ 25 - 30 40 mA
Full - - 50 mA
DYNAMIC
-3dB Bandwidth No Load 25 - 200 - MHz
AV = 1 (See Figure 2)
RL = 1MΩ||20pF 25 - 190 - MHz
CC = 5pF
RL = 50Ω||20pF 25 - 185 - MHz
Bandwidth (Unity Gain Crossing) No Load 25 210 230 - MHz
AV = Open Loop
RL = 20pF||1MΩ 25 180 200 - MHz
CC = 0 (See Figure 1)
RL = 50Ω||20pF 25 180 220 - MHz
Bandwidth (Unity Gain Crossing) No Load 25 200 210 - MHz
AV = 10, CC = 0pF
50Ω 25 175 190 - MHz
RFEEDBACK = 450Ω
RPIN 3 - G = 50Ω (See Figure 2) 1M||20pF 25 180 195 - MHz
50Ω||1M||20pF 25 170 188 - MHz
Transient Response, Overshoot OS AV = 1, CC = 5pF RL = 50Ω||20pF 25 - 30 - %
(See Figure 3)
No Load 25 - 20 - %
AV ≥10, CC = 0pF, RL = 50Ω||20pF 25 - 10 - %
Settling Time (See Figure 5) tS AV = -1, CC = 5pF, 0.1%, 10 Bits 25 - 35 - ns
(2V Step, RL = 50Ω||20pF)
AV = 1, CC = 5pF, 0.1%, 10 Bits 25 - 50 - ns
AV = 10, CC = 0pF, 0.1%, 10 Bits 25 - 35 - ns
AV = 10, CC = 0pF, 1.0%, 7 Bits 25 - 25 - ns

3
 CA3450

Electrical Specifications CC = 5pF, VSUPPLY = ±6V, Unless Otherwise Specified (Continued)

TEMP.
PARAMETER SYMBOL TEST CONDITIONS (oC) MIN TYP MAX UNITS
Slew Rate (See Figures 2, 4) SR AV = 1, CC = 5pF No Load 25 - 220 - V/µs
RL = 50Ω||20pF 25 - 160 - V/µs
AV ≥10, CC = 0pF No Load 25 370 440 - V/µs
RL = 50Ω||20pF 25 300 330 - V/µs
Full Power Bandwidth FPBW AV = 5, CC = 5pF No Load 25 - 10 - MHz
(FPBW = SR/π VP-P) VOUT = ±3.5V
RL = 50Ω||20pF 25 - 7.2 - MHz
AV ≥10, CC = 0pF No Load 25 29 35 - MHz
VOUT = ±2.0V
RL = 50Ω||20pF 25 24 26 - MHz
Input Noise Voltage eN f = 1kHz 25 - 12 - nV/√Hz
Differential Gain DG See Figure 8 25 - 0.2 - %
Differential Phase DP See Figure 8 25 - 0.2 - Degrees
Output Current IOUT Into +4V or -4V 25 60 75 - mA
Output Voltage Swing VOM+ RL = 75Ω 25 3.9 4.1 - V
VOM - 25 -3.9 -4.1 - V
Input Capacitance CI f = 1MHz 25 - 2.2 - pF
Input Resistance RI 25 - 1 - MΩ
Output Resistance ROUT See Figure 14, AV = 1, 30MHz 25 - 4 - Ω

Test Circuits and Waveforms

10Ω (NOTE 2)
+6V
+
0.1µF 4.7µF (TANT.)
-

7
GEN 50Ω 8
CC 0.001µF
14 + 11
9 CC
SCOPE INPUT
50Ω
CA3450 6

50Ω 20pF 1M
1
3 -
12 16

4 13 OFFSET
5 NULL

10Ω (NOTE 2)
-6V All 0.1µF and 0.001µF supply decoupling capacitors
-
0.1µF 4.7µF (TANT.) are multilayer ceramic chip types.
+

10Ω 51K

MULTILAYER 0.1µF 820pF SILVER MICA

CERAMIC CHIP OR EQUIVALENT
NOTE:
2. A 10Ω, 1/4W supply decoupling resistor is shown in all application circuits of this device. The resistor serves two purposes. First it provides a
means of decoupling the IC directly at its terminal without introducing additional supply resonance due to parallel connected capacitors. Second,
it also provides protection for the device in event of a sustained short circuit applied directly to the output terminals.

FIGURE 1. OPEN LOOP GAIN vs FREQUENCY TEST CIRCUIT

4
 CA3450

Test Circuits and Waveforms (Continued)

0pF (AV = 10)
GEN 5pF (AV = 1)
50Ω
10Ω
9 +6V
+
0.1µF 4.7µF (TANT.)
11 -
14 + 8
7
50Ω
CA3450 6

15

3 - 12
5 13
2 10
CABLE CABLE
LENGTH 4 LENGTH
1M 1M

10Ω
-6V
450Ω
-
0.1µF 4.7µF (TANT.)
FOR AV = 10 3 6 +

50Ω
TEKTRONIX 2465
OSCILLOSCOPE
50Ω 50Ω

FIGURE 2. UNITY GAIN AND X10 NON-INVERTING AMPLIFIER/AND SLEW RATE TEST CIRCUIT

Transient Response Waveforms

FIGURE 3. TRANSIENT RESPONSE WAVEFORM FIGURE 4. SLEW RATE WAVEFORM

5
 CA3450

Test Circuits and Waveforms (Continued)

11
2V STEP
54Ω +6V 10
2-10pF
9
10Ω
8
CC 11
0.01 7
9 8 µF

BITS
INPUT 6
511Ω 7
3 - 5
174 SIMULATED 4
CA3450 6
Ω TWO
50 3
14 + Ω TRANSMISSION
12 LINE
2
4 11 1
15 20 25 30 35 40 45 50
5
ALL RESISTORS SETTLING TIME TO ±1/2LSB (ns)
MULTILAYER ARE 1%
CERAMIC CHIP 10Ω FIGURE 6. ACCURACY IN BITS AS A FUNCTION OF SETTLING
0.1µF TIME
-6V
MEASUREMENT
82.5Ω POINT 82.5Ω

2 10 15 0.5kΩ 10kΩ 0.5kΩ

2-HP-5082-2835
1 16
DIODES

4
V-
FIGURE 5. CIRCUIT USED TO MEASURE SETTLING TIME FIGURE 7. NULLING CIRCUIT FOR THE CA3450

5pF
10Ω
+6V
MODULATED 11
STAIRCASE 0.1µF +
INPUT SIGNAL 9 - 4.7µF
14 + 8 SHIELDED CABLE
7
75Ω 75Ω 1VP-P
CA3450 6

15 75Ω

3 - 12 220Ω

5 13 TEKTRONIX VM700A
NTSC TEST SET
2 10
4

10Ω
-6V 220Ω
0.1µF 4.7µF

FIGURE 8. CONFIGURATION USED TO MEASURE DIFFERENTIAL GAIN AND PHASE

6
 CA3450

Test Circuits and Waveforms (Continued)

+8V
10Ω
0.001µF

7
75Ω, 1VP-P
14 8
VIDEO INPUT
+
75Ω 10Ω
11
5pF CA3450 6 16
FLASH A/D
9 INPUT
- 390Ω 21
3 12
0.001µF
4 13
5

10Ω 750Ω 110Ω

-4V 0.1µF

0V TO -10V OFFSET
SOURCE, RS <10Ω

FIGURE 9. TYPICAL HIGH BANDWIDTH X5 AMPLIFIER FOR DRIVING THE CA3318 FLASH A/D

Typical Performance Curves

60 10
CLOSED LOOP GAIN (dB)

RL = 50Ω, || 20pF AV = 1
55 -85 CC = 5pF
50 CC = 0pF, TA = 25oC -100
VS = ±6V
PHASE ANGLE (DEGREES)

0
OPEN LOOP GAIN (dB)

45 -115
40 -130 CC = 7pF
35 -145
-10
30 35o MARGIN -160
CC = 5pF
25 -175

PHASE (DEGREES)
0
20 -190
45
15 -205 CC = 7pF
10 PHASE -220 90
5 SHIFT -235
135
0 -250
-5 AOL -265 180

1 10 100 1000 1 10 100 300

FREQUENCY (MHz) FREQUENCY (MHz)

FIGURE 10. BODE PLOT FOR THE CA3450 FIGURE 11. CLOSED LOOP GAIN AND PHASE vs FREQUENCY

7
 CA3450

Typical Performance Curves (Continued)

30

EQUIVALENT INPUT NOISE VOLTAGE (nV/√Hz)

AV = 10
CLOSED LOOP GAIN (dB)

20

GAIN 100

10 0

PHASE (DEGREES)
PHASE
45
10
0 90

135

-10 180 1
1 10 100 300 101 102 103 104 105 106
FREQUENCY (MHz) FREQUENCY (MHz)

FIGURE 12. CLOSED LOOP GAIN AND PHASE vs FREQUENCY FIGURE 13. EQUIVALENT INPUT NOISE vs FREQUENCY

100 10.0
AV = 10, CC = 0pF
90 9.0 RL = 660Ω || 20pF
OUTPUT VOLTAGE SWING (VP-P)
RL = 75Ω || 20pF
80 8.0
OUTPUT RESISTANCE (Ω)

70 7.0
RL = 50Ω || 20pF
60 6.0

50 5.0

40 4.0

30 3.0

20 2.0

10 1.0

0 0.0
1 10 100 200 1 10 100 300
FREQUENCY (MHz) FREQUENCY (MHz)

FIGURE 14. OUTPUT RESISTANCE vs FREQUENCY FIGURE 15. OUTPUT VOLTAGE vs FREQUENCY

Metallization Mask Layout

0 10 20 30 40 50 60 70 80 90 100 106
66
60 Dimensions in parenthesis are in millimeters and are derived
from the basic inch dimensions as indicated. Grid graduations
50 are in mils (10-3 inch).
40 The photographs and dimensions of each CMOS chip represent
66 a chip when it is part of the wafer. When the wafer is cut into
30 (1.676) chips, the angle of cleavage may vary with respect to the chip
face for different chips. The actual dimensions of the isolated
20
chip, therefore, may differ slightly from the nominal dimensions
10 shown. The user should consider a tolerance of -3mils to +6mils
applicable to the nominal dimensions shown.
0
106
(2.692)