Escolar Documentos
Profissional Documentos
Cultura Documentos
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User Guide
V0.1
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Explore
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Explore reserves the right to make changes without further notice to any products herein to improve reliability, function or design.
Explore does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it
convey any license under its patent rights nor the rights of others. Explore products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Explore product could create a situation where personal injury or death may occur. Should
Buyer purchase or use Explore products for any such unintended or unauthorized application, Buyer shall indemnify and hold Explore
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Explore was negligent regarding the design or manufacture of the part.
Oct/18/2011
Initial Version
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0.1
Description of Changes
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Revision
Date
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Version
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Revision History
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Section 1 Introduction
1.1 Overview
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EP92A2E is an HDMI 1.4a 3-IN 1-OUT Repeater/Switch/MCU combo suitable for Home Theater
application. The on-chip HDMI/HDCP/CEC controller makes the user very easy to use the chip. It
manages HDMI and HDCP automatically without the need for user to develop firmware. The CEC
Controller provides the CEC physical layer transceiver and handles the protocol layer automatically. The
chip supports 3 HDMI input ports (Port 0, Port 1 and Port 2) where Port 0 and Port 1 input to an HDMI
Repeater and Port 2 input to an HDMI Switch. The HDMI Repeater supports HDCP decryption, audio
outputs, audio inputs and HDCP re-encryption. The HDMI Switch supports TMDS switching and DDC
switching. The chip supports ARC (Audio Return Channel) RX and is compliant with HDMI 1.4a. The
chip supports SD/HD/DSD Audio in IIS and SPDIF format. The chip supports HD and 3-D Video up to
225 Mhz TMDS clock. The chip also supports 2 ports of on-chip EDID RAM and Power Regulator to save
system cost.
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1.2 Features
On-chip HDMI/HDCP controller which manages HDMI and HDCP automatically without the
need for user to develop firmware
On-chip CEC controller which provides CEC Physical Layer Transceiver and handle the Protocol
Layer without the need for user to develop firmware
On-chip HDMI Receiver and Transmitter core which are compliant with HDMI 1.4a specification
On-chip HDCP Engine which supports Repeater and is compliant with HDCP 1.3 specification
On-chip Audio Decoder which support 8-channel IIS/DSD and SPDIF audio outputs
Audio source for Repeater output can be from a regenerated LPCM audio source or the original
audio from the selected Repeater input port.
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Section 2 Overview
2.1 Chip Block Diagram
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MCU_RSTb
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MCU
(64K ROM, 3K RAM)
(GPIO x 24)
MCU_XIN
CEC/GPIOs
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MCU_OP
HDMI/HDCP/CEC
CONTROLLER
Int
2-In 1-Out Switch
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Co
TX0+/TX1+/TX2+/TXC+/-
MCLK
IIS_SCK
IIS_WS
IIS_SD*/DSD*
EDID 0
ARC
RX
Power
Regulator
REG_VO1
REG_VO2
MUX
SPDIF
HEAC+/IIS_SCK_IN
IIS_WS_IN
IIS_SD_IN
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REG_VIN
IIS/SPDIF/DSD/HBR
HDMI
RX
Input
Port 0
Audio
Processor
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EDID 1
HDCP RX
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HDMI
RX
Input
Port 1
RX01+/RX11+/RX21+/RXC1+/DDC1_SDA
DDC1_SCL
R_SEL[1]
HDCP TX
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HDMI
RX
Input
Port 2
R_SEL[0]
RX00+/RX10+/RX20+/RXC0+/DDC0_SDA
DDC0_SCL
DDCT_SDA
DDCT_SCL
no
RX02+/RX12+/RX22+/RXC2+/-
ch
DDC2_SDA
DDC2_SCL
HDMI
REPEATER & SWITCH
HDMI TX
Registers
&
Control Logic
R_SEL[1]
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DDCR_SCL
DDCR_SDA
SCL2/SCL3
SDA2/SDA3
INTb
X_IN
RSTb
MCU_XOUT
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
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IIS_SD0
IIS_WS
IIS_SCK
MCLK
SPDIF
VDD18
VSSE
PLL_XFC_A
VDD_PLL
X_IN
EXT_RSTb
INTb
IIS_SD1
IIS_SD2
IIS_SD3
REG_VO2
REG_VO1
REG_VIN
COMR
AVSS
TX2+
TX2AVDD18
TX1+
TX1AVSS
TX0+
TX0AVDD18
TXC+
TXCAVSS
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MCU_P30
MCU_P31
MCU_P34
MCU_P35
MCU_P36
MCU_P37
VSSE
MCU_RSTb
MCU_P45
MCU_OP
AVDD
RXC0RXC0+
AVSS
RX00RX00+
AVDD33
RX10RX10+
AVDD
RX20RX20+
AVDD
RXC1RXC1+
AVSS
RX01RX01+
AVDD33
RX11RX11+
AVDD
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64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
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97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SDA2/SDA3
SCL2/SCL3
VSSE
VDD18
IIS_SCK_IN
IIS_WS_IN
IIS_SD_IN
VDDE
ARC+
ARCVSSE
MCU_XIN
MCU_XOUT
MCU_VDD
MCU_P20
MCU_P21
MCU_P22
MCU_P23
MCU_P24
MCU_P25
MCU_P26
MCU_P27
VSSE
MCU_P10
MCU_P11
MCU_P12
MCU_P13
MCU_P14
MCU_P70
MCU_P71
MCU_P40
MCU_P41
PVSS
PVDD18
SWING
DDCR_SCL
DDCT_SCL
DDC2_SCL
DDCR_SDA
DDCT_SDA
DDC2_SDA
VDDE
DDC1_SCL
DDC1_SDA
DDC0_SCL
DDC0_SDA
VSSE
AVDD
RXC2RXC2+
AVSS
RX02RX02+
AVDD33
RX12RX12+
AVDD
RX22RX22+
AVSS
EXT_RES
AVSS
RX21+
RX21-
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Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open.
In/Out
RXC0-
IN
Description
Differential Clock Input Pair for HDMI Input Port 0
RXC0+
IN
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Name
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RX00-
IN
RX00+
IN
IN
IN
RX20-
IN
RX20+
IN
Int
RX10RX10+
IN
IN
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RXC1RXC1+
IN
IN
RX11-
IN
RX11+
IN
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RX01RX01+
IN
IN
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RX21RX21+
IN
IN
RX02-
IN
RX02+
IN
RX22RX22+
IN
IN
IN
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EXT_RES
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TXC-
OUT
TXC+
OUT
TX0-
OUT
TX0+
OUT
OUT
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In/Out
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Name
OUT
OUT
SWING
Analog
Voltage Swing Adjust for HDMI Output. A resistor should tie this
pin to PVDD18. This resistance determines the amplitude of the
voltage swing. 390 is recommended.
COMR
Analog
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TX2TX2+
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Description
ARC+/-
IN/OUT
no
Name
MCLK
OUT
Description
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In/Out
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Name
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IIS_SCK
IIS_WS
IIS SCK output for IIS audio port. Sampling clock output for DSD.
OUT
OUT
OUT
OUT
SPDIF
OUT
SPDIF output.
DSD audio output port 2 (Left Channel).
IIS_SCK_IN
IN
IIS_WS_IN
IN
IIS_SD_IN
IN
IIS_SD1
IIS_SD2
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IIS_SD3
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IIS_SD0
OUT
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INTb
OUT
Interrupt signal. Asserted when interrupt requests occur. This pin is open drain
output when programmed as active low and external pull-up resistor is needed.
This pin is push-pull when programmed as active high. Connect this pin to the
GPIO pin of the HDMI controller externally.
SCL2/SCL3
IO
SCL signal for HDMI and HDCP Control Logic. Connect this pin to the GPIO pin
of the HDMI controller with pull up resistor externally.
SDA2/SDA3
IO
SDA signal for HDMI and HDCP Control Logic. Connect this pin to the GPIO pin
of the HDMI controller with pull up resistor externally.
DDC0_SCL
IN
DDC0_SDA
IO
DDC1_SCL
IN
DDC1_SDA
IO
DDC2_SCL
IN
DDC2_SDA
IO
DDCR_SCL
IN
DDCR_SDA
IO
DDCT_SCL
OUT
DDCT_SDA
IO
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In/Out
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Name
In/Out
X_IN
Analog
External Crystal Input, 18.432 Mhz. Connect this pin to the GPIO pin of the HDMI
controller externally.
PLL_XFC_A
Analog
EXT_RSTb
IN
REG_VIN
PWR
REG_VO1
OUT
REG_VO2
OUT
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MCU_XIN
Description
IN
External Reset (active low) with on-chip pull-up. When this pin is asserted low, the HDMI
controller is totally reset.
IN
IN
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External Reset input (Active Low) with internal weak pull-up. Connect this pin to
the GPIO pin of the HDMI controller externally.
In/Out
MCU_OP
Description
Te
Name
Name
MCU_XOUT
OUT
P2[7:0]
IN/OUT
Co
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In/Out
Description
P1[4:0]
IN/OUT
GPIO port 1 or Keyboard Interrupt inputs with internal 20K pull-up to VDD
P3[7:4, 1:0]
OD
IN/OUT
P4[5, 1:0]
IN/OUT
P7[1:0]
IN/OUT
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AVDD
PWR
Description
HDMI Receiver Analog Power (1.8V)
Int
Name
PWR
PWR
AVDD18
PWR
PVDD18
PWR
AVSS, PVSS
GND
Analog Ground
VDDE
PWR
VSSE
GND
I/O Ground
VDD
PWR
VSS
GND
Logic Ground
VDD_PLL
GND
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PVDD
AVDD33
GND
GND
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VSS_PLL
MCU_VDD
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NOTES:
1. Customer shall follow the pre-defined I/O pins application which shown in reference circuit for the correct operation of this chip.
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Vcc33
-0.3
Vcc18
-0.3
Vcc_REG
-0.3
VI
Input Voltage
-0.3
VO
Output Voltage
-0.3
TJ
Junction Temperature
TSTG
Storage Temperature
JA
JC
Typ
Max
4.0
Units
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Min
5.7
Vcc33 + 0.3
Vcc33 + 0.3
125
125
39.9
C/W
13.1
C/W
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Parameter
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NOTES:
1. Analyzed by FEM (Finite Element Modeling) method with chip mounted on 4-layers PCB.
Min
Typ
Max
Units
Vcc33
3.14
3.3
3.6
Vcc18
1.71
1.8
1.98
Vcc_REG
4.5
5.0
5.5
VCCN
-0.3
100
mVp-p
TA
70
Te
Parameter
25
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Max
Units
2.6
3.6
1.45
1.98
30
mA
IREG_VO2
20
mA
VIH
VIL
VREG_VO1
VREG_VO2
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IREG_VO1
Parameter
Conditions
Min
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Symbol
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DC Digital I/O Specifications (under normal operating conditions unless otherwise specified)
Typ
2.0
V
0.8
11
VOL
IOL
2.4
0.4
High Impedance
-10
10
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uA
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VOH
Parameter
Conditions
VOD
Differential Voltage
Single ended peak to peak amplitude
RLOAD = 50 ohm
RSWING = 390 ohm
VDOH
IDOS
Typ
Max
Units
510
550
590
mV
AVCC
uA
3V3
150
uA
1V8
20
uA
3V3
18
uA
1V8
20
uA
3V3
85
mA
1V8
454
mA
RSEN_DIS = 0
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1080p Resolution
(12-bit)
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RSEN_DIS = 1
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ICCD
Min
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Power-Down Current2
(25C Ambient,
IPD
Int
Symbol
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1 Guaranteed by design.
2 Assumes all HDMI/DVI I/O ports are not connected and all digital inputs are silent.
or
D
Symbol
Conditions
Min
Typ
Max
Units
0.4
Tbit
TCCS
1.0
Tpixel
0.3
Tbit
225
MHz
TIJIT
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TDPS
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FCIP
2,3
25
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NOTES:
1. Guaranteed by design.
2. Jitter defines as per DVI 1.0 Specification, Section 4.6 Jitter Specification.
3. Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electronic Measurement Procedures
12
Parameter
Conditions
Min
Typ
SLHT
CLOAD = 5pF,
RLOAD = 50 ohm,
REXT_SWING = 270 ohm
170
200
SHLT
CLOAD = 5pF,
RLOAD = 50 ohm,
REXT_SWING = 270 ohm
170
Max
Units
230
ps
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230
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200
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I2S Audio AC Specifications (under normal operating conditions unless otherwise specified)
Parameter
Conditions
Tsck
CL = 10pF
Tsck_d
CL = 10pF
40%
60%
Tsck
Tsck_h
CL = 10pF
40%
60%
Tsck
Tsck_l
CL = 10pF
40%
60%
Tsck
Tiis_s
CL = 10pF
40%
Tsck
Tiis_h
CL = 10pF
40%
Tsck
Min
Typ
Max
Units
Tsck
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Symbol
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SPDIF Audio AC Specifications (under normal operating conditions unless otherwise specified)
Parameter
Conditions
Tspdif
CL = 10pF
Tspdif_d
CL = 10pF
Min
Typ
Max
1
90%
Units
UI
110%
UI
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Symbol
13
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HBR (True HD High Bit Rate) audio is output from IIS pins as shown in the following figure:
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2nd16 bits
9th16 bits
IIS_SD1
3rd 16 bits
4th16 bits
11th 16 bits
IIS_SD2
5th16 bits
6th 16 bits
13th 16 bits
IIS_SD3
7th 16 bits
8th 16 bits
15th 16 bits
10th 16 bits
12th16 bits
Int
1st 16 bits
14th16 bits
16th16 bits
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IIS_SD0
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IIS_WS
(WS_POL = 0)
15
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Appendix A Package
65
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96
D
D1
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64
97
DETAIL A
date code
Int
E1
E
0.25
EP92A2E
GAUGE PLANE
SEATING PLANE
lot number
33
log
128
IDENT
no
32
ch
0.05
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A2
DETAIL "A"
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SYMBOLS
MIN.
NOM.
MAX.
A
A1
A2
0.05
1.35
0.1
1.40
1.6
0.15
1.45
or
D
0.13
0.09
0.23
0.20
C
D
16.00 BSC
D1
0.45
0"
16.00 BSC
14.00 BSC
0.40 BSC
0.60
1.00 REF
3.5"
0.75
7"
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E1
14.00 BSC
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0.16
-
NOTES:
1. JEDEC OUTLINE : N/A
2. DIMENSIONS D1 AND E1 DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION IS
0.25mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08mm.
17
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This application note describes the guideline for the system designer to follow while preparing
the application circuit and PCB layout in order to achieve the best performance of the EP92A2E.
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For receiver input, each differential pair shall be routed symmetrically. Also, the best performance
will be expected if the differential pair is equal length. The maximum difference of the trace length
between D+ and D- (intra-pair) is 12 mil.
The receiver module can tolerate the skew among different pairs (inter-pair skew). Anyway, user
can limit the maximum difference of the trace length among different pairs (inter-pair) to 150 mil.
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The transmitter uses the new AC-coupling mechanism at its differential data output. The block diagram of
the recommended transmitter output connection is shown in the following figure.
Rs=0
or
D
D0-
ESD
DIODE
Rs=0
100nF
Rs=0
ESD
DIODE
D0+
100nF
Rs=0
ESD
DIODE
D1-
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D1+
CK+
Rp=499
COMR
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EP92A2E
HDMI CONNECTOR
100nF
D2-
Te
D2+
ESD
DIODE
ch
The 100nF capacitor to implement the AC-coupling mechanism is needed for the EP92A2E TMDS
differential data output. The differential clock output still keeps the DC-coupling mechanism.
The 499 (Rp) pull down resistor for each differentail data output signal is needed for keeping the
DC voltage to the TMDS connector output to be 3V3.
In order to provide the higher level of the ESD protection in the HDMI TX output, a serial resistor
(Rs) can be added between the external ESD device and the silicon HDMI transmitter output pad.
The typical value of the serial resistor could be set to 0 first.
For transmitter output, each differential data pair shall be routed symmetrically. The best
performance will be expected if the differential data pairs are equal length. The maximum trace
difference will depends on the connected receiver characteristics. In practice, try to minimize of the
trace length differences of the intra-pair and inter-pairs of the differential data lines.
For the best intra-pair skew between the single-ended CLK+ output and single-ended CLK- output,
it is recommended to route the CLK+ with the trace length longer than CLK- for 400 mil to 600 mil.
Keep the area of the CLK+ and CLK- current loop to have the minimum area while routing the
additional trace of the CLK+ signal.
Minimize the length from the HDMI TX pins to the HDMI connector. If possible, keep the length
less than 1500 mil.
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The EP92A2E embeds two regulators to generate 3V3 and 1V8 voltage for its own use. The output of the
embedded regulator can not be used for the other purpose. The regulator input is supplied from the +5V
of the HDMI input connector. The low ESR capacitor shall be used and placed closely to the regulator
output pin. The minimum capacitance of the low ESR capacitor is 1uF. The schotty diodes are needed to
isolate the possible reverse current among different supplied power.
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In order to provide a desirable return path for current, the solid ground plane is necessary. Also,
connect the power and ground pins and all bypass capacitors to the appropriate power and ground
plane with a via. Via is suggested to be as fat and as short as possible in order to reduce the
inductance.
Place one 0.1uF capacitor as close as possible between each power pin and ground. A bulk
decoupling capacitor should be placed on the sub-plane of the power. Additional capacitors may be
needed depending on the PCB design.
Control the PCB impedance of all differential traces (both receiver and transmitter) to be 100.
This will be one of the critical points for the system performance at very high frequency operation.
Following items are listed based on our experience:
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If possible, the differential traces shall be routed on the TOP layer and the continuous ground
plane shall be placed beneath the differential traces. The discontinuous ground plane will
degrade the high speed differential signal integrity.
The ground traces stay with the differential traces on the same layer are not suggested.
Keep any TTL signals away from the differential traces as far as possible.
Avoid the differential traces cornering, crossing and the through holes.
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Choose the discrete ESD protection devices with the very low capacitance, the Semtech
RClamp0524P or CMD (California Micro Devices) CM2020 is recommended. Place the ESD
devices close to the HDMI connector for the best performance.
TTL
> 2S
D1
D0
> 3S
CLK
TTL
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