Chapter 3

Number Representation
and
Arithmetic Circuits

Binary numbers
Unsigned numbers
all bits represent the magnitude of a positive integer

Signed numbers
left-most bit represents the sign of a number

Table 3.1. Numbers in different systems.

x
+y

0
+0

0
+1

1
+0

1
+1

c s

0 0

0 1

0 1

1 0

Carry

Sum

(a) The four possible cases

Carry
c

Sum

x
0

(b) Truth table

x

s
HA

y
c

(c) Circuit

(d) Graphical symbol

Figure 3.1. Half-adder.

Bit position i

Figure 3.2. Addition of multibit numbers

xi yi
ci
ci xi yi

1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0
1
1
1

0
1
1
0
1
0
0
1

01

11

si

00

10
1

s i = x i y i c i
xi yi
ci

00

01

(a) Truth table

10

0
1

11

ci + 1 = xi yi + xici + yici

(b) Karnaugh maps

xi
yi

si

ci

ci + 1

(c) Circuit

Figure 3.3. Full-adder.

ci
xi
yi

s
HA

HA

si
ci + 1

(a) Block diagram

ci

si

xi
yi
ci + 1

(b) Detailed diagram

Figure 3.4. A decomposed implementation of the full-adder circuit.

xn 1

cn

x1

yn 1

cn

FA

sn 1
MSB position

c2

y1

x0

y0

c1
FA

FA

s1

s0
LSB position

Figure 3.5. An n-bit ripple-carry adder.

c0

x7

x0

A : a7

a0

y7

y0

c7
s7

s0

0
x8 x7
c8

P = 3 A : P9

x0

y8 y7

y0

s8

s0

P8

P0

(a) Naive approach

A : a7

0
x8
c8

P = 3 A : P9

x1 x0

a0

0
y8 y7

y0

s8

s0

P8

P0

(b) Efficient design

Figure 3.6. Circuit that multiplies an eight-bit

unsigned number by 3.

bn 1

b1

b0

b1

b0

Magnitude
MSB

(a) Unsigned number

bn 1 bn 2

Sign
0 denotes +
1 denotes

Magnitude
MSB

(b) Signed number

Figure 3.7. Formats for representation of integers.

Negative numbers can be represented in following ways:

Sign and magnitude
1s complement
2s complement

1s complement
Let K be the negative equivalent of an n-bit positive number P.

Then, in 1s complement representation K is obtained by

subtracting P from 2n 1, namely
K = (2n 1) P

This means that K can be obtained by inverting all bits of P.

2s complement
Let K be the negative equivalent of an n-bit positive number P.

Then, in 2s complement representation K is obtained by

subtracting P from 2n , namely
K = 2n P

Deriving 2s complement
For a positive n-bit number P, let K1 and K2 denote its 1s
and 2s complements, respectively.
K1 = (2n 1) P
K2 = 2n P
Since K2 = K1 + 1, it is evident that in a logic circuit the 2s
complement can computed by inverting all bits of P and then
adding 1 to the resulting 1s-complement number.

Table 3.2. Interpretation of four-bit signed integers.

(+ 5)
+ (+ 2)
(+ 7)

0101
+0010
0111

( 5 )
+ (+2)
(- 3 )

1010
+0010
1100

(+ 5)
+ ( 2)
(+ 3)

0101
+1101
10010
1
0011

(5 )
+ (2 )
(7 )

1010
+1101
1 0111
1
1000

Figure 3.8. Examples of 1s complement addition.

( + 5)
+ ( + 2)

0101
+ 0010

(5)
+ ( + 2)

1011
+ 0010

( + 7)

0111

(3)

1101

( + 5)
+ (2)

0101
+ 1110

(5)
+ (2)

1011
+ 1110

( + 3)

10011

(7)

11 0 0 1

ignore

ignore

Figure 3.9. Examples of 2s complement addition.

( + 5)
( + 2)

0101
0010

( + 3)

0101
+ 1110
10011

ignore

(5)
( + 2)

1011
0010

(7)

1011
+ 1110
11001

ignore
( + 5)
(2)

0101
1110

( + 7)
(5)
(2)
(3)

0101
+ 0010
0111

1011
1110

1011
+ 0010
1101

Figure 3.10. Examples of 2s complement subtraction.

Graphical interpretation of four-bit 2s complement numbers

yn 1

y1

y0
Add Sub
control

xn 1

x1

cn

x0

c0

n-bit adder

sn 1

s1

s0

Figure 3.12. Adder/subtractor unit.

( + 7)
+ ( + 2)

0111
+ 0010

(7)
+ ( + 2)

1001
+ 0010

( + 9)

1001
c4 = 0
c3 = 1

(5)

1011
c4 = 0
c3 = 0

( + 7)
+ ( 2)

0111
+ 1110

(7)
+ (2)

1001
+ 1110

( + 5)

10101
c4 = 1
c3 = 1

(9)

10 1 1 1
c4 = 1
c3 = 0

Figure 3.13. Examples of determination of overflow.

x1

g1

y1

x0

p1

g0

y0

p0

c1

c2

Stage 1

c0

Stage 0
s1

s0

Figure 3.14. A ripple-carry adder based on Expression 3.3.

x1

y1

x0

x0

g1

p1

y0

y0

g0

p0

c0
c2

c1

s1

s0

Figure 3.15. The first two stages of a carry-lookahead adder.

x31 24

c32

x15 8

y31 24

Block
3

s31 24

c24

c16

y15 8

Block
1

s15 8

x7 0

c8

y7 0

Block
0

s7 0

Figure 3.16. A hierarchical carry-lookahead adder with

ripple-carry between blocks.

c0

x31 24 y31 24

Block
3

x15 8

y15 8

x7 0

Block
1

c24

G3 P3

Block
0

G1 P1

s31 24

c32

G0 P0

s15 8

c16

y7 0

s7 0

c8

Second-level lookahead

Figure 3.17. A hierarchical carry-lookahead adder.

c0

Figure 3.34. Multiplication of unsigned numbers.

Figure 3.35. A 4x4 multiplier circuit.

Multiplicand M
Multiplier Q

(+14)
(+11)

Partial product 0

0 00 1 1 1 0
+ 001110

Partial product 1

0010101
+ 000000

Partial product 2

00 0 1 0 1 0
+ 00 1 1 1 0

Partial product 3
Product P

01110
x 01011

00 1 0 0 1 1
+ 000000
(+154)

0010011010

(a) Positive multiplicand

Multiplicand M
Multiplier Q

( 14)
(+11)

Partial product 0

1 11 0 0 1 0
+ 11 0 0 1 0

Partial product 1

11 0 1 0 1 1
+ 00 0 0 0 0

Partial product 2

11 1 0 1 0 1
+ 11 0 0 1 0

Partial product 3
Product P

10010
01011

11 0 1 1 0 0
+ 000000
( 154)

1101100110

(b) Negative multiplicand

Figure 3.36. Multiplication of signed numbers.

Convert (14959)10

Remainder
14959 16
934 16
58 16
3 16

=
=
=
=

934
58
3
0

6
10
3

Hex digit
15
F
6
A
3

LSB

MSB

Result is (3A6F)16

Figure 3.42. Conversion from decimal to hexadecimal.

Figure 3.45. A comparator circuit.