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2, FEBRUARY 2014

increase due to the TSV effect is called the efficiency. In Table II, the

average wire lengths of the 2-D and 3-D ICs for a different number of

gates, addressed in [18], have been gathered and compared to the wire

lengths predicted by PPCIDF. From Table II, we realize that under

the above-mentioned test conditions, we have achieved an accuracy

of about 92% for the wire length prediction. Moreover, an increase

of 16% in wire length due to TSV (the efficiency) is considerable.

The wire length increase due to the TSV is later used for power

prediction of TSVs [employing (21)].

IV. C ONCLUSION

In this brief, we first introduced a novel and accurate method for

the prediction of the power, including crosstalk-induced power, in

coupled interconnects. By using an elegant PPC for calibrating the

output data of the PPCIDF, we improved the accuracy of the predicted

data. Secondly, we addressed a solution approach to add the impact

of the TSVs, on the power prediction of 3-D ICs of periodic/regular

structures. The contribution of TSVs on increasing both the power

consumption and the wire length (only inside 3-D), for the examined

benchmarks, was observed to be 16%, compared to when the PPC

was not used.

443

P. Sharma, Accurate predictive interconnect modeling for system-level

design, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 4,

pp. 679684, Apr. 2010.

[15] D. H. Kim, S. Mukhopadhyay, and S. K. Lim, Through-silicon-via

aware interconnect prediction and optimization for 3-D stacked ICs, in

Proc. Syst. Level Interconnect Predict. Conf., San Francisco, CA, USA,

Jun. 2009, pp. 8592.

[16] A. Atghiaee, N. Masoumi, and S. Rabiee TSV-aware IDF-based

power prediction for FPGA, in Proc. SPI Conf., Hildesheim, Germany,

May 2010, pp. 2124.

[17] J. W. Joyner, Opportunities and limitations of 3-D integration for

interconnect design, Ph.D. dissertation, Dept. Electr. Eng. Comput. Sci.,

Georgia Inst. Technol., Atlanta, GA, USA, 2003.

[18] D. Stroobandt and H. V. Marck, Efficient representation of interconnection length distributions using generating polynomials, in Proc. Syst.Level Interconnect Predict. Conf., San Diego, CA, USA, Apr. 2000,

pp. 99105.

[19] D. H. Kim and S. K. Lim, Through-silicon-via-aware delay and power

prediction model for buffered interconnects in 3-D ICs, in Proc. Syst.Level Interconnect Predict. Conf., Anaheim, CA, USA, Jun. 2010,

pp. 2532.

[20] A. Atghiaee and N. Masoumi, A predictive and accurate interconnect

density function: The core of a novel interconnect-centric prediction

engine, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19,

no. 9, pp. 17041717, Sep. 2011.

R EFERENCES

[1] G. Katti, M. Stucchi, J. V. Olmen, K. D. Meyer, and W. Dehaene,

Through-silicon-via capacitance reduction technique to benefit 3-D IC

performance, IEEE Electron Device Lett., vol. 31, no. 6, pp. 549551,

Jun. 2010.

[2] M. Haselman and S. Hauck, The future of integrated circuits: A survey

of nanoelectronics, Proc. IEEE, vol. 98, no. 1, pp. 1138, Jan. 2010.

[3] A. Atghiaee and N. Masoumi, Interconnect-induced effects on highspeed submicron ADC and clocking scheme, Sensors Transducers J.,

vol. 80, no. 6, pp. 12571263, Jun. 2007.

[4] J. M. Dias Pereira, O. Postalche, and P. M. B. Silva Girao, PDFbased progressive polynomial calibration method for smart sensors linearization, IEEE Trans. Instrum. Meas., vol. 58, no. 9,

pp. 32453252, Sep. 2009.

[5] P. Christie and D. Stroobandt, The interpretation and application of

Rents rule, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8,

no. 12, pp. 639648, Dec. 2000.

[6] P. Christie and J. P. de Gyvez, Pre-layout prediction of interconnect

manufacturability, in Proc. Syst. Level Interconnect Predict. Conf.,

Sonoma, CA, USA, Apr. 2001, pp. 167173.

[7] J. Wang, P. Ghanta, and S. Vrudhula, Stochastic analysis of interconnect performance in the presence of process variations, in Proc. Int.

Conf. Comput. Aided Design Conf., Washington, DC, USA, Nov. 2004,

pp. 880886.

[8] A. Atghiaee and N. Masoumi, Predictive estimation for distribution of

interconnects, in Proc. SPI Conf., May 2008, pp. 14.

[9] S. Das, A. P. Chandrakasan, and R. Reif, Calibration of Rents rule

models for 3-D integrated circuits, IEEE Trans. Very Large Scale Integr.

(VLSI) Syst., vol. 12, no. 4, pp. 359366, Apr. 2004.

[10] A. K. Palit, V. Meyer, W. Anheier, and J. Schloeffel, ABCD modeling

of crosstalk coupling noise to analyze the signal integrity losses on the

victim interconnect in DSM chips, in Proc. VLSID Conf., Jan. 2005,

pp. 354359.

[11] L. L. Vijaykrishnan, N. Kandemir, and M. Irwin, A crosstalk aware

interconnect with variable cycle transmission, in Proc. Design, Autom.

Test Eur. Conf., Feb. 2004, pp. 102107.

[12] A. Atghiaee and N. Masoumi, Nano-scale early-design-stage prediction for crosstalk-induced power, in Proc. Int. Nanoelectron. Conf.,

Jan. 2010, pp. 2124.

[13] S. Roy and A. Dounavis, Closed-form delay and crosstalk models for

RLC on-chip interconnects using a matrix rational approximation, IEEE

Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 28, no. 10,

pp. 14811492, Oct. 2009.

With Applications in Analog Signal Processing

Cosmin Popa

Abstract This brief presents two original implementations of

improved accuracy current-mode multiplier/divider circuits. Besides the

advantage of their simplicity, these original multiplier/divider structures

present the advantage of very small linearity errors that can be obtained

as a result of the proposed design techniques (0.75% and 0.9%,

respectively, for an extended range of the input currents). The original

multiplier/divider circuits permit a facile reconfiguration, the presented

structures representing the functional basis for implementing complex

function synthesizer circuits. The proposed computational structures

are designed for implementing in 0.18-m CMOS technology, with a

low-voltage operation (a supply voltage of 1.2 V). The circuits power

consumptions are 60 and 75 W, respectively, while their frequency

bandwidths are 79.6 and 59.7 MHz, respectively.

Index Terms Analog signal processing, current-mode operation,

functional core, multiplier, reconfigurable circuits.

I. I NTRODUCTION

Signal processing circuits find a multitude of applications in

many domains such as telecommunications, medical equipment,

hearing devices, and disk drives [1][4], the preference for an analog

Manuscript received February 1, 2012; revised November 19, 2012;

accepted January 8, 2013. Date of publication January 30, 2013; date of

current version January 17, 2014.

The author is with the Faculty of Electronics, Telecommunications and

Information Technology, University Politehnica of Bucharest, Bucharest

12345, Romania (e-mail: cosmin_popa@yahoo.com).

Color versions of one or more of the figures in this paper are available

online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TVLSI.2013.2239670

1063-8210 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.

See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

444

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014

their low-power operation and high speed that allows a real-time

signal processing.

Multiplier circuits represent intensively used blocks in analog

signal processing structures. The motivation for designing these computational structures is related to their extremely wide range of applications in analog signal processing, such as adaptive equalization,

frequency translation, waveform generation and curve-fitting generators, amplitude modulation, automatic gain control, squaring

and square rooting, rms-dc conversion, neural networks, and VLSI

adaptive filters, or measurement equipment. Based on subthresholdoperated MOS transistors, the realization of multiplier/dividers

[5][10] requires simple architectures.

In order to improve the frequency response of the computational

structures and to increase their 3 dB bandwidth, many analog

signal processing functions can be achieved by exploiting the

squaring characteristic of MOS transistors biased in saturation. In

[11][15], multiplier structures were presented with single-ended

input voltages, the linearization of their characteristics being obtained

using proper squaring relations between the input potentials. In order

to implement the multiplication of two differential-input voltages, in

[16][18] multiplier circuits were described based on mathematical

principles, similar to the methods used for multipliers with singleinput voltages. The biasing of the multiplier differential core at a

current equal to the sum of a constant component and a current

proportional to the square of the differential input voltage was

presented in [19] and [20] and allows us to obtain a linear behavior

of the implemented multiplier circuits. In another class of multipliers

[21][23], currents are used as input variables. In this case, the

designed circuits present the advantage of an independence of the

circuit performances on technological errors. These circuits can

implement, based on the same configuration, both multiplying,

and dividing functions. Multiplier structures were also reported

[24][28] with increased linearity, designed using different

mathematical principles.

multiplying/dividing function, having the advantage of an independence of the output current expression on technological parameters

and of a circuit operation that is not affected by temperature variations. The aspect ratios of MOS transistors from Fig. 1 are as follows:

M1M8 4.5/0.9; M9, M14, M16, M17 5.4/0.9; M10M13, M15

10.8/0.9. The chip area of the multiplier/divider implemented in

0.18-m CMOS technology, shown in Fig. 1, equals approximately

600 m2 (including pads).

B. Second Multiplier/Divider Circuit

The second original realization of the multiplier/divider circuit is

presented in Fig. 2. The equation of the functional loop containing

M1, M2, M4, and M5 gate-source voltages can be expressed as

follows:

(3)

2VGS (I2 ) = VGS (IOUT1 ) + VGS IOUT1 + 2 (I1 + I O )

resulting

IOUT1 = I2

2 (I1 + I O )

4 (I1 + I O )2

.

+

2

16I2

(4)

replacing in (4) the (I1 + I O ) current with (I1 I O ) current. The

expression of the output current of the multiplier/divider circuit from

Fig. 2 is IOUT = IOUT1 IOUT2 +2I O , resulting IOUT = (I O I1 ) /I2 .

The aspect ratios of MOS transistors from Fig. 2 are as

follows: M1M5, M7M11, M13M15, M18M23 4.5/0.9; M6, M12

10.8/0.9; M16, M17 9/0.9. The chip area of the multiplier/divider

implemented in 0.18-m CMOS technology, shown in Fig. 2,

equals approximately 800 m2 (including pads). The negative feedback loops that enforce M4 and M15 transistors and, respectively,

M8 and M18 transistors to have the same current are stable, since

their speed is suitable for obtaining the requested frequency response

for the designed circuits.

C. Errors Introduced by Second-Order Effects

Two original implementations of current-mode multiplier/divider

structures will be presented. The main goal of the proposed designs is

related to the accuracy of implemented functions. The current-mode

approach of the multiplier/divider circuits strongly increases their

frequency response. A further advantage of the independence of the

computational circuits output currents on technological parameters

is that it contributes to an important increase in the accuracy of the

multipliers and dividers. Additionally, the operation of the proposed

circuits is not affected by the temperature variations.

A. First Multiplier/Divider Circuit

The first original proposed implementation of a current-mode

multiplier/divider circuit is presented in Fig. 1.

The equations of the functional loops containing M1, M2, M3,

and M4 gate-source voltages and, respectively, M1, M2, M6, and

M7 gate-source voltages can be expressed as follows:

(1)

2VGS (I2 ) = VGS I D1,2 + VGS I D1,2 + 2 (I1 I O )

resulting, considering the squaring characteristics of MOS transistors

biased in the saturation region

I D1,2 = I2 (I1 I O ) +

(I1 I O )2

.

4I2

(2)

2I O , resulting in IOUT = I O I1 /I2 . So, the circuit implements the

circuits operation are represented by the mismatches, channel effect

modulation, body effect, and mobility degradation. As a result of

these undesired effects, the proper functionality of previous circuits

will be affected by additive errors. The values of these errors are

relatively small (because second-order effects are smaller with a

few order of magnitude than the main squaring characteristic that

models the MOS transistor operation). Additionally, a multitude of

specific design techniques exist that are able to compensate the errors

introduced by the second-order effects. The practical realization of

translinear loops using common-centroid MOS transistors strongly

reduces the errors introduced by the mismatches between the corresponding devices. The design of current mirrors using cascode

configurations allows an important reduction of the errors caused by

the channel length modulation. In this situation, a tradeoff between

the impact of the second-order effects and the minimal value of the

supply voltage must be performed. Because the bulks of an important

number of MOS transistors from Figs. 1 and 2 can be connected to

their source (as a result of the original proposed circuit architectures),

the errors introduced by the bulk effect can be canceled out for these

devices.

D. Small-Signal Frequency Response of Multiplier/Dividers

The multiplier/divider circuit proposed in Fig. 1 is designed for

allowing a high bandwidth. In order to achieve this goal, there exists

a single high-impedance node, noted with A, which will impose the

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014

445

VDD

M9

M17

IOUT

M12

2K

M10

2K

2IO

M11

2K

A

ID1

M3

I2

2K

M15

M13

2K

2IO

IO

M14

K

ID2

2I1

M7

2I1

I1

M2

2(I1 - IO)

M1

Fig. 1.

M4

2IO

2IO

2(I1 + IO)

M5

M16

K

M8

M6

VDD

M20

M13

M21

M16

M15

M14

M23

M22

M17

M18

M19

2IO B

I2

IOUT1

M2

IOUT

A

M3

IOUT2

C

2(I1 + IO)

M4

2(I1 - IO)

M8

M9

M10

M1

M11

M6

Fig. 2.

M5

M7

M12

maximal frequency of operation. The frequency response of the multiplier/divider circuit presented in Fig. 2 is poorer than the frequency

response of the circuit from Fig. 1, because in Fig. 2 there exist three

high-impedance nodes (A, B, and C). As most of the nodes in a circuit

represent low-impedance nodes, it is expected that the proposed

circuits to have relatively high maximal frequencies of operation

(79.6 and 59.7 MHz, respectively, obtained after simulations).

III. S IMULATED R ESULTS

The IOUT (I1 ) simulation for the first multiplier/divider circuit

proposed in Fig. 1, for an extended range of I1 current (between

0 and 10 A), is presented in Fig. 3. The I O current is set to be equal

to 40 A, while the I2 current has a parametric variation: 1) 10 A;

2) 20 A; 3) 30 A; and 4) 40 A. A similar simulation was made

for the second circuit from Fig. 2, the results being presented in Fig. 4.

The simulated linearity errors of the IOUT (I1 ) characteristic for

the multiplier/divider circuits are shown in Fig. 5 (for the first

circuit) and Fig. 6 (for the second circuit), respectively. The MULT

error is defined as the difference between the ideal linear characteristic of the multiplier/divider structure and its real characteristic,

implemented using the original proposed computational structure.

Taking into account PVT and Monte Carlo analysis (performed for

2 standard deviations), the linearity errors of the circuits are smaller

than 0.75% (first multiplier/divider) and smaller than 0.9% (second

multiplier/divider).

The IOUT (I2 ) simulations are presented in Figs. 7 and 8, respectively. The I O current is set to be equal to 10 A, while the I1

current has a parametric variation: 1) 10 A; 2) 20 A; 3) 30 A;

and 4) 40 A. The range of I2 current was chosen to be between

1 A and 10 A.

The simulation of the multiplier/dividers frequency responses

shows a 3 dB bandwidth of approximately 79.6 and 59.7 MHz,

respectively. The transient analysis for the first multiplier/divider

circuit proposed in Fig. 1 is shown in Fig. 9. The I O current is

a sinusoidal current with a frequency of 1 MHz and an amplitude

equal to 200 A, the I1 current is a sinusoidal current having a

frequency of 60 MHz and an amplitude equal to 300 A, while I2 is

a constant current equal to 300 A. A similar simulation is made in

Fig. 10 for the second multiplier/divider, I O and I2 currents having

the same form and I1 being a sinusoidal current with a frequency of

45 MHz. The simulations were made using the BSIM4 model, associated with a 0.18-m CMOS process, MOS active devices having

f T = 3.5 GHz.

Comparing with alternative implementations in 0.35-m CMOS

technology of the proposed multiplier/divider structures, some

important advantages can be achieved. The supply voltage can be

decreased from 3 to 1.2 V, correlated with a relatively important

decrease of the circuits power consumption. Additionally, the

circuits bandwidths can be increased by their implementation in

0.18-m CMOS technology.

446

Fig. 3.

Fig. 4.

Fig. 5.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014

Fig. 7.

Fig. 8.

Fig. 9.

Fig. 10.

Fig. 6.

reported in the previous works and the multiplier/divider circuits in

Figs. 1 and 2 is presented in Table I.

The proposed multiplier/divider structures have the most important

advantages, such as the smallest linearity error and an increased band-

designed for implementing in 0.18-m CMOS technology, being

supplied at 1.2 V. If the range of input currents is limited to 05 A,

the power consumptions of both proposed multiplier/divider circuits

(60 and 75 W, respectively) are smaller than the power consumption of most previously

reported circuits. The input referred noise

is smaller than 0.6 V/ Hz for both proposed multiplier/divider

structures.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014

447

TABLE I

C OMPARISON B ETWEEN THE P ROPOSED M ULTIPLIER /D IVIDER C IRCUITS AND P REVIOUS R EPORTED W ORKS

Reference no./Parameter

[9]

[10]

[14]

[15]

[16]

[17]

[22]

[23]

[25]

[26]

[28]

Fig. 1 (this brief)

Fig. 2 (this brief)

Technology

[m]

0.8

0.35

Supply

Voltage [V]

0.75

2

5

0.35

0.35

0.35

0.35

1.5

1.2

3.3

3.3

0.25

0.18

0.18

0.18

1

1

1.2

1.2

Linearity

Error [%]

2

0.9

1

1

1.15

1.1

1

0.75

0.9

IV. C ONCLUSION

This brief presented two original improved accuracy multiplier/divider circuits. The current-mode operation of the proposed

computational structures further increases the circuits accuracy,

while the removal of the impact of temperature variations on the

circuits operation additionally contributes to the increase of the

multiplier/dividers performances. The proposed structures have

extremely low linearity errors (0.75% and 0.9%, respectively). The

minimal value for the supply voltage of 1.2 V was obtained for

implementing the proposed computational structures in 0.18-m

CMOS technology and was correlated with the model parameters

associated with this technology. It is possible to also implement

the proposed circuits in processes of 40 or 28 nm, having much

lower values of the threshold voltages and, in consequence,

allowing a much smaller value of the minimal supply voltage

(even less than 1 V). Another important factor that contributes

to the small value of the minimal supply voltage is represented

by the proposed architectures of the multiplier/divider circuits,

compatible with low-voltage operation (avoiding any cascode stages

and having a current-mode operation). The circuits bandwidth are

79.6 and 59.7 MHz, respectively, while their power consumptions

are extremely low (60 and 75 W, respectively).

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Bandwidth [MHz]

5.5

18 700

0.2

130

290

4.3

240

340

44.9

41.8

5

16

326

588

60

75

600

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59.7

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- boylestad electronics multiple choice q&a chapter (6)Enviado porDenaiya Watton Leeh
- Technical Product Guide for Tri GPEnviado porjuandals
- Linearity and Analog Performance Analysis of Double Gate Tunnel FET: Effect of Temperature and Gate StackEnviado porAnonymous e4UpOQEP
- Beta Multiplier based current referenceEnviado porSrikanth Reddy Paramaiahgari
- BCD Lite Data SheetEnviado porAnonymous YDF1ID15zJ
- 22nd DecemberEnviado porMuhammad Mansoor
- Regras de Projeto AMS CMOS 0.35Enviado porBárbara Britto
- 7_RFEnviado porsaleemnasir2k7154
- Analysis & Design of low Power Dynamic latched Double-Tail ComparatorEnviado porIJSTE
- DE_Ch8-wmEnviado porMahmood Kohansal
- cmos.pdfEnviado porMonirul Ahmed
- ChemSocRev(39)2643Enviado porronbinye
- Nov 2011 JBV SubrahmanyamEnviado porAakash Sheelvant
- Dll Jia Cheng 200512 PhdEnviado porfrostyfoley
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